target/linux/mediatek/patches-4.19/0227-arm-dts-Add-Unielec-U7623-DTS.patch

   1 From 004eb24e939b5b31f828333f37fb5cb2a877d6f2 Mon Sep 17 00:00:00 2001
   2 From: Kristian Evensen <kristian.evensen@gmail.com>
   3 Date: Sun, 17 Jun 2018 14:41:47 +0200
   4 Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
   5
   6 ---
   7  arch/arm/boot/dts/Makefile                         |   1 +
   8  .../dts/mt7623a-unielec-u7623-02-emmc-512M.dts     |  18 +
   9  .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi    | 366 +++++++++++++++++++++
  10  3 files changed, 385 insertions(+)
  11  create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
  12  create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  13
  14 Index: linux-4.19.57/arch/arm/boot/dts/Makefile
  15 ===================================================================
  16 --- linux-4.19.57.orig/arch/arm/boot/dts/Makefile
  17 +++ linux-4.19.57/arch/arm/boot/dts/Makefile
  18 @@ -1193,6 +1193,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  19         mt7623a-rfb-nand.dtb \
  20         mt7623n-rfb-emmc.dtb \
  21         mt7623n-bananapi-bpi-r2.dtb \
  22 +       mt7623a-unielec-u7623-02-emmc-512M.dtb \
  23         mt8127-moose.dtb \
  24         mt8135-evbp1.dtb
  25  dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
  26 Index: linux-4.19.57/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
  27 ===================================================================
  28 --- /dev/null
  29 +++ linux-4.19.57/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
  30 @@ -0,0 +1,18 @@
  31 +/*
  32 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
  33 + *
  34 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  35 + */
  36 +
  37 +/dts-v1/;
  38 +#include "mt7623a-unielec-u7623-02-emmc.dtsi"
  39 +
  40 +/ {
  41 +       model = "UniElec U7623-02 eMMC (512M RAM)";
  42 +       compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623";
  43 +
  44 +       memory@80000000 {
  45 +               device_type = "memory";
  46 +               reg = <0 0x80000000 0 0x20000000>;
  47 +       };
  48 +};
  49 Index: linux-4.19.57/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  50 ===================================================================
  51 --- /dev/null
  52 +++ linux-4.19.57/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  53 @@ -0,0 +1,366 @@
  54 +/*
  55 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
  56 + *
  57 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  58 + */
  59 +
  60 +#include <dt-bindings/input/input.h>
  61 +#include "mt7623.dtsi"
  62 +#include "mt6323.dtsi"
  63 +
  64 +/ {
  65 +       compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
  66 +
  67 +       aliases {
  68 +               serial2 = &uart2;
  69 +       };
  70 +
  71 +       chosen {
  72 +               bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs";
  73 +               stdout-path = "serial2:115200n8";
  74 +       };
  75 +
  76 +       cpus {
  77 +               cpu@0 {
  78 +                       proc-supply = <&mt6323_vproc_reg>;
  79 +               };
  80 +
  81 +               cpu@1 {
  82 +                       proc-supply = <&mt6323_vproc_reg>;
  83 +               };
  84 +
  85 +               cpu@2 {
  86 +                       proc-supply = <&mt6323_vproc_reg>;
  87 +               };
  88 +
  89 +               cpu@3 {
  90 +                       proc-supply = <&mt6323_vproc_reg>;
  91 +               };
  92 +       };
  93 +
  94 +       reg_1p8v: regulator-1p8v {
  95 +               compatible = "regulator-fixed";
  96 +               regulator-name = "fixed-1.8V";
  97 +               regulator-min-microvolt = <1800000>;
  98 +               regulator-max-microvolt = <1800000>;
  99 +               regulator-boot-on;
 100 +               regulator-always-on;
 101 +       };
 102 +
 103 +       reg_3p3v: regulator-3p3v {
 104 +               compatible = "regulator-fixed";
 105 +               regulator-name = "fixed-3.3V";
 106 +               regulator-min-microvolt = <3300000>;
 107 +               regulator-max-microvolt = <3300000>;
 108 +               regulator-boot-on;
 109 +               regulator-always-on;
 110 +       };
 111 +
 112 +       reg_5v: regulator-5v {
 113 +               compatible = "regulator-fixed";
 114 +               regulator-name = "fixed-5V";
 115 +               regulator-min-microvolt = <5000000>;
 116 +               regulator-max-microvolt = <5000000>;
 117 +               regulator-boot-on;
 118 +               regulator-always-on;
 119 +       };
 120 +
 121 +       gpio-keys {
 122 +               compatible = "gpio-keys";
 123 +               pinctrl-names = "default";
 124 +               pinctrl-0 = <&key_pins_a>;
 125 +
 126 +               factory {
 127 +                       label = "factory";
 128 +                       linux,code = <KEY_RESTART>;
 129 +                       gpios = <&pio 256 GPIO_ACTIVE_LOW>;
 130 +               };
 131 +       };
 132 +
 133 +       leds {
 134 +               compatible = "gpio-leds";
 135 +               pinctrl-names = "default";
 136 +               pinctrl-0 = <&led_pins_unielec>;
 137 +
 138 +               led3 {
 139 +                       label = "u7623-01:green:led3";
 140 +                       gpios = <&pio 14 GPIO_ACTIVE_LOW>;
 141 +                       default-state = "off";
 142 +               };
 143 +
 144 +               led4 {
 145 +                       label = "u7623-01:green:led4";
 146 +                       gpios = <&pio 15 GPIO_ACTIVE_LOW>;
 147 +                       default-state = "off";
 148 +               };
 149 +       };
 150 +
 151 +       mt7530: switch@0 {
 152 +               compatible = "mediatek,mt7530";
 153 +               #address-cells = <1>;
 154 +               #size-cells = <0>;
 155 +       };
 156 +};
 157 +
 158 +&crypto {
 159 +       status = "okay";
 160 +};
 161 +
 162 +&eth {
 163 +       status = "okay";
 164 +
 165 +       gmac0: mac@0 {
 166 +               compatible = "mediatek,eth-mac";
 167 +               reg = <0>;
 168 +               phy-mode = "trgmii";
 169 +
 170 +               fixed-link {
 171 +                       speed = <1000>;
 172 +                       full-duplex;
 173 +                       pause;
 174 +               };
 175 +       };
 176 +
 177 +       mdio: mdio-bus {
 178 +               #address-cells = <1>;
 179 +               #size-cells = <0>;
 180 +               phy5: ethernet-phy@5 {
 181 +                       reg = <5>;
 182 +                       phy-mode = "rgmii-rxid";
 183 +               };
 184 +       };
 185 +};
 186 +
 187 +&mt7530 {
 188 +       compatible = "mediatek,mt7530";
 189 +       #address-cells = <1>;
 190 +       #size-cells = <0>;
 191 +       reg = <0>;
 192 +       pinctrl-names = "default";
 193 +       mediatek,mcm;
 194 +       resets = <&ethsys 2>;
 195 +       reset-names = "mcm";
 196 +       core-supply = <&mt6323_vpa_reg>;
 197 +       io-supply = <&mt6323_vemc3v3_reg>;
 198 +
 199 +       dsa,mii-bus = <&mdio>;
 200 +
 201 +       ports {
 202 +               #address-cells = <1>;
 203 +               #size-cells = <0>;
 204 +               reg = <0>;
 205 +
 206 +               port@0 {
 207 +                       reg = <0>;
 208 +                       label = "lan0";
 209 +                       cpu = <&cpu_port0>;
 210 +               };
 211 +
 212 +               port@1 {
 213 +                       reg = <1>;
 214 +                       label = "lan1";
 215 +                       cpu = <&cpu_port0>;
 216 +               };
 217 +
 218 +               port@2 {
 219 +                       reg = <2>;
 220 +                       label = "lan2";
 221 +                       cpu = <&cpu_port0>;
 222 +               };
 223 +
 224 +               port@3 {
 225 +                       reg = <3>;
 226 +                       label = "lan3";
 227 +                       cpu = <&cpu_port0>;
 228 +               };
 229 +
 230 +               port@4 {
 231 +                       reg = <4>;
 232 +                       label = "wan";
 233 +                       cpu = <&cpu_port0>;
 234 +               };
 235 +
 236 +               cpu_port0: port@6 {
 237 +                       reg = <6>;
 238 +                       label = "cpu";
 239 +                       ethernet = <&gmac0>;
 240 +                       phy-mode = "trgmii";
 241 +
 242 +                       fixed-link {
 243 +                               speed = <1000>;
 244 +                               full-duplex;
 245 +                       };
 246 +               };
 247 +       };
 248 +};
 249 +
 250 +&mmc0 {
 251 +       pinctrl-names = "default", "state_uhs";
 252 +       pinctrl-0 = <&mmc0_pins_default>;
 253 +       pinctrl-1 = <&mmc0_pins_uhs>;
 254 +       status = "okay";
 255 +       bus-width = <8>;
 256 +       max-frequency = <50000000>;
 257 +       cap-mmc-highspeed;
 258 +       vmmc-supply = <&reg_3p3v>;
 259 +       vqmmc-supply = <&reg_1p8v>;
 260 +       non-removable;
 261 +};
 262 +
 263 +&pio {
 264 +       key_pins_a: keys-alt {
 265 +               pins-keys {
 266 +                       pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
 267 +                                <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
 268 +                       input-enable;
 269 +               };
 270 +       };
 271 +
 272 +       led_pins_unielec: leds-unielec {
 273 +               pins-leds {
 274 +                       pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
 275 +                                <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
 276 +               };
 277 +       };
 278 +
 279 +       mmc0_pins_default: mmc0default {
 280 +               pins_cmd_dat {
 281 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 282 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 283 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 284 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 285 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 286 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 287 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 288 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 289 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 290 +                       input-enable;
 291 +                       bias-pull-up;
 292 +               };
 293 +
 294 +               pins_clk {
 295 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 296 +                       bias-pull-down;
 297 +               };
 298 +
 299 +               pins_rst {
 300 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 301 +                       bias-pull-up;
 302 +               };
 303 +       };
 304 +
 305 +       mmc0_pins_uhs: mmc0 {
 306 +               pins_cmd_dat {
 307 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 308 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 309 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 310 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 311 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 312 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 313 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 314 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 315 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 316 +                       input-enable;
 317 +                       drive-strength = <MTK_DRIVE_2mA>;
 318 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 319 +               };
 320 +
 321 +               pins_clk {
 322 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 323 +                       drive-strength = <MTK_DRIVE_2mA>;
 324 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
 325 +               };
 326 +
 327 +               pins_rst {
 328 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 329 +                       bias-pull-up;
 330 +               };
 331 +       };
 332 +
 333 +       pwm_pins_a: pwm@0 {
 334 +               pins_pwm {
 335 +                       pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
 336 +                                <MT7623_PIN_204_PWM1_FUNC_PWM1>,
 337 +                                <MT7623_PIN_205_PWM2_FUNC_PWM2>,
 338 +                                <MT7623_PIN_206_PWM3_FUNC_PWM3>,
 339 +                                <MT7623_PIN_207_PWM4_FUNC_PWM4>;
 340 +               };
 341 +       };
 342 +
 343 +       uart2_pins_b: uart@2 {
 344 +               pins_dat {
 345 +                       pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
 346 +                                <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
 347 +               };
 348 +       };
 349 +
 350 +       pcie_default: pcie_pin_default {
 351 +               pins_cmd_dat {
 352 +                       pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
 353 +                                <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
 354 +                       bias-disable;
 355 +               };
 356 +       };
 357 +};
 358 +
 359 +&pwm {
 360 +       pinctrl-names = "default";
 361 +       pinctrl-0 = <&pwm_pins_a>;
 362 +       status = "okay";
 363 +};
 364 +
 365 +&pwrap {
 366 +       mt6323 {
 367 +               mt6323led: led {
 368 +                       compatible = "mediatek,mt6323-led";
 369 +                       #address-cells = <1>;
 370 +                       #size-cells = <0>;
 371 +
 372 +                       led@0 {
 373 +                               reg = <0>;
 374 +                               label = "led0";
 375 +                               default-state = "off";
 376 +                       };
 377 +               };
 378 +       };
 379 +};
 380 +
 381 +&uart2 {
 382 +       pinctrl-names = "default";
 383 +       pinctrl-0 = <&uart2_pins_b>;
 384 +       status = "okay";
 385 +};
 386 +
 387 +&usb1 {
 388 +       vusb33-supply = <&reg_3p3v>;
 389 +       vbus-supply = <&reg_3p3v>;
 390 +       status = "okay";
 391 +};
 392 +
 393 +&u3phy1 {
 394 +       status = "okay";
 395 +};
 396 +
 397 +&u3phy2 {
 398 +       status = "okay";
 399 +       mediatek,phy-switch = <&hifsys>;
 400 +};
 401 +
 402 +&pcie {
 403 +       pinctrl-names = "default";
 404 +       pinctrl-0 = <&pcie_default>;
 405 +       status = "okay";
 406 +
 407 +       pcie@1,0 {
 408 +               status = "okay";
 409 +       };
 410 +
 411 +       pcie@2,0 {
 412 +               status = "okay";
 413 +       };
 414 +};
 415 +
 416 +&pcie1_phy {
 417 +       status = "okay";
 418 +};
 419 +