target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2021 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "mt7986a.dtsi"
   9
  10 / {
  11         model = "MediaTek MT7986a RFB";
  12         compatible = "mediatek,mt7986a-rfb";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16         };
  17
  18         chosen {
  19                 stdout-path = "serial0:115200n8";
  20         };
  21
  22         memory {
  23                 reg = <0 0x40000000 0 0x40000000>;
  24         };
  25
  26         reg_1p8v: regulator-1p8v {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "fixed-1.8V";
  29                 regulator-min-microvolt = <1800000>;
  30                 regulator-max-microvolt = <1800000>;
  31                 regulator-boot-on;
  32                 regulator-always-on;
  33         };
  34
  35         reg_3p3v: regulator-3p3v {
  36                 compatible = "regulator-fixed";
  37                 regulator-name = "fixed-3.3V";
  38                 regulator-min-microvolt = <3300000>;
  39                 regulator-max-microvolt = <3300000>;
  40                 regulator-boot-on;
  41                 regulator-always-on;
  42         };
  43
  44         reg_5v: regulator-5v {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "fixed-5V";
  47                 regulator-min-microvolt = <5000000>;
  48                 regulator-max-microvolt = <5000000>;
  49                 regulator-boot-on;
  50                 regulator-always-on;
  51         };
  52 };
  53
  54 &eth {
  55         status = "okay";
  56
  57         gmac0: mac@0 {
  58                 compatible = "mediatek,eth-mac";
  59                 reg = <0>;
  60                 phy-mode = "2500base-x";
  61
  62                 fixed-link {
  63                         speed = <2500>;
  64                         full-duplex;
  65                         pause;
  66                 };
  67         };
  68
  69         gmac1: mac@1 {
  70                 compatible = "mediatek,eth-mac";
  71                 reg = <1>;
  72                 phy-mode = "2500base-x";
  73         };
  74
  75         mdio: mdio-bus {
  76                 #address-cells = <1>;
  77                 #size-cells = <0>;
  78         };
  79 };
  80
  81 &wmac {
  82         status = "okay";
  83         pinctrl-names = "default", "dbdc";
  84         pinctrl-0 = <&wf_2g_5g_pins>;
  85         pinctrl-1 = <&wf_dbdc_pins>;
  86 };
  87
  88 &mdio {
  89         phy5: phy@5 {
  90                 compatible = "ethernet-phy-id67c9.de0a";
  91                 reg = <5>;
  92
  93                 reset-gpios = <&pio 6 1>;
  94                 reset-deassert-us = <20000>;
  95         };
  96
  97         phy6: phy@6 {
  98                 compatible = "ethernet-phy-id67c9.de0a";
  99                 reg = <6>;
 100         };
 101
 102         switch: switch@0 {
 103                 compatible = "mediatek,mt7531";
 104                 reg = <31>;
 105                 reset-gpios = <&pio 5 0>;
 106         };
 107 };
 108
 109 &crypto {
 110         status = "okay";
 111 };
 112
 113 &mmc0 {
 114         pinctrl-names = "default", "state_uhs";
 115         pinctrl-0 = <&mmc0_pins_default>;
 116         pinctrl-1 = <&mmc0_pins_uhs>;
 117         bus-width = <8>;
 118         max-frequency = <200000000>;
 119         cap-mmc-highspeed;
 120         mmc-hs200-1_8v;
 121         mmc-hs400-1_8v;
 122         hs400-ds-delay = <0x14014>;
 123         vmmc-supply = <&reg_3p3v>;
 124         vqmmc-supply = <&reg_1p8v>;
 125         non-removable;
 126         no-sd;
 127         no-sdio;
 128         status = "okay";
 129 };
 130
 131 &pcie {
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&pcie_pins>;
 134         status = "okay";
 135 };
 136
 137 &pcie_phy {
 138         status = "okay";
 139 };
 140
 141 &pio {
 142         mmc0_pins_default: mmc0-pins {
 143                 mux {
 144                         function = "emmc";
 145                         groups = "emmc_51";
 146                 };
 147                 conf-cmd-dat {
 148                         pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
 149                                "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
 150                                "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
 151                         input-enable;
 152                         drive-strength = <4>;
 153                         mediatek,pull-up-adv = <1>;     /* pull-up 10K */
 154                 };
 155                 conf-clk {
 156                         pins = "EMMC_CK";
 157                         drive-strength = <6>;
 158                         mediatek,pull-down-adv = <2>;   /* pull-down 50K */
 159                 };
 160                 conf-ds {
 161                         pins = "EMMC_DSL";
 162                         mediatek,pull-down-adv = <2>;   /* pull-down 50K */
 163                 };
 164                 conf-rst {
 165                         pins = "EMMC_RSTB";
 166                         drive-strength = <4>;
 167                         mediatek,pull-up-adv = <1>;     /* pull-up 10K */
 168                 };
 169         };
 170
 171         mmc0_pins_uhs: mmc0-uhs-pins {
 172                 mux {
 173                         function = "emmc";
 174                         groups = "emmc_51";
 175                 };
 176                 conf-cmd-dat {
 177                         pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
 178                                "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
 179                                "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
 180                         input-enable;
 181                         drive-strength = <4>;
 182                         mediatek,pull-up-adv = <1>;     /* pull-up 10K */
 183                 };
 184                 conf-clk {
 185                         pins = "EMMC_CK";
 186                         drive-strength = <6>;
 187                         mediatek,pull-down-adv = <2>;   /* pull-down 50K */
 188                 };
 189                 conf-ds {
 190                         pins = "EMMC_DSL";
 191                         mediatek,pull-down-adv = <2>;   /* pull-down 50K */
 192                 };
 193                 conf-rst {
 194                         pins = "EMMC_RSTB";
 195                         drive-strength = <4>;
 196                         mediatek,pull-up-adv = <1>;     /* pull-up 10K */
 197                 };
 198         };
 199
 200         pcie_pins: pcie-pins {
 201                 mux {
 202                         function = "pcie";
 203                         groups = "pcie_clk", "pcie_wake", "pcie_pereset";
 204                 };
 205         };
 206
 207         spic_pins_g2: spic-pins-29-to-32 {
 208                 mux {
 209                         function = "spi";
 210                         groups = "spi1_2";
 211                 };
 212         };
 213
 214         spi_flash_pins: spi-flash-pins-33-to-38 {
 215                 mux {
 216                         function = "spi";
 217                         groups = "spi0", "spi0_wp_hold";
 218                 };
 219                 conf-pu {
 220                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 221                         drive-strength = <8>;
 222                         mediatek,pull-up-adv = <0>;     /* bias-disable */
 223                 };
 224                 conf-pd {
 225                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 226                         drive-strength = <8>;
 227                         mediatek,pull-down-adv = <0>;   /* bias-disable */
 228                 };
 229         };
 230
 231         uart1_pins: uart1-pins {
 232                 mux {
 233                         function = "uart";
 234                         groups = "uart1";
 235                 };
 236         };
 237
 238         uart2_pins: uart2-pins {
 239                 mux {
 240                         function = "uart";
 241                         groups = "uart2";
 242                 };
 243         };
 244
 245         wf_2g_5g_pins: wf_2g_5g-pins {
 246                 mux {
 247                         function = "wifi";
 248                         groups = "wf_2g", "wf_5g";
 249                 };
 250                 conf {
 251                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 252                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 253                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 254                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 255                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 256                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 257                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 258                         drive-strength = <4>;
 259                 };
 260         };
 261
 262         wf_dbdc_pins: wf_dbdc-pins {
 263                 mux {
 264                         function = "wifi";
 265                         groups = "wf_dbdc";
 266                 };
 267                 conf {
 268                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 269                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 270                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 271                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 272                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 273                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 274                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 275                         drive-strength = <4>;
 276                 };
 277         };
 278 };
 279
 280 &spi0 {
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&spi_flash_pins>;
 283         cs-gpios = <0>, <0>;
 284         #address-cells = <1>;
 285         #size-cells = <0>;
 286         status = "disabled";
 287 };
 288
 289 &spi1 {
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&spic_pins_g2>;
 292         status = "okay";
 293
 294         proslic_spi: proslic_spi@0 {
 295                 compatible = "silabs,proslic_spi";
 296                 reg = <0>;
 297                 spi-max-frequency = <10000000>;
 298                 spi-cpha = <1>;
 299                 spi-cpol = <1>;
 300                 channel_count = <1>;
 301                 debug_level = <4>;       /* 1 = TRC, 2 = DBG, 4 = ERR */
 302                 reset_gpio = <&pio 7 0>;
 303                 ig,enable-spi = <1>;     /* 1: Enable, 0: Disable */
 304         };
 305 };
 306
 307 &gmac1 {
 308         phy-mode = "2500base-x";
 309         phy-connection-type = "2500base-x";
 310         phy-handle = <&phy6>;
 311 };
 312
 313 &switch {
 314         ports {
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317
 318                 port@0 {
 319                         reg = <0>;
 320                         label = "lan1";
 321                 };
 322
 323                 port@1 {
 324                         reg = <1>;
 325                         label = "lan2";
 326                 };
 327
 328                 port@2 {
 329                         reg = <2>;
 330                         label = "lan3";
 331                 };
 332
 333                 port@3 {
 334                         reg = <3>;
 335                         label = "lan4";
 336                 };
 337
 338                 port@4 {
 339                         reg = <4>;
 340                         label = "wan";
 341                 };
 342
 343                 port@5 {
 344                         reg = <5>;
 345                         label = "lan6";
 346
 347                         phy-mode = "2500base-x";
 348                         phy-handle = <&phy5>;
 349                 };
 350
 351                 port@6 {
 352                         reg = <6>;
 353                         ethernet = <&gmac0>;
 354                         phy-mode = "2500base-x";
 355
 356                         fixed-link {
 357                                 speed = <2500>;
 358                                 full-duplex;
 359                                 pause;
 360                         };
 361                 };
 362         };
 363 };
 364
 365 &ssusb {
 366         vusb33-supply = <&reg_3p3v>;
 367         vbus-supply = <&reg_5v>;
 368         status = "okay";
 369 };
 370
 371 &uart0 {
 372         status = "okay";
 373 };
 374
 375 &uart1 {
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&uart1_pins>;
 378         status = "okay";
 379 };
 380
 381 &uart2 {
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&uart2_pins>;
 384         status = "okay";
 385 };
 386
 387 &usb_phy {
 388         status = "okay";
 389 };