target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/clock/mt7622-clk.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include <dt-bindings/power/mt7622-power.h>
  14 #include <dt-bindings/reset/mt7622-reset.h>
  15 #include <dt-bindings/thermal/thermal.h>
  16
  17 / {
  18         compatible = "mediatek,mt7622";
  19         interrupt-parent = <&sysirq>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         cpu_opp_table: opp-table {
  24                 compatible = "operating-points-v2";
  25                 opp-shared;
  26                 opp-300000000 {
  27                         opp-hz = /bits/ 64 <30000000>;
  28                         opp-microvolt = <950000>;
  29                 };
  30
  31                 opp-437500000 {
  32                         opp-hz = /bits/ 64 <437500000>;
  33                         opp-microvolt = <1000000>;
  34                 };
  35
  36                 opp-600000000 {
  37                         opp-hz = /bits/ 64 <600000000>;
  38                         opp-microvolt = <1050000>;
  39                 };
  40
  41                 opp-812500000 {
  42                         opp-hz = /bits/ 64 <812500000>;
  43                         opp-microvolt = <1100000>;
  44                 };
  45
  46                 opp-1025000000 {
  47                         opp-hz = /bits/ 64 <1025000000>;
  48                         opp-microvolt = <1150000>;
  49                 };
  50
  51                 opp-1137500000 {
  52                         opp-hz = /bits/ 64 <1137500000>;
  53                         opp-microvolt = <1200000>;
  54                 };
  55
  56                 opp-1262500000 {
  57                         opp-hz = /bits/ 64 <1262500000>;
  58                         opp-microvolt = <1250000>;
  59                 };
  60
  61                 opp-1350000000 {
  62                         opp-hz = /bits/ 64 <1350000000>;
  63                         opp-microvolt = <1310000>;
  64                 };
  65         };
  66
  67         cpus {
  68                 #address-cells = <2>;
  69                 #size-cells = <0>;
  70
  71                 cpu0: cpu@0 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53", "arm,armv8";
  74                         reg = <0x0 0x0>;
  75                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
  76                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
  77                         clock-names = "cpu", "intermediate";
  78                         operating-points-v2 = <&cpu_opp_table>;
  79                         #cooling-cells = <2>;
  80                         enable-method = "psci";
  81                         clock-frequency = <1300000000>;
  82                 };
  83
  84                 cpu1: cpu@1 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a53", "arm,armv8";
  87                         reg = <0x0 0x1>;
  88                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
  89                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
  90                         clock-names = "cpu", "intermediate";
  91                         operating-points-v2 = <&cpu_opp_table>;
  92                         #cooling-cells = <2>;
  93                         enable-method = "psci";
  94                         clock-frequency = <1300000000>;
  95                 };
  96         };
  97
  98         pwrap_clk: dummy40m {
  99                 compatible = "fixed-clock";
 100                 clock-frequency = <40000000>;
 101                 #clock-cells = <0>;
 102         };
 103
 104         clk25m: oscillator {
 105                 compatible = "fixed-clock";
 106                 #clock-cells = <0>;
 107                 clock-frequency = <25000000>;
 108                 clock-output-names = "clkxtal";
 109         };
 110
 111         psci {
 112                 compatible  = "arm,psci-0.2";
 113                 method      = "smc";
 114         };
 115
 116         reserved-memory {
 117                 #address-cells = <2>;
 118                 #size-cells = <2>;
 119                 ranges;
 120
 121                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 122                 secmon_reserved: secmon@43000000 {
 123                         reg = <0 0x43000000 0 0x30000>;
 124                         no-map;
 125                 };
 126         };
 127
 128         thermal-zones {
 129                 cpu_thermal: cpu-thermal {
 130                         polling-delay-passive = <1000>;
 131                         polling-delay = <1000>;
 132
 133                         thermal-sensors = <&thermal 0>;
 134
 135                         trips {
 136                                 cpu_passive: cpu-passive {
 137                                         temperature = <47000>;
 138                                         hysteresis = <2000>;
 139                                         type = "passive";
 140                                 };
 141
 142                                 cpu_active: cpu-active {
 143                                         temperature = <67000>;
 144                                         hysteresis = <2000>;
 145                                         type = "active";
 146                                 };
 147
 148                                 cpu_hot: cpu-hot {
 149                                         temperature = <87000>;
 150                                         hysteresis = <2000>;
 151                                         type = "hot";
 152                                 };
 153
 154                                 cpu-crit {
 155                                         temperature = <107000>;
 156                                         hysteresis = <2000>;
 157                                         type = "critical";
 158                                 };
 159                         };
 160
 161                         cooling-maps {
 162                                 map0 {
 163                                         trip = <&cpu_passive>;
 164                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 165                                 };
 166
 167                                 map1 {
 168                                         trip = <&cpu_active>;
 169                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 170                                 };
 171
 172                                 map2 {
 173                                         trip = <&cpu_hot>;
 174                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 175                                 };
 176                         };
 177                 };
 178         };
 179
 180         timer {
 181                 compatible = "arm,armv8-timer";
 182                 interrupt-parent = <&gic>;
 183                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 184                               IRQ_TYPE_LEVEL_HIGH)>,
 185                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 186                               IRQ_TYPE_LEVEL_HIGH)>,
 187                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 188                               IRQ_TYPE_LEVEL_HIGH)>,
 189                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 190                               IRQ_TYPE_LEVEL_HIGH)>;
 191         };
 192
 193         infracfg: infracfg@10000000 {
 194                 compatible = "mediatek,mt7622-infracfg",
 195                              "syscon";
 196                 reg = <0 0x10000000 0 0x1000>;
 197                 #clock-cells = <1>;
 198                 #reset-cells = <1>;
 199         };
 200
 201         pwrap: pwrap@10001000 {
 202                 compatible = "mediatek,mt7622-pwrap";
 203                 reg = <0 0x10001000 0 0x250>;
 204                 reg-names = "pwrap";
 205                 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
 206                 clock-names = "spi", "wrap";
 207                 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
 208                 reset-names = "pwrap";
 209                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 210                 status = "disabled";
 211         };
 212
 213         pericfg: pericfg@10002000 {
 214                 compatible = "mediatek,mt7622-pericfg",
 215                              "syscon";
 216                 reg = <0 0x10002000 0 0x1000>;
 217                 #clock-cells = <1>;
 218                 #reset-cells = <1>;
 219         };
 220
 221         scpsys: scpsys@10006000 {
 222                 compatible = "mediatek,mt7622-scpsys",
 223                              "syscon";
 224                 #power-domain-cells = <1>;
 225                 reg = <0 0x10006000 0 0x1000>;
 226                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
 227                              <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
 228                              <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
 229                              <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
 230                 infracfg = <&infracfg>;
 231                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
 232                 clock-names = "hif_sel";
 233         };
 234
 235         cir: cir@10009000 {
 236                 compatible = "mediatek,mt7622-cir";
 237                 reg = <0 0x10009000 0 0x1000>;
 238                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
 239                 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
 240                          <&topckgen CLK_TOP_AXI_SEL>;
 241                 clock-names = "clk", "bus";
 242                 status = "disabled";
 243         };
 244
 245         sysirq: interrupt-controller@10200620 {
 246                 compatible = "mediatek,mt7622-sysirq",
 247                              "mediatek,mt6577-sysirq";
 248                 interrupt-controller;
 249                 #interrupt-cells = <3>;
 250                 interrupt-parent = <&gic>;
 251                 reg = <0 0x10200620 0 0x20>;
 252         };
 253
 254         efuse: efuse@10206000 {
 255                 compatible = "mediatek,mt7622-efuse",
 256                              "mediatek,efuse";
 257                 reg = <0 0x10206000 0 0x1000>;
 258                 #address-cells = <1>;
 259                 #size-cells = <1>;
 260
 261                 thermal_calibration: calib@198 {
 262                         reg = <0x198 0xc>;
 263                 };
 264         };
 265
 266         apmixedsys: apmixedsys@10209000 {
 267                 compatible = "mediatek,mt7622-apmixedsys",
 268                              "syscon";
 269                 reg = <0 0x10209000 0 0x1000>;
 270                 #clock-cells = <1>;
 271         };
 272
 273         topckgen: topckgen@10210000 {
 274                 compatible = "mediatek,mt7622-topckgen",
 275                              "syscon";
 276                 reg = <0 0x10210000 0 0x1000>;
 277                 #clock-cells = <1>;
 278         };
 279
 280         rng: rng@1020f000 {
 281                 compatible = "mediatek,mt7622-rng",
 282                              "mediatek,mt7623-rng";
 283                 reg = <0 0x1020f000 0 0x1000>;
 284                 clocks = <&infracfg CLK_INFRA_TRNG>;
 285                 clock-names = "rng";
 286         };
 287
 288         pio: pinctrl@10211000 {
 289                 compatible = "mediatek,mt7622-pinctrl";
 290                 reg = <0 0x10211000 0 0x1000>,
 291                       <0 0x10005000 0 0x1000>;
 292                 reg-names = "base", "eint";
 293                 gpio-controller;
 294                 #gpio-cells = <2>;
 295                 gpio-ranges = <&pio 0 0 103>;
 296                 interrupt-controller;
 297                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 298                 interrupt-parent = <&gic>;
 299                 #interrupt-cells = <2>;
 300         };
 301
 302         watchdog: watchdog@10212000 {
 303                 compatible = "mediatek,mt7622-wdt",
 304                              "mediatek,mt6589-wdt";
 305                 reg = <0 0x10212000 0 0x800>;
 306         };
 307
 308         rtc: rtc@10212800 {
 309                 compatible = "mediatek,mt7622-rtc",
 310                              "mediatek,soc-rtc";
 311                 reg = <0 0x10212800 0 0x200>;
 312                 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
 313                 clocks = <&topckgen CLK_TOP_RTC>;
 314                 clock-names = "rtc";
 315         };
 316
 317         gic: interrupt-controller@10300000 {
 318                 compatible = "arm,gic-400";
 319                 interrupt-controller;
 320                 #interrupt-cells = <3>;
 321                 interrupt-parent = <&gic>;
 322                 reg = <0 0x10310000 0 0x1000>,
 323                       <0 0x10320000 0 0x1000>,
 324                       <0 0x10340000 0 0x2000>,
 325                       <0 0x10360000 0 0x2000>;
 326         };
 327
 328         auxadc: adc@11001000 {
 329                 compatible = "mediatek,mt7622-auxadc";
 330                 reg = <0 0x11001000 0 0x1000>;
 331                 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
 332                 clock-names = "main";
 333                 #io-channel-cells = <1>;
 334         };
 335
 336         uart0: serial@11002000 {
 337                 compatible = "mediatek,mt7622-uart",
 338                              "mediatek,mt6577-uart";
 339                 reg = <0 0x11002000 0 0x400>;
 340                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 341                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 342                          <&pericfg CLK_PERI_UART0_PD>;
 343                 clock-names = "baud", "bus";
 344                 status = "disabled";
 345         };
 346
 347         uart1: serial@11003000 {
 348                 compatible = "mediatek,mt7622-uart",
 349                              "mediatek,mt6577-uart";
 350                 reg = <0 0x11003000 0 0x400>;
 351                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 352                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 353                          <&pericfg CLK_PERI_UART1_PD>;
 354                 clock-names = "baud", "bus";
 355                 status = "disabled";
 356         };
 357
 358         uart2: serial@11004000 {
 359                 compatible = "mediatek,mt7622-uart",
 360                              "mediatek,mt6577-uart";
 361                 reg = <0 0x11004000 0 0x400>;
 362                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 363                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 364                          <&pericfg CLK_PERI_UART2_PD>;
 365                 clock-names = "baud", "bus";
 366                 status = "disabled";
 367         };
 368
 369         uart3: serial@11005000 {
 370                 compatible = "mediatek,mt7622-uart",
 371                              "mediatek,mt6577-uart";
 372                 reg = <0 0x11005000 0 0x400>;
 373                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 374                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 375                          <&pericfg CLK_PERI_UART3_PD>;
 376                 clock-names = "baud", "bus";
 377                 status = "disabled";
 378         };
 379
 380         pwm: pwm@11006000 {
 381                 compatible = "mediatek,mt7622-pwm";
 382                 reg = <0 0x11006000 0 0x1000>;
 383                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 384                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 385                          <&pericfg CLK_PERI_PWM_PD>,
 386                          <&pericfg CLK_PERI_PWM1_PD>,
 387                          <&pericfg CLK_PERI_PWM2_PD>,
 388                          <&pericfg CLK_PERI_PWM3_PD>,
 389                          <&pericfg CLK_PERI_PWM4_PD>,
 390                          <&pericfg CLK_PERI_PWM5_PD>,
 391                          <&pericfg CLK_PERI_PWM6_PD>;
 392                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
 393                               "pwm5", "pwm6";
 394                 status = "disabled";
 395         };
 396
 397         i2c0: i2c@11007000 {
 398                 compatible = "mediatek,mt7622-i2c";
 399                 reg = <0 0x11007000 0 0x90>,
 400                       <0 0x11000100 0 0x80>;
 401                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 402                 clock-div = <16>;
 403                 clocks = <&pericfg CLK_PERI_I2C0_PD>,
 404                          <&pericfg CLK_PERI_AP_DMA_PD>;
 405                 clock-names = "main", "dma";
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 status = "disabled";
 409         };
 410
 411         i2c1: i2c@11008000 {
 412                 compatible = "mediatek,mt7622-i2c";
 413                 reg = <0 0x11008000 0 0x90>,
 414                       <0 0x11000180 0 0x80>;
 415                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 416                 clock-div = <16>;
 417                 clocks = <&pericfg CLK_PERI_I2C1_PD>,
 418                          <&pericfg CLK_PERI_AP_DMA_PD>;
 419                 clock-names = "main", "dma";
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 status = "disabled";
 423         };
 424
 425         i2c2: i2c@11009000 {
 426                 compatible = "mediatek,mt7622-i2c";
 427                 reg = <0 0x11009000 0 0x90>,
 428                       <0 0x11000200 0 0x80>;
 429                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 430                 clock-div = <16>;
 431                 clocks = <&pericfg CLK_PERI_I2C2_PD>,
 432                          <&pericfg CLK_PERI_AP_DMA_PD>;
 433                 clock-names = "main", "dma";
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 status = "disabled";
 437         };
 438
 439         spi0: spi@1100a000 {
 440                 compatible = "mediatek,mt7622-spi";
 441                 reg = <0 0x1100a000 0 0x100>;
 442                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
 443                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 444                          <&topckgen CLK_TOP_SPI0_SEL>,
 445                          <&pericfg CLK_PERI_SPI0_PD>;
 446                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 status = "disabled";
 450         };
 451
 452         thermal: thermal@1100b000 {
 453                 #thermal-sensor-cells = <1>;
 454                 compatible = "mediatek,mt7622-thermal";
 455                 reg = <0 0x1100b000 0 0x1000>;
 456                 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
 457                 clocks = <&pericfg CLK_PERI_THERM_PD>,
 458                          <&pericfg CLK_PERI_AUXADC_PD>;
 459                 clock-names = "therm", "auxadc";
 460                 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
 461                 reset-names = "therm";
 462                 mediatek,auxadc = <&auxadc>;
 463                 mediatek,apmixedsys = <&apmixedsys>;
 464                 nvmem-cells = <&thermal_calibration>;
 465                 nvmem-cell-names = "calibration-data";
 466         };
 467
 468         btif: serial@1100c000 {
 469                 compatible = "mediatek,mt7622-btif",
 470                              "mediatek,mtk-btif";
 471                 reg = <0 0x1100c000 0 0x1000>;
 472                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
 473                 clocks = <&pericfg CLK_PERI_BTIF_PD>;
 474                 clock-names = "main";
 475                 reg-shift = <2>;
 476                 reg-io-width = <4>;
 477                 status = "disabled";
 478
 479                 bluetooth {
 480                         compatible = "mediatek,mt7622-bluetooth";
 481                         power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
 482                         clocks = <&clk25m>;
 483                         clock-names = "ref";
 484                 };
 485         };
 486
 487         nandc: nfi@1100d000 {
 488                 compatible = "mediatek,mt7622-nfc";
 489                 reg = <0 0x1100D000 0 0x1000>;
 490                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
 491                 clocks = <&pericfg CLK_PERI_NFI_PD>,
 492                          <&pericfg CLK_PERI_SNFI_PD>;
 493                 clock-names = "nfi_clk", "pad_clk";
 494                 ecc-engine = <&bch>;
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 status = "disabled";
 498         };
 499
 500         bch: ecc@1100e000 {
 501                 compatible = "mediatek,mt7622-ecc";
 502                 reg = <0 0x1100e000 0 0x1000>;
 503                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
 504                 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
 505                 clock-names = "nfiecc_clk";
 506                 status = "disabled";
 507         };
 508
 509         nor_flash: spi@11014000 {
 510                 compatible = "mediatek,mt7622-nor",
 511                              "mediatek,mt8173-nor";
 512                 reg = <0 0x11014000 0 0xe0>;
 513                 clocks = <&pericfg CLK_PERI_FLASH_PD>,
 514                          <&topckgen CLK_TOP_FLASH_SEL>;
 515                 clock-names = "spi", "sf";
 516                 #address-cells = <1>;
 517                 #size-cells = <0>;
 518                 status = "disabled";
 519         };
 520
 521         snfi: spi@1100d000 {
 522                 compatible = "mediatek,mt7622-snfi";
 523                 reg = <0 0x1100d000 0 0x1000>;
 524                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
 525                 clocks = <&pericfg CLK_PERI_NFI_PD>,
 526                          <&pericfg CLK_PERI_SNFI_PD>;
 527                 clock-names = "nfi_clk", "spi_clk";
 528                 ecc-engine = <&bch>;
 529                 #address-cells = <1>;
 530                 #size-cells = <0>;
 531                 status = "disabled";
 532         };
 533
 534         spi1: spi@11016000 {
 535                 compatible = "mediatek,mt7622-spi";
 536                 reg = <0 0x11016000 0 0x100>;
 537                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
 538                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 539                          <&topckgen CLK_TOP_SPI1_SEL>,
 540                          <&pericfg CLK_PERI_SPI1_PD>;
 541                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 status = "disabled";
 545         };
 546
 547         uart4: serial@11019000 {
 548                 compatible = "mediatek,mt7622-uart",
 549                              "mediatek,mt6577-uart";
 550                 reg = <0 0x11019000 0 0x400>;
 551                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
 552                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 553                          <&pericfg CLK_PERI_UART4_PD>;
 554                 clock-names = "baud", "bus";
 555                 status = "disabled";
 556         };
 557
 558         audsys: clock-controller@11220000 {
 559                 compatible = "mediatek,mt7622-audsys", "syscon";
 560                 reg = <0 0x11220000 0 0x2000>;
 561                 #clock-cells = <1>;
 562
 563                 afe: audio-controller {
 564                         compatible = "mediatek,mt7622-audio";
 565                         interrupts =  <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
 566                                       <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
 567                         interrupt-names = "afe", "asys";
 568
 569                         clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
 570                                  <&topckgen CLK_TOP_AUD1_SEL>,
 571                                  <&topckgen CLK_TOP_AUD2_SEL>,
 572                                  <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
 573                                  <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
 574                                  <&topckgen CLK_TOP_I2S0_MCK_SEL>,
 575                                  <&topckgen CLK_TOP_I2S1_MCK_SEL>,
 576                                  <&topckgen CLK_TOP_I2S2_MCK_SEL>,
 577                                  <&topckgen CLK_TOP_I2S3_MCK_SEL>,
 578                                  <&topckgen CLK_TOP_I2S0_MCK_DIV>,
 579                                  <&topckgen CLK_TOP_I2S1_MCK_DIV>,
 580                                  <&topckgen CLK_TOP_I2S2_MCK_DIV>,
 581                                  <&topckgen CLK_TOP_I2S3_MCK_DIV>,
 582                                  <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
 583                                  <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
 584                                  <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
 585                                  <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
 586                                  <&audsys CLK_AUDIO_I2SO1>,
 587                                  <&audsys CLK_AUDIO_I2SO2>,
 588                                  <&audsys CLK_AUDIO_I2SO3>,
 589                                  <&audsys CLK_AUDIO_I2SO4>,
 590                                  <&audsys CLK_AUDIO_I2SIN1>,
 591                                  <&audsys CLK_AUDIO_I2SIN2>,
 592                                  <&audsys CLK_AUDIO_I2SIN3>,
 593                                  <&audsys CLK_AUDIO_I2SIN4>,
 594                                  <&audsys CLK_AUDIO_ASRCO1>,
 595                                  <&audsys CLK_AUDIO_ASRCO2>,
 596                                  <&audsys CLK_AUDIO_ASRCO3>,
 597                                  <&audsys CLK_AUDIO_ASRCO4>,
 598                                  <&audsys CLK_AUDIO_AFE>,
 599                                  <&audsys CLK_AUDIO_AFE_CONN>,
 600                                  <&audsys CLK_AUDIO_A1SYS>,
 601                                  <&audsys CLK_AUDIO_A2SYS>;
 602
 603                         clock-names = "infra_sys_audio_clk",
 604                                       "top_audio_mux1_sel",
 605                                       "top_audio_mux2_sel",
 606                                       "top_audio_a1sys_hp",
 607                                       "top_audio_a2sys_hp",
 608                                       "i2s0_src_sel",
 609                                       "i2s1_src_sel",
 610                                       "i2s2_src_sel",
 611                                       "i2s3_src_sel",
 612                                       "i2s0_src_div",
 613                                       "i2s1_src_div",
 614                                       "i2s2_src_div",
 615                                       "i2s3_src_div",
 616                                       "i2s0_mclk_en",
 617                                       "i2s1_mclk_en",
 618                                       "i2s2_mclk_en",
 619                                       "i2s3_mclk_en",
 620                                       "i2so0_hop_ck",
 621                                       "i2so1_hop_ck",
 622                                       "i2so2_hop_ck",
 623                                       "i2so3_hop_ck",
 624                                       "i2si0_hop_ck",
 625                                       "i2si1_hop_ck",
 626                                       "i2si2_hop_ck",
 627                                       "i2si3_hop_ck",
 628                                       "asrc0_out_ck",
 629                                       "asrc1_out_ck",
 630                                       "asrc2_out_ck",
 631                                       "asrc3_out_ck",
 632                                       "audio_afe_pd",
 633                                       "audio_afe_conn_pd",
 634                                       "audio_a1sys_pd",
 635                                       "audio_a2sys_pd";
 636
 637                         assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
 638                                           <&topckgen CLK_TOP_A2SYS_HP_SEL>,
 639                                           <&topckgen CLK_TOP_A1SYS_HP_DIV>,
 640                                           <&topckgen CLK_TOP_A2SYS_HP_DIV>;
 641                         assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
 642                                                  <&topckgen CLK_TOP_AUD2PLL>;
 643                         assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
 644                 };
 645         };
 646
 647         mmc0: mmc@11230000 {
 648                 compatible = "mediatek,mt7622-mmc";
 649                 reg = <0 0x11230000 0 0x1000>;
 650                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 651                 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
 652                          <&topckgen CLK_TOP_MSDC50_0_SEL>;
 653                 clock-names = "source", "hclk";
 654                 status = "disabled";
 655         };
 656
 657         mmc1: mmc@11240000 {
 658                 compatible = "mediatek,mt7622-mmc";
 659                 reg = <0 0x11240000 0 0x1000>;
 660                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 661                 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
 662                          <&topckgen CLK_TOP_AXI_SEL>;
 663                 clock-names = "source", "hclk";
 664                 status = "disabled";
 665         };
 666
 667         ssusbsys: ssusbsys@1a000000 {
 668                 compatible = "mediatek,mt7622-ssusbsys",
 669                              "syscon";
 670                 reg = <0 0x1a000000 0 0x1000>;
 671                 #clock-cells = <1>;
 672                 #reset-cells = <1>;
 673         };
 674
 675         ssusb: usb@1a0c0000 {
 676                 compatible = "mediatek,mt7622-xhci",
 677                              "mediatek,mtk-xhci";
 678                 reg = <0 0x1a0c0000 0 0x01000>,
 679                       <0 0x1a0c4700 0 0x0100>;
 680                 reg-names = "mac", "ippc";
 681                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 682                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
 683                 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
 684                          <&ssusbsys CLK_SSUSB_REF_EN>,
 685                          <&ssusbsys CLK_SSUSB_MCU_EN>,
 686                          <&ssusbsys CLK_SSUSB_DMA_EN>;
 687                 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
 688                 phys = <&u2port0 PHY_TYPE_USB2>,
 689                        <&u3port0 PHY_TYPE_USB3>,
 690                        <&u2port1 PHY_TYPE_USB2>;
 691
 692                 status = "disabled";
 693         };
 694
 695         u3phy: usb-phy@1a0c4000 {
 696                 compatible = "mediatek,mt7622-u3phy",
 697                              "mediatek,generic-tphy-v1";
 698                 reg = <0 0x1a0c4000 0 0x700>;
 699                 #address-cells = <2>;
 700                 #size-cells = <2>;
 701                 ranges;
 702                 status = "disabled";
 703
 704                 u2port0: usb-phy@1a0c4800 {
 705                         reg = <0 0x1a0c4800 0 0x0100>;
 706                         #phy-cells = <1>;
 707                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
 708                         clock-names = "ref";
 709                 };
 710
 711                 u3port0: usb-phy@1a0c4900 {
 712                         reg = <0 0x1a0c4900 0 0x0700>;
 713                         #phy-cells = <1>;
 714                         clocks = <&clk25m>;
 715                         clock-names = "ref";
 716                 };
 717
 718                 u2port1: usb-phy@1a0c5000 {
 719                         reg = <0 0x1a0c5000 0 0x0100>;
 720                         #phy-cells = <1>;
 721                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
 722                         clock-names = "ref";
 723                 };
 724         };
 725
 726         pciesys: pciesys@1a100800 {
 727                 compatible = "mediatek,mt7622-pciesys",
 728                              "syscon";
 729                 reg = <0 0x1a100800 0 0x1000>;
 730                 #clock-cells = <1>;
 731                 #reset-cells = <1>;
 732         };
 733
 734         pcie: pcie@1a140000 {
 735                 compatible = "mediatek,mt7622-pcie";
 736                 device_type = "pci";
 737                 reg = <0 0x1a140000 0 0x1000>,
 738                       <0 0x1a143000 0 0x1000>,
 739                       <0 0x1a145000 0 0x1000>;
 740                 reg-names = "subsys", "port0", "port1";
 741                 #address-cells = <3>;
 742                 #size-cells = <2>;
 743                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
 744                              <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 745                 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
 746                          <&pciesys CLK_PCIE_P1_MAC_EN>,
 747                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 748                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 749                          <&pciesys CLK_PCIE_P0_AUX_EN>,
 750                          <&pciesys CLK_PCIE_P1_AUX_EN>,
 751                          <&pciesys CLK_PCIE_P0_AXI_EN>,
 752                          <&pciesys CLK_PCIE_P1_AXI_EN>,
 753                          <&pciesys CLK_PCIE_P0_OBFF_EN>,
 754                          <&pciesys CLK_PCIE_P1_OBFF_EN>,
 755                          <&pciesys CLK_PCIE_P0_PIPE_EN>,
 756                          <&pciesys CLK_PCIE_P1_PIPE_EN>;
 757                 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
 758                               "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
 759                               "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
 760                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 761                 bus-range = <0x00 0xff>;
 762                 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
 763                 status = "disabled";
 764
 765                 pcie0: pcie@0,0 {
 766                         reg = <0x0000 0 0 0 0>;
 767                         #address-cells = <3>;
 768                         #size-cells = <2>;
 769                         #interrupt-cells = <1>;
 770                         ranges;
 771                         status = "disabled";
 772
 773                         num-lanes = <1>;
 774                         interrupt-map-mask = <0 0 0 7>;
 775                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 776                                         <0 0 0 2 &pcie_intc0 1>,
 777                                         <0 0 0 3 &pcie_intc0 2>,
 778                                         <0 0 0 4 &pcie_intc0 3>;
 779                         pcie_intc0: interrupt-controller {
 780                                 interrupt-controller;
 781                                 #address-cells = <0>;
 782                                 #interrupt-cells = <1>;
 783                         };
 784                 };
 785
 786                 pcie1: pcie@1,0 {
 787                         reg = <0x0800 0 0 0 0>;
 788                         #address-cells = <3>;
 789                         #size-cells = <2>;
 790                         #interrupt-cells = <1>;
 791                         ranges;
 792                         status = "disabled";
 793
 794                         num-lanes = <1>;
 795                         interrupt-map-mask = <0 0 0 7>;
 796                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 797                                         <0 0 0 2 &pcie_intc1 1>,
 798                                         <0 0 0 3 &pcie_intc1 2>,
 799                                         <0 0 0 4 &pcie_intc1 3>;
 800                         pcie_intc1: interrupt-controller {
 801                                 interrupt-controller;
 802                                 #address-cells = <0>;
 803                                 #interrupt-cells = <1>;
 804                         };
 805                 };
 806         };
 807
 808         sata: sata@1a200000 {
 809                 compatible = "mediatek,mt7622-ahci",
 810                              "mediatek,mtk-ahci";
 811                 reg = <0 0x1a200000 0 0x1100>;
 812                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 813                 interrupt-names = "hostc";
 814                 clocks = <&pciesys CLK_SATA_AHB_EN>,
 815                          <&pciesys CLK_SATA_AXI_EN>,
 816                          <&pciesys CLK_SATA_ASIC_EN>,
 817                          <&pciesys CLK_SATA_RBC_EN>,
 818                          <&pciesys CLK_SATA_PM_EN>;
 819                 clock-names = "ahb", "axi", "asic", "rbc", "pm";
 820                 phys = <&sata_port PHY_TYPE_SATA>;
 821                 phy-names = "sata-phy";
 822                 ports-implemented = <0x1>;
 823                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 824                 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
 825                          <&pciesys MT7622_SATA_PHY_SW_RST>,
 826                          <&pciesys MT7622_SATA_PHY_REG_RST>;
 827                 reset-names = "axi", "sw", "reg";
 828                 mediatek,phy-mode = <&pciesys>;
 829                 status = "disabled";
 830         };
 831
 832         sata_phy: sata-phy@1a243000 {
 833                 compatible = "mediatek,generic-tphy-v1";
 834                 #address-cells = <2>;
 835                 #size-cells = <2>;
 836                 ranges;
 837                 status = "disabled";
 838
 839                 sata_port: sata-phy@1a243000 {
 840                         reg = <0 0x1a243000 0 0x0100>;
 841                         clocks = <&topckgen CLK_TOP_ETH_500M>;
 842                         clock-names = "ref";
 843                         #phy-cells = <1>;
 844                 };
 845         };
 846
 847         ethsys: syscon@1b000000 {
 848                 compatible = "mediatek,mt7622-ethsys",
 849                              "syscon";
 850                 reg = <0 0x1b000000 0 0x1000>;
 851                 #clock-cells = <1>;
 852                 #reset-cells = <1>;
 853         };
 854
 855         hsdma: dma-controller@1b007000 {
 856                 compatible = "mediatek,mt7622-hsdma";
 857                 reg = <0 0x1b007000 0 0x1000>;
 858                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
 859                 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
 860                 clock-names = "hsdma";
 861                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 862                 #dma-cells = <1>;
 863         };
 864
 865         eth: ethernet@1b100000 {
 866                 compatible = "mediatek,mt7622-eth",
 867                              "mediatek,mt2701-eth",
 868                              "syscon";
 869                 reg = <0 0x1b100000 0 0x20000>;
 870                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
 871                              <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
 872                              <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 873                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
 874                          <&ethsys CLK_ETH_ESW_EN>,
 875                          <&ethsys CLK_ETH_GP0_EN>,
 876                          <&ethsys CLK_ETH_GP1_EN>,
 877                          <&ethsys CLK_ETH_GP2_EN>,
 878                          <&sgmiisys CLK_SGMII_TX250M_EN>,
 879                          <&sgmiisys CLK_SGMII_RX250M_EN>,
 880                          <&sgmiisys CLK_SGMII_CDR_REF>,
 881                          <&sgmiisys CLK_SGMII_CDR_FB>,
 882                          <&topckgen CLK_TOP_SGMIIPLL>,
 883                          <&apmixedsys CLK_APMIXED_ETH2PLL>;
 884                 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
 885                               "sgmii_tx250m", "sgmii_rx250m",
 886                               "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
 887                               "eth2pll";
 888                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 889                 mediatek,ethsys = <&ethsys>;
 890                 mediatek,sgmiisys = <&sgmiisys>;
 891                 #address-cells = <1>;
 892                 #size-cells = <0>;
 893                 status = "disabled";
 894         };
 895
 896         sgmiisys: sgmiisys@1b128000 {
 897                 compatible = "mediatek,mt7622-sgmiisys",
 898                              "syscon";
 899                 reg = <0 0x1b128000 0 0x3000>;
 900                 #clock-cells = <1>;
 901                 mediatek,physpeed = "2500";
 902         };
 903 };