target/linux/ipq806x/patches-5.4/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch

   1 From c9ecd920324a647bf1f2b47f771c8f599cc7b551 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Sat, 22 Feb 2020 18:02:17 +0100
   4 Subject: [PATCH 2/8] Documentation: cpufreq: add qcom,krait-cache bindings
   5
   6 Document dedicated cpufreq for Krait CPUs.
   7
   8 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
   9 ---
  10  .../bindings/cpufreq/qcom-cpufreq-krait.yaml  | 221 ++++++++++++++++++
  11  1 file changed, 221 insertions(+)
  12  create mode 100644 Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml
  13
  14 --- /dev/null
  15 +++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml
  16 @@ -0,0 +1,221 @@
  17 +# SPDX-License-Identifier: GPL-2.0
  18 +%YAML 1.2
  19 +---
  20 +$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-krait.yaml#
  21 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  22 +
  23 +title: CPU Frequency scaling driver for Krait SoCs
  24 +
  25 +maintainers:
  26 +  - Ansuel Smith <ansuelsmth@gmail.com>
  27 +
  28 +description: |
  29 +  The krait cpufreq driver is a dedicated frequency scaling driver
  30 +  based on cpufreq-dt generic driver that scale L2 cache and the
  31 +  cores. TEST
  32 +
  33 +  The L2 cache is scaled based on the max clk across all cores and
  34 +  the clock is decided based on the opp-level set in the device tree.
  35 +
  36 +  Different core freq can be linked to a specific l2 freq and the driver
  37 +  on frequency change will scale the core and the l2 clk based of the
  38 +  linked freq.
  39 +
  40 +  On Krait SoC is present a bug and on every L2 clk change the driver
  41 +  needs to set the clk to the idle freq before changing it to the new value.
  42 +
  43 +  This requires the qcom cpufreq nvmem driver to parse the different opp
  44 +  core clk and an additional opp table for the l2 scaling.
  45 +
  46 +  If the driver detect broken config (for example missing opp-level) the
  47 +  cpufreq driver skips the l2 scaling
  48 +
  49 +  Referring to this example opp-level can be used to link a range of cpu freq
  50 +  to a specific l2 freq:
  51 +    cpu opp freq 384000000 has opp-level 0
  52 +    l2 opp freq 384000000 has opp-level 0
  53 +    The driver will scale l2 to 384000000
  54 +
  55 +    cpu opp freq 600000000-1000000000 has opp-level 1
  56 +    l2 opp freq 1000000000 has opp-level 1
  57 +    The driver will scale l2 to 1000000000
  58 +
  59 +allOf:
  60 +  - $ref: /schemas/cache-controller.yaml#
  61 +
  62 +select:
  63 +  properties:
  64 +    compatible:
  65 +      items:
  66 +        - enum:
  67 +            - qcom,krait-cache
  68 +
  69 +  required:
  70 +    - compatible
  71 +
  72 +properties:
  73 +  compatible:
  74 +    items:
  75 +      - const: qcom,krait-cache
  76 +      - const: cache
  77 +
  78 +  cache-level:
  79 +    const: 2
  80 +
  81 +  clocks:
  82 +    maxItems: 1
  83 +
  84 +  clock-names:
  85 +    const: l2
  86 +
  87 +  l2-supply: true
  88 +
  89 +  operating-points-v2: true
  90 +
  91 +required:
  92 +  - compatible
  93 +  - cache-level
  94 +  - clocks
  95 +  - clock-names
  96 +  - l2-supply
  97 +  - operating-points-v2
  98 +
  99 +additionalProperties: false
 100 +
 101 +examples:
 102 +  - |
 103 +    cpus {
 104 +      #address-cells = <1>;
 105 +      #size-cells = <0>;
 106 +
 107 +      cpu0: cpu@0 {
 108 +        compatible = "qcom,krait";
 109 +        enable-method = "qcom,kpss-acc-v1";
 110 +        device_type = "cpu";
 111 +        reg = <0>;
 112 +        next-level-cache = <&L2>;
 113 +        qcom,acc = <&acc0>;
 114 +        qcom,saw = <&saw0>;
 115 +        clocks = <&kraitcc 0>, <&kraitcc 4>;
 116 +        clock-names = "cpu", "l2";
 117 +        clock-latency = <100000>;
 118 +        cpu-supply = <&smb208_s2a>;
 119 +        operating-points-v2 = <&opp_table0>;
 120 +        voltage-tolerance = <5>;
 121 +        cooling-min-state = <0>;
 122 +        cooling-max-state = <10>;
 123 +        #cooling-cells = <2>;
 124 +        cpu-idle-states = <&CPU_SPC>;
 125 +      };
 126 +
 127 +      /* ... */
 128 +
 129 +    };
 130 +
 131 +    opp_table0: opp_table0 {
 132 +      compatible = "operating-points-v2-kryo-cpu";
 133 +      nvmem-cells = <&speedbin_efuse>;
 134 +
 135 +      opp-384000000 {
 136 +        opp-hz = /bits/ 64 <384000000>;
 137 +        opp-microvolt-speed0-pvs0-v0 = <1000000>;
 138 +        opp-microvolt-speed0-pvs1-v0 = <925000>;
 139 +        opp-microvolt-speed0-pvs2-v0 = <875000>;
 140 +        opp-microvolt-speed0-pvs3-v0 = <800000>;
 141 +        opp-supported-hw = <0x1>;
 142 +        clock-latency-ns = <100000>;
 143 +        opp-level = <0>;
 144 +      };
 145 +
 146 +      opp-600000000 {
 147 +        opp-hz = /bits/ 64 <600000000>;
 148 +        opp-microvolt-speed0-pvs0-v0 = <1050000>;
 149 +        opp-microvolt-speed0-pvs1-v0 = <975000>;
 150 +        opp-microvolt-speed0-pvs2-v0 = <925000>;
 151 +        opp-microvolt-speed0-pvs3-v0 = <850000>;
 152 +        opp-supported-hw = <0x1>;
 153 +        clock-latency-ns = <100000>;
 154 +        opp-level = <1>;
 155 +      };
 156 +
 157 +      opp-800000000 {
 158 +        opp-hz = /bits/ 64 <800000000>;
 159 +        opp-microvolt-speed0-pvs0-v0 = <1100000>;
 160 +        opp-microvolt-speed0-pvs1-v0 = <1025000>;
 161 +        opp-microvolt-speed0-pvs2-v0 = <995000>;
 162 +        opp-microvolt-speed0-pvs3-v0 = <900000>;
 163 +        opp-supported-hw = <0x1>;
 164 +        clock-latency-ns = <100000>;
 165 +        opp-level = <1>;
 166 +      };
 167 +
 168 +      opp-1000000000 {
 169 +        opp-hz = /bits/ 64 <1000000000>;
 170 +        opp-microvolt-speed0-pvs0-v0 = <1150000>;
 171 +        opp-microvolt-speed0-pvs1-v0 = <1075000>;
 172 +        opp-microvolt-speed0-pvs2-v0 = <1025000>;
 173 +        opp-microvolt-speed0-pvs3-v0 = <950000>;
 174 +        opp-supported-hw = <0x1>;
 175 +        clock-latency-ns = <100000>;
 176 +        opp-level = <1>;
 177 +      };
 178 +
 179 +      opp-1200000000 {
 180 +        opp-hz = /bits/ 64 <1200000000>;
 181 +        opp-microvolt-speed0-pvs0-v0 = <1200000>;
 182 +        opp-microvolt-speed0-pvs1-v0 = <1125000>;
 183 +        opp-microvolt-speed0-pvs2-v0 = <1075000>;
 184 +        opp-microvolt-speed0-pvs3-v0 = <1000000>;
 185 +        opp-supported-hw = <0x1>;
 186 +        clock-latency-ns = <100000>;
 187 +        opp-level = <2>;
 188 +      };
 189 +
 190 +      opp-1400000000 {
 191 +        opp-hz = /bits/ 64 <1400000000>;
 192 +        opp-microvolt-speed0-pvs0-v0 = <1250000>;
 193 +        opp-microvolt-speed0-pvs1-v0 = <1175000>;
 194 +        opp-microvolt-speed0-pvs2-v0 = <1125000>;
 195 +        opp-microvolt-speed0-pvs3-v0 = <1050000>;
 196 +        opp-supported-hw = <0x1>;
 197 +        clock-latency-ns = <100000>;
 198 +        opp-level = <2>;
 199 +      };
 200 +    };
 201 +
 202 +    opp_table_l2: opp_table_l2 {
 203 +      compatible = "operating-points-v2";
 204 +
 205 +      opp-384000000 {
 206 +        opp-hz = /bits/ 64 <384000000>;
 207 +        opp-microvolt = <1100000>;
 208 +        clock-latency-ns = <100000>;
 209 +        opp-level = <0>;
 210 +      };
 211 +      opp-1000000000 {
 212 +        opp-hz = /bits/ 64 <1000000000>;
 213 +        opp-microvolt = <1100000>;
 214 +        clock-latency-ns = <100000>;
 215 +        opp-level = <1>;
 216 +      };
 217 +      opp-1200000000 {
 218 +        opp-hz = /bits/ 64 <1200000000>;
 219 +        opp-microvolt = <1150000>;
 220 +        clock-latency-ns = <100000>;
 221 +        opp-level = <2>;
 222 +      };
 223 +    };
 224 +
 225 +    soc {
 226 +      L2: l2-cache {
 227 +        compatible = "qcom,krait-cache", "cache";
 228 +        cache-level = <2>;
 229 +
 230 +        clocks = <&kraitcc 4>;
 231 +        clock-names = "l2";
 232 +        l2-supply = <&smb208_s1a>;
 233 +        operating-points-v2 = <&opp_table_l2>;
 234 +      };
 235 +    };
 236 +
 237 +...