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ipq806x: remove skeleton definition
[openwrt/staging/zorun.git] / target / linux / ipq806x / files-5.4 / arch / arm / boot / dts / qcom-ipq8064.dtsi
1 /dts-v1/;
2
3 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
4 #include <dt-bindings/mfd/qcom-rpm.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/gpio/gpio.h>
11
12 / {
13 model = "Qualcomm IPQ8064";
14 compatible = "qcom,ipq8064";
15 interrupt-parent = <&intc>;
16
17 #address-cells = <1>;
18 #size-cells = <1>;
19 memory { device_type = "memory"; reg = <0 0>; };
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 compatible = "qcom,krait";
27 enable-method = "qcom,kpss-acc-v1";
28 device_type = "cpu";
29 reg = <0>;
30 next-level-cache = <&L2>;
31 qcom,acc = <&acpu0_aux>;
32 qcom,saw = <&saw0>;
33 clocks = <&kraitcc 0>, <&kraitcc 4>;
34 clock-names = "cpu", "l2";
35 clock-latency = <100000>;
36 cpu-supply = <&smb208_s2a>;
37 operating-points-v2 = <&opp_table0>;
38 voltage-tolerance = <5>;
39 cooling-min-state = <0>;
40 cooling-max-state = <10>;
41 #cooling-cells = <2>;
42 cpu-idle-states = <&CPU_SPC>;
43 };
44
45 cpu1: cpu@1 {
46 compatible = "qcom,krait";
47 enable-method = "qcom,kpss-acc-v1";
48 device_type = "cpu";
49 reg = <1>;
50 next-level-cache = <&L2>;
51 qcom,acc = <&acpu1_aux>;
52 qcom,saw = <&saw1>;
53 clocks = <&kraitcc 1>, <&kraitcc 4>;
54 clock-names = "cpu", "l2";
55 clock-latency = <100000>;
56 cpu-supply = <&smb208_s2b>;
57 operating-points-v2 = <&opp_table0>;
58 voltage-tolerance = <5>;
59 cooling-min-state = <0>;
60 cooling-max-state = <10>;
61 #cooling-cells = <2>;
62 cpu-idle-states = <&CPU_SPC>;
63 };
64
65 L2: l2-cache {
66 compatible = "cache";
67 cache-level = <2>;
68 qcom,saw = <&saw_l2>;
69 };
70
71 qcom,l2 {
72 qcom,l2-rates = <384000000 1000000000 1200000000>;
73 qcom,l2-cpufreq = <384000000 600000000 1200000000>;
74 qcom,l2-volt = <1100000 1100000 1150000>;
75 qcom,l2-supply = <&smb208_s1a>;
76 };
77
78 idle-states {
79 CPU_SPC: spc {
80 compatible = "qcom,idle-state-spc",
81 "arm,idle-state";
82 status = "okay";
83 entry-latency-us = <400>;
84 exit-latency-us = <900>;
85 min-residency-us = <3000>;
86 };
87 };
88 };
89
90 opp_table0: opp_table0 {
91 compatible = "operating-points-v2-qcom-cpu";
92 nvmem-cells = <&speedbin_efuse>;
93
94 opp-384000000 {
95 opp-hz = /bits/ 64 <384000000>;
96 opp-microvolt-speed0-pvs0-v0 = <1000000>;
97 opp-microvolt-speed0-pvs1-v0 = <925000>;
98 opp-microvolt-speed0-pvs2-v0 = <875000>;
99 opp-microvolt-speed0-pvs3-v0 = <800000>;
100 opp-supported-hw = <0x1>;
101 clock-latency-ns = <100000>;
102 };
103
104 opp-600000000 {
105 opp-hz = /bits/ 64 <600000000>;
106 opp-microvolt-speed0-pvs0-v0 = <1050000>;
107 opp-microvolt-speed0-pvs1-v0 = <975000>;
108 opp-microvolt-speed0-pvs2-v0 = <925000>;
109 opp-microvolt-speed0-pvs3-v0 = <850000>;
110 opp-supported-hw = <0x1>;
111 clock-latency-ns = <100000>;
112 };
113
114 opp-800000000 {
115 opp-hz = /bits/ 64 <800000000>;
116 opp-microvolt-speed0-pvs0-v0 = <1100000>;
117 opp-microvolt-speed0-pvs1-v0 = <1025000>;
118 opp-microvolt-speed0-pvs2-v0 = <995000>;
119 opp-microvolt-speed0-pvs3-v0 = <900000>;
120 opp-supported-hw = <0x1>;
121 clock-latency-ns = <100000>;
122 };
123
124 opp-1000000000 {
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt-speed0-pvs0-v0 = <1150000>;
127 opp-microvolt-speed0-pvs1-v0 = <1075000>;
128 opp-microvolt-speed0-pvs2-v0 = <1025000>;
129 opp-microvolt-speed0-pvs3-v0 = <950000>;
130 opp-supported-hw = <0x1>;
131 clock-latency-ns = <100000>;
132 };
133
134 opp-1200000000 {
135 opp-hz = /bits/ 64 <1200000000>;
136 opp-microvolt-speed0-pvs0-v0 = <1200000>;
137 opp-microvolt-speed0-pvs1-v0 = <1125000>;
138 opp-microvolt-speed0-pvs2-v0 = <1075000>;
139 opp-microvolt-speed0-pvs3-v0 = <1000000>;
140 opp-supported-hw = <0x1>;
141 clock-latency-ns = <100000>;
142 };
143
144 opp-1400000000 {
145 opp-hz = /bits/ 64 <1400000000>;
146 opp-microvolt-speed0-pvs0-v0 = <1250000>;
147 opp-microvolt-speed0-pvs1-v0 = <1175000>;
148 opp-microvolt-speed0-pvs2-v0 = <1125000>;
149 opp-microvolt-speed0-pvs3-v0 = <1050000>;
150 opp-supported-hw = <0x1>;
151 clock-latency-ns = <100000>;
152 };
153
154 };
155
156 thermal-zones {
157 tsens_tz_sensor0 {
158 polling-delay-passive = <0>;
159 polling-delay = <0>;
160 thermal-sensors = <&tsens 0>;
161
162 trips {
163 cpu-critical-hi {
164 temperature = <125000>;
165 hysteresis = <2000>;
166 type = "critical_high";
167 };
168
169 cpu-config-hi {
170 temperature = <105000>;
171 hysteresis = <2000>;
172 type = "configurable_hi";
173 };
174
175 cpu-config-lo {
176 temperature = <95000>;
177 hysteresis = <2000>;
178 type = "configurable_lo";
179 };
180
181 cpu-critical-low {
182 temperature = <0>;
183 hysteresis = <2000>;
184 type = "critical_low";
185 };
186 };
187 };
188
189 tsens_tz_sensor1 {
190 polling-delay-passive = <0>;
191 polling-delay = <0>;
192 thermal-sensors = <&tsens 1>;
193
194 trips {
195 cpu-critical-hi {
196 temperature = <125000>;
197 hysteresis = <2000>;
198 type = "critical_high";
199 };
200
201 cpu-config-hi {
202 temperature = <105000>;
203 hysteresis = <2000>;
204 type = "configurable_hi";
205 };
206
207 cpu-config-lo {
208 temperature = <95000>;
209 hysteresis = <2000>;
210 type = "configurable_lo";
211 };
212
213 cpu-critical-low {
214 temperature = <0>;
215 hysteresis = <2000>;
216 type = "critical_low";
217 };
218 };
219 };
220
221 tsens_tz_sensor2 {
222 polling-delay-passive = <0>;
223 polling-delay = <0>;
224 thermal-sensors = <&tsens 2>;
225
226 trips {
227 cpu-critical-hi {
228 temperature = <125000>;
229 hysteresis = <2000>;
230 type = "critical_high";
231 };
232
233 cpu-config-hi {
234 temperature = <105000>;
235 hysteresis = <2000>;
236 type = "configurable_hi";
237 };
238
239 cpu-config-lo {
240 temperature = <95000>;
241 hysteresis = <2000>;
242 type = "configurable_lo";
243 };
244
245 cpu-critical-low {
246 temperature = <0>;
247 hysteresis = <2000>;
248 type = "critical_low";
249 };
250 };
251 };
252
253 tsens_tz_sensor3 {
254 polling-delay-passive = <0>;
255 polling-delay = <0>;
256 thermal-sensors = <&tsens 3>;
257
258 trips {
259 cpu-critical-hi {
260 temperature = <125000>;
261 hysteresis = <2000>;
262 type = "critical_high";
263 };
264
265 cpu-config-hi {
266 temperature = <105000>;
267 hysteresis = <2000>;
268 type = "configurable_hi";
269 };
270
271 cpu-config-lo {
272 temperature = <95000>;
273 hysteresis = <2000>;
274 type = "configurable_lo";
275 };
276
277 cpu-critical-low {
278 temperature = <0>;
279 hysteresis = <2000>;
280 type = "critical_low";
281 };
282 };
283 };
284
285 tsens_tz_sensor4 {
286 polling-delay-passive = <0>;
287 polling-delay = <0>;
288 thermal-sensors = <&tsens 4>;
289
290 trips {
291 cpu-critical-hi {
292 temperature = <125000>;
293 hysteresis = <2000>;
294 type = "critical_high";
295 };
296
297 cpu-config-hi {
298 temperature = <105000>;
299 hysteresis = <2000>;
300 type = "configurable_hi";
301 };
302
303 cpu-config-lo {
304 temperature = <95000>;
305 hysteresis = <2000>;
306 type = "configurable_lo";
307 };
308
309 cpu-critical-low {
310 temperature = <0>;
311 hysteresis = <2000>;
312 type = "critical_low";
313 };
314 };
315 };
316
317 tsens_tz_sensor5 {
318 polling-delay-passive = <0>;
319 polling-delay = <0>;
320 thermal-sensors = <&tsens 5>;
321
322 trips {
323 cpu-critical-hi {
324 temperature = <125000>;
325 hysteresis = <2000>;
326 type = "critical_high";
327 };
328
329 cpu-config-hi {
330 temperature = <105000>;
331 hysteresis = <2000>;
332 type = "configurable_hi";
333 };
334
335 cpu-config-lo {
336 temperature = <95000>;
337 hysteresis = <2000>;
338 type = "configurable_lo";
339 };
340
341 cpu-critical-low {
342 temperature = <0>;
343 hysteresis = <2000>;
344 type = "critical_low";
345 };
346 };
347 };
348
349 tsens_tz_sensor6 {
350 polling-delay-passive = <0>;
351 polling-delay = <0>;
352 thermal-sensors = <&tsens 6>;
353
354 trips {
355 cpu-critical-hi {
356 temperature = <125000>;
357 hysteresis = <2000>;
358 type = "critical_high";
359 };
360
361 cpu-config-hi {
362 temperature = <105000>;
363 hysteresis = <2000>;
364 type = "configurable_hi";
365 };
366
367 cpu-config-lo {
368 temperature = <95000>;
369 hysteresis = <2000>;
370 type = "configurable_lo";
371 };
372
373 cpu-critical-low {
374 temperature = <0>;
375 hysteresis = <2000>;
376 type = "critical_low";
377 };
378 };
379 };
380
381 tsens_tz_sensor7 {
382 polling-delay-passive = <0>;
383 polling-delay = <0>;
384 thermal-sensors = <&tsens 7>;
385
386 trips {
387 cpu-critical-hi {
388 temperature = <125000>;
389 hysteresis = <2000>;
390 type = "critical_high";
391 };
392
393 cpu-config-hi {
394 temperature = <105000>;
395 hysteresis = <2000>;
396 type = "configurable_hi";
397 };
398
399 cpu-config-lo {
400 temperature = <95000>;
401 hysteresis = <2000>;
402 type = "configurable_lo";
403 };
404
405 cpu-critical-low {
406 temperature = <0>;
407 hysteresis = <2000>;
408 type = "critical_low";
409 };
410 };
411 };
412
413 tsens_tz_sensor8 {
414 polling-delay-passive = <0>;
415 polling-delay = <0>;
416 thermal-sensors = <&tsens 8>;
417
418 trips {
419 cpu-critical-hi {
420 temperature = <125000>;
421 hysteresis = <2000>;
422 type = "critical_high";
423 };
424
425 cpu-config-hi {
426 temperature = <105000>;
427 hysteresis = <2000>;
428 type = "configurable_hi";
429 };
430
431 cpu-config-lo {
432 temperature = <95000>;
433 hysteresis = <2000>;
434 type = "configurable_lo";
435 };
436
437 cpu-critical-low {
438 temperature = <0>;
439 hysteresis = <2000>;
440 type = "critical_low";
441 };
442 };
443 };
444
445 tsens_tz_sensor9 {
446 polling-delay-passive = <0>;
447 polling-delay = <0>;
448 thermal-sensors = <&tsens 9>;
449
450 trips {
451 cpu-critical-hi {
452 temperature = <125000>;
453 hysteresis = <2000>;
454 type = "critical_high";
455 };
456
457 cpu-config-hi {
458 temperature = <105000>;
459 hysteresis = <2000>;
460 type = "configurable_hi";
461 };
462
463 cpu-config-lo {
464 temperature = <95000>;
465 hysteresis = <2000>;
466 type = "configurable_lo";
467 };
468
469 cpu-critical-low {
470 temperature = <0>;
471 hysteresis = <2000>;
472 type = "critical_low";
473 };
474 };
475 };
476
477 tsens_tz_sensor10 {
478 polling-delay-passive = <0>;
479 polling-delay = <0>;
480 thermal-sensors = <&tsens 10>;
481
482 trips {
483 cpu-critical-hi {
484 temperature = <125000>;
485 hysteresis = <2000>;
486 type = "critical_high";
487 };
488
489 cpu-config-hi {
490 temperature = <105000>;
491 hysteresis = <2000>;
492 type = "configurable_hi";
493 };
494
495 cpu-config-lo {
496 temperature = <95000>;
497 hysteresis = <2000>;
498 type = "configurable_lo";
499 };
500
501 cpu-critical-low {
502 temperature = <0>;
503 hysteresis = <2000>;
504 type = "critical_low";
505 };
506 };
507 };
508 };
509
510 cpu-pmu {
511 compatible = "qcom,krait-pmu";
512 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
513 IRQ_TYPE_LEVEL_HIGH)>;
514 };
515
516 reserved-memory {
517 #address-cells = <1>;
518 #size-cells = <1>;
519 ranges;
520
521 nss@40000000 {
522 reg = <0x40000000 0x1000000>;
523 no-map;
524 };
525
526 smem: smem@41000000 {
527 reg = <0x41000000 0x200000>;
528 no-map;
529 };
530 };
531
532 clocks {
533 cxo_board {
534 compatible = "fixed-clock";
535 #clock-cells = <0>;
536 clock-frequency = <25000000>;
537 };
538
539 pxo_board {
540 compatible = "fixed-clock";
541 #clock-cells = <0>;
542 clock-frequency = <25000000>;
543 };
544
545 sleep_clk: sleep_clk {
546 compatible = "fixed-clock";
547 clock-frequency = <32768>;
548 #clock-cells = <0>;
549 };
550 };
551
552 fab-scaling {
553 compatible = "qcom,fab-scaling";
554 clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
555 clock-names = "apps-fab-clk", "ddr-fab-clk";
556 fab_freq_high = <533000000>;
557 fab_freq_nominal = <400000000>;
558 cpu_freq_threshold = <1000000000>;
559 };
560
561 firmware {
562 scm {
563 compatible = "qcom,scm-ipq806x";
564 };
565 };
566
567 soc: soc {
568 #address-cells = <1>;
569 #size-cells = <1>;
570 ranges;
571 compatible = "simple-bus";
572
573 lpass@28100000 {
574 compatible = "qcom,lpass-cpu";
575 status = "disabled";
576 clocks = <&lcc AHBIX_CLK>,
577 <&lcc MI2S_OSR_CLK>,
578 <&lcc MI2S_BIT_CLK>;
579 clock-names = "ahbix-clk",
580 "mi2s-osr-clk",
581 "mi2s-bit-clk";
582 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
583 interrupt-names = "lpass-irq-lpaif";
584 reg = <0x28100000 0x10000>;
585 reg-names = "lpass-lpaif";
586 };
587
588 qfprom: qfprom@700000 {
589 compatible = "qcom,qfprom", "syscon";
590 reg = <0x700000 0x1000>;
591 #address-cells = <1>;
592 #size-cells = <1>;
593 status = "okay";
594 tsens_calib: calib@400 {
595 reg = <0x400 0xb>;
596 };
597 tsens_backup: backup@410 {
598 reg = <0x410 0xb>;
599 };
600 speedbin_efuse: speedbin@0c0 {
601 reg = <0x0c0 0x4>;
602 };
603 };
604
605 rpm@108000 {
606 compatible = "qcom,rpm-ipq8064";
607 reg = <0x108000 0x1000>;
608 qcom,ipc = <&l2cc 0x8 2>;
609
610 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-names = "ack",
614 "err",
615 "wakeup";
616
617 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
618 clock-names = "ram";
619
620 #address-cells = <1>;
621 #size-cells = <0>;
622
623 rpmcc: clock-controller {
624 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
625 #clock-cells = <1>;
626 };
627
628 regulators {
629 compatible = "qcom,rpm-smb208-regulators";
630
631 smb208_s1a: s1a {
632 regulator-min-microvolt = <1050000>;
633 regulator-max-microvolt = <1150000>;
634
635 qcom,switch-mode-frequency = <1200000>;
636
637 };
638
639 smb208_s1b: s1b {
640 regulator-min-microvolt = <1050000>;
641 regulator-max-microvolt = <1150000>;
642
643 qcom,switch-mode-frequency = <1200000>;
644 };
645
646 smb208_s2a: s2a {
647 regulator-min-microvolt = < 800000>;
648 regulator-max-microvolt = <1250000>;
649
650 qcom,switch-mode-frequency = <1200000>;
651 };
652
653 smb208_s2b: s2b {
654 regulator-min-microvolt = < 800000>;
655 regulator-max-microvolt = <1250000>;
656
657 qcom,switch-mode-frequency = <1200000>;
658 };
659 };
660 };
661
662 rng@1a500000 {
663 compatible = "qcom,prng";
664 reg = <0x1a500000 0x200>;
665 clocks = <&gcc PRNG_CLK>;
666 clock-names = "core";
667 };
668
669 qcom_pinmux: pinmux@800000 {
670 compatible = "qcom,ipq8064-pinctrl";
671 reg = <0x800000 0x4000>;
672
673 gpio-controller;
674 #gpio-cells = <2>;
675 interrupt-controller;
676 #interrupt-cells = <2>;
677 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
678
679 pcie0_pins: pcie0_pinmux {
680 mux {
681 pins = "gpio3";
682 function = "pcie1_rst";
683 drive-strength = <12>;
684 bias-disable;
685 };
686 };
687
688 pcie1_pins: pcie1_pinmux {
689 mux {
690 pins = "gpio48";
691 function = "pcie2_rst";
692 drive-strength = <12>;
693 bias-disable;
694 };
695 };
696
697 pcie2_pins: pcie2_pinmux {
698 mux {
699 pins = "gpio63";
700 function = "pcie3_rst";
701 drive-strength = <12>;
702 bias-disable;
703 output-low;
704 };
705 };
706
707 spi_pins: spi_pins {
708 mux {
709 pins = "gpio18", "gpio19", "gpio21";
710 function = "gsbi5";
711 drive-strength = <10>;
712 bias-none;
713 };
714 };
715
716 leds_pins: leds_pins {
717 mux {
718 pins = "gpio7", "gpio8", "gpio9",
719 "gpio26", "gpio53";
720 function = "gpio";
721 drive-strength = <2>;
722 bias-pull-down;
723 output-low;
724 };
725 };
726
727 buttons_pins: buttons_pins {
728 mux {
729 pins = "gpio54";
730 drive-strength = <2>;
731 bias-pull-up;
732 };
733 };
734 };
735
736 intc: interrupt-controller@2000000 {
737 compatible = "qcom,msm-qgic2";
738 interrupt-controller;
739 #interrupt-cells = <3>;
740 reg = <0x02000000 0x1000>,
741 <0x02002000 0x1000>;
742 };
743
744 timer@200a000 {
745 compatible = "qcom,kpss-timer",
746 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
747 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
748 IRQ_TYPE_EDGE_RISING)>,
749 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
750 IRQ_TYPE_EDGE_RISING)>,
751 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
752 IRQ_TYPE_EDGE_RISING)>,
753 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
754 IRQ_TYPE_EDGE_RISING)>,
755 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
756 IRQ_TYPE_EDGE_RISING)>;
757 reg = <0x0200a000 0x100>;
758 clock-frequency = <25000000>,
759 <32768>;
760 clocks = <&sleep_clk>;
761 clock-names = "sleep";
762 cpu-offset = <0x80000>;
763 };
764
765 acpu0_aux: clock-controller@2088000 {
766 compatible = "qcom,kpss-acc-v1";
767 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
768 clock-output-names = "acpu0_aux";
769 };
770
771 acpu1_aux: clock-controller@2098000 {
772 compatible = "qcom,kpss-acc-v1";
773 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
774 clock-output-names = "acpu1_aux";
775 };
776
777 l2cc: clock-controller@2011000 {
778 compatible = "qcom,kpss-gcc", "syscon";
779 reg = <0x2011000 0x1000>;
780 clock-output-names = "acpu_l2_aux";
781 };
782
783 kraitcc: clock-controller {
784 compatible = "qcom,krait-cc-v1";
785 #clock-cells = <1>;
786 };
787
788 saw0: regulator@2089000 {
789 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
790 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
791 regulator;
792 };
793
794 saw1: regulator@2099000 {
795 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
796 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
797 regulator;
798 };
799
800 saw_l2: regulator@02012000 {
801 compatible = "qcom,saw2", "syscon";
802 reg = <0x02012000 0x1000>;
803 regulator;
804 };
805
806 sic_non_secure: sic-non-secure@12100000 {
807 compatible = "syscon";
808 reg = <0x12100000 0x10000>;
809 };
810
811 gsbi2: gsbi@12480000 {
812 compatible = "qcom,gsbi-v1.0.0";
813 cell-index = <2>;
814 reg = <0x12480000 0x100>;
815 clocks = <&gcc GSBI2_H_CLK>;
816 clock-names = "iface";
817 #address-cells = <1>;
818 #size-cells = <1>;
819 ranges;
820 status = "disabled";
821
822 syscon-tcsr = <&tcsr>;
823
824 uart2: serial@12490000 {
825 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
826 reg = <0x12490000 0x1000>,
827 <0x12480000 0x1000>;
828 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
830 clock-names = "core", "iface";
831 status = "disabled";
832 };
833
834 i2c@124a0000 {
835 compatible = "qcom,i2c-qup-v1.1.1";
836 reg = <0x124a0000 0x1000>;
837 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
838
839 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
840 clock-names = "core", "iface";
841 status = "disabled";
842
843 #address-cells = <1>;
844 #size-cells = <0>;
845 };
846
847 };
848
849 gsbi4: gsbi@16300000 {
850 compatible = "qcom,gsbi-v1.0.0";
851 cell-index = <4>;
852 reg = <0x16300000 0x100>;
853 clocks = <&gcc GSBI4_H_CLK>;
854 clock-names = "iface";
855 #address-cells = <1>;
856 #size-cells = <1>;
857 ranges;
858 status = "disabled";
859
860 syscon-tcsr = <&tcsr>;
861
862 gsbi4_serial: serial@16340000 {
863 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
864 reg = <0x16340000 0x1000>,
865 <0x16300000 0x1000>;
866 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
868 clock-names = "core", "iface";
869 status = "disabled";
870 };
871
872 i2c@16380000 {
873 compatible = "qcom,i2c-qup-v1.1.1";
874 reg = <0x16380000 0x1000>;
875 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
876
877 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
878 clock-names = "core", "iface";
879 status = "disabled";
880
881 #address-cells = <1>;
882 #size-cells = <0>;
883 };
884 };
885
886 gsbi5: gsbi@1a200000 {
887 compatible = "qcom,gsbi-v1.0.0";
888 cell-index = <5>;
889 reg = <0x1a200000 0x100>;
890 clocks = <&gcc GSBI5_H_CLK>;
891 clock-names = "iface";
892 #address-cells = <1>;
893 #size-cells = <1>;
894 ranges;
895 status = "disabled";
896
897 syscon-tcsr = <&tcsr>;
898
899 uart5: serial@1a240000 {
900 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
901 reg = <0x1a240000 0x1000>,
902 <0x1a200000 0x1000>;
903 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
905 clock-names = "core", "iface";
906 status = "disabled";
907 };
908
909 i2c@1a280000 {
910 compatible = "qcom,i2c-qup-v1.1.1";
911 reg = <0x1a280000 0x1000>;
912 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
913
914 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
915 clock-names = "core", "iface";
916 status = "disabled";
917
918 #address-cells = <1>;
919 #size-cells = <0>;
920 };
921
922 spi@1a280000 {
923 compatible = "qcom,spi-qup-v1.1.1";
924 reg = <0x1a280000 0x1000>;
925 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
926
927 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
928 clock-names = "core", "iface";
929 status = "disabled";
930
931 #address-cells = <1>;
932 #size-cells = <0>;
933 };
934 };
935
936 gsbi7: gsbi@16600000 {
937 status = "disabled";
938 compatible = "qcom,gsbi-v1.0.0";
939 cell-index = <7>;
940 reg = <0x16600000 0x100>;
941 clocks = <&gcc GSBI7_H_CLK>;
942 clock-names = "iface";
943 #address-cells = <1>;
944 #size-cells = <1>;
945 ranges;
946 syscon-tcsr = <&tcsr>;
947
948 gsbi7_serial: serial@16640000 {
949 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
950 reg = <0x16640000 0x1000>,
951 <0x16600000 0x1000>;
952 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
954 clock-names = "core", "iface";
955 status = "disabled";
956 };
957 };
958
959 sata_phy: sata-phy@1b400000 {
960 compatible = "qcom,ipq806x-sata-phy";
961 reg = <0x1b400000 0x200>;
962
963 clocks = <&gcc SATA_PHY_CFG_CLK>;
964 clock-names = "cfg";
965
966 #phy-cells = <0>;
967 status = "disabled";
968 };
969
970 sata: sata@29000000 {
971 compatible = "qcom,ipq806x-ahci", "generic-ahci";
972 reg = <0x29000000 0x180>;
973
974 ports-implemented = <0x1>;
975
976 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
977
978 clocks = <&gcc SFAB_SATA_S_H_CLK>,
979 <&gcc SATA_H_CLK>,
980 <&gcc SATA_A_CLK>,
981 <&gcc SATA_RXOOB_CLK>,
982 <&gcc SATA_PMALIVE_CLK>;
983 clock-names = "slave_face", "iface", "core",
984 "rxoob", "pmalive";
985
986 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
987 assigned-clock-rates = <100000000>, <100000000>;
988
989 phys = <&sata_phy>;
990 phy-names = "sata-phy";
991 status = "disabled";
992 };
993
994 qcom,ssbi@500000 {
995 compatible = "qcom,ssbi";
996 reg = <0x00500000 0x1000>;
997 qcom,controller-type = "pmic-arbiter";
998 };
999
1000 gcc: clock-controller@900000 {
1001 compatible = "qcom,gcc-ipq8064";
1002 reg = <0x00900000 0x4000>;
1003 #clock-cells = <1>;
1004 #reset-cells = <1>;
1005 #power-domain-cells = <1>;
1006 };
1007
1008 tsens: thermal-sensor@900000 {
1009 compatible = "qcom,ipq8064-tsens";
1010 reg = <0x900000 0x3680>;
1011 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1012 nvmem-cell-names = "calib", "calib_backup";
1013 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1014 #thermal-sensor-cells = <1>;
1015 };
1016
1017 tcsr: syscon@1a400000 {
1018 compatible = "qcom,tcsr-ipq8064", "syscon";
1019 reg = <0x1a400000 0x100>;
1020 };
1021
1022 lcc: clock-controller@28000000 {
1023 compatible = "qcom,lcc-ipq8064";
1024 reg = <0x28000000 0x1000>;
1025 #clock-cells = <1>;
1026 #reset-cells = <1>;
1027 };
1028
1029 sfpb_mutex_block: syscon@1200600 {
1030 compatible = "syscon";
1031 reg = <0x01200600 0x100>;
1032 };
1033
1034 hs_phy_0: hs_phy_0 {
1035 compatible = "qcom,dwc3-hs-usb-phy";
1036 regmap = <&usb3_0>;
1037 clocks = <&gcc USB30_0_UTMI_CLK>;
1038 clock-names = "ref";
1039 #phy-cells = <0>;
1040 };
1041
1042 ss_phy_0: ss_phy_0 {
1043 compatible = "qcom,dwc3-ss-usb-phy";
1044 regmap = <&usb3_0>;
1045 clocks = <&gcc USB30_0_MASTER_CLK>;
1046 clock-names = "ref";
1047 #phy-cells = <0>;
1048 };
1049
1050 usb3_0: usb3@110f8800 {
1051 compatible = "qcom,dwc3", "syscon";
1052 #address-cells = <1>;
1053 #size-cells = <1>;
1054 reg = <0x110f8800 0x8000>;
1055 clocks = <&gcc USB30_0_MASTER_CLK>;
1056 clock-names = "core";
1057
1058 ranges;
1059
1060 resets = <&gcc USB30_0_MASTER_RESET>;
1061 reset-names = "master";
1062
1063 status = "disabled";
1064
1065 dwc3_0: dwc3@11000000 {
1066 compatible = "snps,dwc3";
1067 reg = <0x11000000 0xcd00>;
1068 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1069 phys = <&hs_phy_0>, <&ss_phy_0>;
1070 phy-names = "usb2-phy", "usb3-phy";
1071 dr_mode = "host";
1072 snps,dis_u3_susphy_quirk;
1073 };
1074 };
1075
1076 hs_phy_1: hs_phy_1 {
1077 compatible = "qcom,dwc3-hs-usb-phy";
1078 regmap = <&usb3_1>;
1079 clocks = <&gcc USB30_1_UTMI_CLK>;
1080 clock-names = "ref";
1081 #phy-cells = <0>;
1082 };
1083
1084 ss_phy_1: ss_phy_1 {
1085 compatible = "qcom,dwc3-ss-usb-phy";
1086 regmap = <&usb3_1>;
1087 clocks = <&gcc USB30_1_MASTER_CLK>;
1088 clock-names = "ref";
1089 #phy-cells = <0>;
1090 };
1091
1092 usb3_1: usb3@100f8800 {
1093 compatible = "qcom,dwc3", "syscon";
1094 #address-cells = <1>;
1095 #size-cells = <1>;
1096 reg = <0x100f8800 0x8000>;
1097 clocks = <&gcc USB30_1_MASTER_CLK>;
1098 clock-names = "core";
1099
1100 ranges;
1101
1102 resets = <&gcc USB30_1_MASTER_RESET>;
1103 reset-names = "master";
1104
1105 status = "disabled";
1106
1107 dwc3_1: dwc3@10000000 {
1108 compatible = "snps,dwc3";
1109 reg = <0x10000000 0xcd00>;
1110 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1111 phys = <&hs_phy_1>, <&ss_phy_1>;
1112 phy-names = "usb2-phy", "usb3-phy";
1113 dr_mode = "host";
1114 snps,dis_u3_susphy_quirk;
1115 };
1116 };
1117
1118 pcie0: pci@1b500000 {
1119 compatible = "qcom,pcie-ipq8064";
1120 reg = <0x1b500000 0x1000
1121 0x1b502000 0x80
1122 0x1b600000 0x100
1123 0x0ff00000 0x100000>;
1124 reg-names = "dbi", "elbi", "parf", "config";
1125 device_type = "pci";
1126 linux,pci-domain = <0>;
1127 bus-range = <0x00 0xff>;
1128 num-lanes = <1>;
1129 #address-cells = <3>;
1130 #size-cells = <2>;
1131
1132 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
1133 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1134
1135 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1136 interrupt-names = "msi";
1137 #interrupt-cells = <1>;
1138 interrupt-map-mask = <0 0 0 0x7>;
1139 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1140 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1141 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1142 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1143
1144 clocks = <&gcc PCIE_A_CLK>,
1145 <&gcc PCIE_H_CLK>,
1146 <&gcc PCIE_PHY_CLK>,
1147 <&gcc PCIE_AUX_CLK>,
1148 <&gcc PCIE_ALT_REF_CLK>;
1149 clock-names = "core", "iface", "phy", "aux", "ref";
1150
1151 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1152 assigned-clock-rates = <100000000>;
1153
1154 resets = <&gcc PCIE_ACLK_RESET>,
1155 <&gcc PCIE_HCLK_RESET>,
1156 <&gcc PCIE_POR_RESET>,
1157 <&gcc PCIE_PCI_RESET>,
1158 <&gcc PCIE_PHY_RESET>,
1159 <&gcc PCIE_EXT_RESET>;
1160 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1161
1162 pinctrl-0 = <&pcie0_pins>;
1163 pinctrl-names = "default";
1164
1165 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1166
1167 phy-tx0-term-offset = <7>;
1168
1169 status = "disabled";
1170 };
1171
1172 pcie1: pci@1b700000 {
1173 compatible = "qcom,pcie-ipq8064";
1174 reg = <0x1b700000 0x1000
1175 0x1b702000 0x80
1176 0x1b800000 0x100
1177 0x31f00000 0x100000>;
1178 reg-names = "dbi", "elbi", "parf", "config";
1179 device_type = "pci";
1180 linux,pci-domain = <1>;
1181 bus-range = <0x00 0xff>;
1182 num-lanes = <1>;
1183 #address-cells = <3>;
1184 #size-cells = <2>;
1185
1186 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
1187 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1188
1189 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1190 interrupt-names = "msi";
1191 #interrupt-cells = <1>;
1192 interrupt-map-mask = <0 0 0 0x7>;
1193 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1194 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1195 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1196 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1197
1198 clocks = <&gcc PCIE_1_A_CLK>,
1199 <&gcc PCIE_1_H_CLK>,
1200 <&gcc PCIE_1_PHY_CLK>,
1201 <&gcc PCIE_1_AUX_CLK>,
1202 <&gcc PCIE_1_ALT_REF_CLK>;
1203 clock-names = "core", "iface", "phy", "aux", "ref";
1204
1205 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1206 assigned-clock-rates = <100000000>;
1207
1208 resets = <&gcc PCIE_1_ACLK_RESET>,
1209 <&gcc PCIE_1_HCLK_RESET>,
1210 <&gcc PCIE_1_POR_RESET>,
1211 <&gcc PCIE_1_PCI_RESET>,
1212 <&gcc PCIE_1_PHY_RESET>,
1213 <&gcc PCIE_1_EXT_RESET>;
1214 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1215
1216 pinctrl-0 = <&pcie1_pins>;
1217 pinctrl-names = "default";
1218
1219 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1220
1221 phy-tx0-term-offset = <7>;
1222
1223 status = "disabled";
1224 };
1225
1226 pcie2: pci@1b900000 {
1227 compatible = "qcom,pcie-ipq8064";
1228 reg = <0x1b900000 0x1000
1229 0x1b902000 0x80
1230 0x1ba00000 0x100
1231 0x35f00000 0x100000>;
1232 reg-names = "dbi", "elbi", "parf", "config";
1233 device_type = "pci";
1234 linux,pci-domain = <2>;
1235 bus-range = <0x00 0xff>;
1236 num-lanes = <1>;
1237 #address-cells = <3>;
1238 #size-cells = <2>;
1239
1240 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1241 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1242
1243 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1244 interrupt-names = "msi";
1245 #interrupt-cells = <1>;
1246 interrupt-map-mask = <0 0 0 0x7>;
1247 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1248 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1249 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1250 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1251
1252 clocks = <&gcc PCIE_2_A_CLK>,
1253 <&gcc PCIE_2_H_CLK>,
1254 <&gcc PCIE_2_PHY_CLK>,
1255 <&gcc PCIE_2_AUX_CLK>,
1256 <&gcc PCIE_2_ALT_REF_CLK>;
1257 clock-names = "core", "iface", "phy", "aux", "ref";
1258
1259 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1260 assigned-clock-rates = <100000000>;
1261
1262 resets = <&gcc PCIE_2_ACLK_RESET>,
1263 <&gcc PCIE_2_HCLK_RESET>,
1264 <&gcc PCIE_2_POR_RESET>,
1265 <&gcc PCIE_2_PCI_RESET>,
1266 <&gcc PCIE_2_PHY_RESET>,
1267 <&gcc PCIE_2_EXT_RESET>;
1268 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1269
1270 pinctrl-0 = <&pcie2_pins>;
1271 pinctrl-names = "default";
1272
1273 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1274
1275 phy-tx0-term-offset = <7>;
1276
1277 status = "disabled";
1278 };
1279
1280 adm_dma: dma@18300000 {
1281 compatible = "qcom,adm";
1282 reg = <0x18300000 0x100000>;
1283 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1284 #dma-cells = <1>;
1285
1286 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1287 clock-names = "core", "iface";
1288
1289 resets = <&gcc ADM0_RESET>,
1290 <&gcc ADM0_PBUS_RESET>,
1291 <&gcc ADM0_C0_RESET>,
1292 <&gcc ADM0_C1_RESET>,
1293 <&gcc ADM0_C2_RESET>;
1294 reset-names = "clk", "pbus", "c0", "c1", "c2";
1295 qcom,ee = <0>;
1296
1297 status = "disabled";
1298 };
1299
1300 nand_controller: nand-controller@1ac00000 {
1301 compatible = "qcom,ipq806x-nand";
1302 reg = <0x1ac00000 0x800>;
1303
1304 clocks = <&gcc EBI2_CLK>,
1305 <&gcc EBI2_AON_CLK>;
1306 clock-names = "core", "aon";
1307
1308 dmas = <&adm_dma 3>;
1309 dma-names = "rxtx";
1310 qcom,cmd-crci = <15>;
1311 qcom,data-crci = <3>;
1312
1313 status = "disabled";
1314
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1317 };
1318
1319 nss_common: syscon@03000000 {
1320 compatible = "syscon";
1321 reg = <0x03000000 0x0000FFFF>;
1322 };
1323
1324 qsgmii_csr: syscon@1bb00000 {
1325 compatible = "syscon";
1326 reg = <0x1bb00000 0x000001FF>;
1327 };
1328
1329 stmmac_axi_setup: stmmac-axi-config {
1330 snps,wr_osr_lmt = <7>;
1331 snps,rd_osr_lmt = <7>;
1332 snps,blen = <16 0 0 0 0 0 0>;
1333 };
1334
1335 gmac0: ethernet@37000000 {
1336 device_type = "network";
1337 compatible = "qcom,ipq806x-gmac";
1338 reg = <0x37000000 0x200000>;
1339 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1340 interrupt-names = "macirq";
1341
1342 snps,axi-config = <&stmmac_axi_setup>;
1343 snps,pbl = <32>;
1344 snps,aal = <1>;
1345
1346 qcom,nss-common = <&nss_common>;
1347 qcom,qsgmii-csr = <&qsgmii_csr>;
1348
1349 clocks = <&gcc GMAC_CORE1_CLK>;
1350 clock-names = "stmmaceth";
1351
1352 resets = <&gcc GMAC_CORE1_RESET>;
1353 reset-names = "stmmaceth";
1354
1355 status = "disabled";
1356 };
1357
1358 gmac1: ethernet@37200000 {
1359 device_type = "network";
1360 compatible = "qcom,ipq806x-gmac";
1361 reg = <0x37200000 0x200000>;
1362 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1363 interrupt-names = "macirq";
1364
1365 snps,axi-config = <&stmmac_axi_setup>;
1366 snps,pbl = <32>;
1367 snps,aal = <1>;
1368
1369 qcom,nss-common = <&nss_common>;
1370 qcom,qsgmii-csr = <&qsgmii_csr>;
1371
1372 clocks = <&gcc GMAC_CORE2_CLK>;
1373 clock-names = "stmmaceth";
1374
1375 resets = <&gcc GMAC_CORE2_RESET>;
1376 reset-names = "stmmaceth";
1377
1378 status = "disabled";
1379 };
1380
1381 gmac2: ethernet@37400000 {
1382 device_type = "network";
1383 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1384 reg = <0x37400000 0x200000>;
1385 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1386 interrupt-names = "macirq";
1387
1388 snps,axi-config = <&stmmac_axi_setup>;
1389 snps,pbl = <32>;
1390 snps,aal = <1>;
1391
1392 qcom,nss-common = <&nss_common>;
1393 qcom,qsgmii-csr = <&qsgmii_csr>;
1394
1395 clocks = <&gcc GMAC_CORE3_CLK>;
1396 clock-names = "stmmaceth";
1397
1398 resets = <&gcc GMAC_CORE3_RESET>;
1399 reset-names = "stmmaceth";
1400
1401 status = "disabled";
1402 };
1403
1404 gmac3: ethernet@37600000 {
1405 device_type = "network";
1406 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1407 reg = <0x37600000 0x200000>;
1408 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1409 interrupt-names = "macirq";
1410
1411 snps,axi-config = <&stmmac_axi_setup>;
1412 snps,pbl = <32>;
1413 snps,aal = <1>;
1414
1415 qcom,nss-common = <&nss_common>;
1416 qcom,qsgmii-csr = <&qsgmii_csr>;
1417
1418 clocks = <&gcc GMAC_CORE4_CLK>;
1419 clock-names = "stmmaceth";
1420
1421 resets = <&gcc GMAC_CORE4_RESET>;
1422 reset-names = "stmmaceth";
1423
1424 status = "disabled";
1425 };
1426
1427 /* Temporary fixed regulator */
1428 vsdcc_fixed: vsdcc-regulator {
1429 compatible = "regulator-fixed";
1430 regulator-name = "SDCC Power";
1431 regulator-min-microvolt = <3300000>;
1432 regulator-max-microvolt = <3300000>;
1433 regulator-always-on;
1434 };
1435
1436 sdcc1bam:dma@12402000 {
1437 compatible = "qcom,bam-v1.3.0";
1438 reg = <0x12402000 0x8000>;
1439 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1440 clocks = <&gcc SDC1_H_CLK>;
1441 clock-names = "bam_clk";
1442 #dma-cells = <1>;
1443 qcom,ee = <0>;
1444 };
1445
1446 sdcc3bam:dma@12182000 {
1447 compatible = "qcom,bam-v1.3.0";
1448 reg = <0x12182000 0x8000>;
1449 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1450 clocks = <&gcc SDC3_H_CLK>;
1451 clock-names = "bam_clk";
1452 #dma-cells = <1>;
1453 qcom,ee = <0>;
1454 };
1455
1456 amba {
1457 compatible = "arm,amba-bus";
1458 #address-cells = <1>;
1459 #size-cells = <1>;
1460 ranges;
1461 sdcc1: sdcc@12400000 {
1462 status = "disabled";
1463 compatible = "arm,pl18x", "arm,primecell";
1464 arm,primecell-periphid = <0x00051180>;
1465 reg = <0x12400000 0x2000>;
1466 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1467 interrupt-names = "cmd_irq";
1468 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1469 clock-names = "mclk", "apb_pclk";
1470 bus-width = <8>;
1471 max-frequency = <96000000>;
1472 non-removable;
1473 cap-sd-highspeed;
1474 cap-mmc-highspeed;
1475 vmmc-supply = <&vsdcc_fixed>;
1476 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1477 dma-names = "tx", "rx";
1478 };
1479
1480 sdcc3: sdcc@12180000 {
1481 compatible = "arm,pl18x", "arm,primecell";
1482 arm,primecell-periphid = <0x00051180>;
1483 status = "disabled";
1484 reg = <0x12180000 0x2000>;
1485 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1486 interrupt-names = "cmd_irq";
1487 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1488 clock-names = "mclk", "apb_pclk";
1489 bus-width = <8>;
1490 cap-sd-highspeed;
1491 cap-mmc-highspeed;
1492 max-frequency = <192000000>;
1493 #mmc-ddr-1_8v;
1494 sd-uhs-sdr104;
1495 sd-uhs-ddr50;
1496 vqmmc-supply = <&vsdcc_fixed>;
1497 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1498 dma-names = "tx", "rx";
1499 };
1500 };
1501 };
1502
1503 sfpb_mutex: sfpb-mutex {
1504 compatible = "qcom,sfpb-mutex";
1505 syscon = <&sfpb_mutex_block 4 4>;
1506
1507 #hwlock-cells = <1>;
1508 };
1509
1510 smem {
1511 compatible = "qcom,smem";
1512 memory-region = <&smem>;
1513 hwlocks = <&sfpb_mutex 3>;
1514 };
1515 };
Staging tree of Baptiste Jonglez