1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "qcom-ipq8064-v2.0.dtsi"
5 #include <dt-bindings/input/input.h>
9 bootargs = "console=ttyMSM0,115200n8";
10 /* append to bootargs adding the root deviceblock nbr from bootloader */
11 append-rootblock = "ubi.mtd=";
16 /* eax500 routers reuse the pcie2 reset pin for switch reset pin */
17 switch_reset: switch_reset_pins {
21 drive-strength = <12>;
48 pinctrl-0 = <&nand_pins>;
49 pinctrl-names = "default";
53 compatible = "qcom,nandcs";
55 nand-ecc-strength = <4>;
57 nand-ecc-step-size = <512>;
60 qcom,boot_pages_size = <0x0c80000>;
62 partitions: partitions {
63 compatible = "fixed-partitions";
69 reg = <0x0000000 0x0040000>;
75 reg = <0x0040000 0x0140000>;
81 reg = <0x0180000 0x0140000>;
87 reg = <0x02c0000 0x0280000>;
93 reg = <0x0540000 0x0120000>;
99 reg = <0x0660000 0x0120000>;
105 reg = <0x0780000 0x0280000>;
111 reg = <0x0a00000 0x0280000>;
115 art: partition@c80000 {
117 reg = <0x0c80000 0x0140000>;
123 reg = <0x0dc0000 0x0100000>;
129 reg = <0x0ec0000 0x0040000>;
134 reg = <0x0f00000 0x0040000>;
139 reg = <0x0f40000 0x0040000>;
144 reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */
149 reg = <0x1380000 0x2400000>;
154 reg = <0x3780000 0x2800000>;
159 reg = <0x3b80000 0x2400000>;
168 pinctrl-0 = <&mdio0_pins>;
169 pinctrl-names = "default";
171 /* Switch from documentation require at least 10ms for reset */
172 reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
173 reset-post-delay-us = <12000>;
175 phy0: ethernet-phy@0 {
177 qca,ar8327-initvals = <
178 0x00004 0x7600000 /* PAD0_MODE */
179 0x00008 0x1000000 /* PAD5_MODE */
180 0x0000c 0x80 /* PAD6_MODE */
181 0x00010 0x2613a0 /* PWS_REG */
182 0x000e4 0x6a545 /* MAC_POWER_SEL */
183 0x000e0 0xc74164de /* SGMII_CTRL */
184 0x0007c 0x4e /* PORT0_STATUS */
185 0x00094 0x4e /* PORT6_STATUS */
196 pinctrl-0 = <&rgmii2_pins>;
197 pinctrl-names = "default";