ipq40xx: switch default to 6.6
[openwrt/staging/stintel.git] / target / linux / ipq40xx / files-6.1 / arch / arm / boot / dts / qcom-ipq4018-wrtq-329acn.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/soc/qcom,tcsr.h>
7
8 / {
9 model = "Luma Home WRTQ-329ACN";
10 compatible = "luma,wrtq-329acn";
11
12 i2c-gpio {
13 compatible = "i2c-gpio";
14 sda-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
15 scl-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 /* No driver exists */
20 led_ring@48 {
21 compatible = "ti,msp430";
22 reg = <0x48>;
23 };
24
25 eeprom@50 {
26 compatible = "atmel,24c16";
27 reg = <0x50>;
28 pagesize = <16>;
29 read-only;
30 };
31 };
32
33 keys {
34 compatible = "gpio-keys";
35
36 reset {
37 label = "reset";
38 gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
39 linux,code = <KEY_RESTART>;
40 };
41 };
42
43 soc {
44 rng@22000 {
45 status = "okay";
46 };
47
48 tcsr@1949000 {
49 compatible = "qcom,tcsr";
50 reg = <0x1949000 0x100>;
51 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
52 };
53
54 tcsr@194b000 {
55 compatible = "qcom,tcsr";
56 reg = <0x194b000 0x100>;
57 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
58 };
59
60 ess_tcsr@1953000 {
61 compatible = "qcom,tcsr";
62 reg = <0x1953000 0x1000>;
63 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
64 };
65
66 tcsr@1957000 {
67 compatible = "qcom,tcsr";
68 reg = <0x1957000 0x100>;
69 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
70 };
71
72 usb2@60f8800 {
73 status = "okay";
74 };
75
76 usb3@8af8800 {
77 status = "okay";
78 };
79
80 crypto@8e3a000 {
81 status = "okay";
82 };
83
84 watchdog@b017000 {
85 status = "okay";
86 };
87 };
88 };
89
90 &blsp_dma {
91 status = "okay";
92 };
93
94
95 &blsp1_spi1 {
96 status = "okay";
97
98 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
99 <&tlmm 59 GPIO_ACTIVE_HIGH>;
100 pinctrl-0 = <&spi0_pins>;
101 pinctrl-names = "default";
102
103 flash@0 {
104 compatible = "jedec,spi-nor";
105 reg = <0>;
106 spi-max-frequency = <24000000>;
107
108 partitions {
109 compatible = "fixed-partitions";
110 #address-cells = <1>;
111 #size-cells = <1>;
112
113 partition@0 {
114 label = "0:SBL1";
115 reg = <0x000000 0x040000>;
116 read-only;
117 };
118
119 partition@40000 {
120 label = "0:MIBIB";
121 reg = <0x040000 0x020000>;
122 read-only;
123 };
124
125 partition@60000 {
126 label = "0:QSEE";
127 reg = <0x060000 0x060000>;
128 read-only;
129 };
130
131 partition@c0000 {
132 label = "0:CDT";
133 reg = <0x0c0000 0x010000>;
134 read-only;
135 };
136
137 partition@d0000 {
138 label = "0:DDRPARAMS";
139 reg = <0x0d0000 0x010000>;
140 read-only;
141 };
142
143 partition@e0000 {
144 label = "0:APPSBLENV";
145 reg = <0x0e0000 0x010000>;
146 };
147
148 partition@f0000 {
149 label = "0:APPSBL";
150 reg = <0x0f0000 0x080000>;
151 read-only;
152 };
153
154 partition@170000 {
155 label = "0:ART";
156 reg = <0x170000 0x010000>;
157 read-only;
158
159 nvmem-layout {
160 compatible = "fixed-layout";
161 #address-cells = <1>;
162 #size-cells = <1>;
163
164 macaddr_art_0: macaddr@0{
165 reg = <0x0000 0x0006>;
166 };
167
168 macaddr_art_6: macaddr@6{
169 reg = <0x0006 0x0006>;
170 };
171
172 precal_art_1000: precal@1000 {
173 reg = <0x1000 0x2f20>;
174 };
175
176 precal_art_5000: precal@5000 {
177 reg = <0x5000 0x2f20>;
178 };
179 };
180 };
181 };
182 };
183
184 flash@1 {
185 status = "okay";
186
187 compatible = "spi-nand";
188 reg = <1>;
189 spi-max-frequency = <24000000>;
190
191 partitions {
192 compatible = "fixed-partitions";
193 #address-cells = <1>;
194 #size-cells = <1>;
195
196 partition@0 {
197 label = "ubi";
198 reg = <0x0000000 0x8000000>;
199 };
200 };
201 };
202 };
203
204 &blsp1_uart1 {
205 status = "okay";
206
207 pinctrl-0 = <&serial0_pins>;
208 pinctrl-names = "default";
209 };
210
211 &cryptobam {
212 status = "okay";
213 };
214
215 &gmac {
216 status = "okay";
217 };
218
219 &ethphy0 {
220 status = "disabled";
221 };
222
223 &ethphy1 {
224 status = "disabled";
225 };
226
227 &ethphy3 {
228 status = "disabled";
229 };
230
231 &mdio {
232 status = "okay";
233 };
234
235 &switch {
236 status = "okay";
237 };
238
239 &swport3 {
240 status = "okay";
241
242 label = "lan";
243 nvmem-cell-names = "mac-address";
244 nvmem-cells = <&macaddr_art_6>;
245 };
246
247 &swport5 {
248 status = "okay";
249
250 nvmem-cell-names = "mac-address";
251 nvmem-cells = <&macaddr_art_0>;
252 };
253
254 &tlmm {
255 serial0_pins: serial0_pinmux {
256 mux {
257 function = "blsp_uart0";
258 pins = "gpio60", "gpio61";
259 bias-disable;
260 };
261 };
262
263 spi0_pins: spi0_pinmux {
264 mux {
265 function = "blsp_spi0";
266 pins = "gpio55", "gpio56", "gpio57";
267 bias-disable;
268 drive-strength = <12>;
269 };
270
271 mux_cs {
272 function = "gpio";
273 pins = "gpio54", "gpio59";
274 bias-disable;
275 drive-strength = <2>;
276 output-high;
277 };
278 };
279 };
280
281 &usb2_hs_phy {
282 status = "okay";
283 };
284
285 &usb3_hs_phy {
286 status = "okay";
287 };
288
289 &usb3_ss_phy {
290 status = "okay";
291 };
292
293 &wifi0 {
294 status = "okay";
295 nvmem-cell-names = "pre-calibration";
296 nvmem-cells = <&precal_art_1000>;
297 qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
298 };
299
300 &wifi1 {
301 status = "okay";
302 nvmem-cell-names = "pre-calibration";
303 nvmem-cells = <&precal_art_5000>;
304 qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
305 };