target/linux/bmips/dts/bcm63268.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 /dts-v1/;
   4
   5 #include <dt-bindings/clock/bcm63268-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/reset/bcm63268-reset.h>
  11 #include <dt-bindings/soc/bcm63268-pm.h>
  12
  13 / {
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16         compatible = "brcm,bcm63268";
  17
  18         aliases {
  19                 nflash = &nflash;
  20                 pinctrl = &pinctrl;
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 spi0 = &lsspi;
  24                 spi1 = &hsspi;
  25         };
  26
  27         chosen {
  28                 bootargs = "earlycon";
  29                 stdout-path = "serial0:115200n8";
  30         };
  31
  32         clocks {
  33                 periph_osc: periph-osc {
  34                         compatible = "fixed-clock";
  35
  36                         #clock-cells = <0>;
  37
  38                         clock-frequency = <50000000>;
  39                         clock-output-names = "periph";
  40                 };
  41
  42                 hsspi_osc: hsspi-osc {
  43                         compatible = "fixed-clock";
  44
  45                         #clock-cells = <0>;
  46
  47                         clock-frequency = <400000000>;
  48                         clock-output-names = "hsspi_osc";
  49                 };
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 mips-hpt-frequency = <200000000>;
  56
  57                 cpu@0 {
  58                         compatible = "brcm,bmips4350", "mips,mips4Kc";
  59                         device_type = "cpu";
  60                         reg = <0>;
  61                 };
  62
  63                 cpu@1 {
  64                         compatible = "brcm,bmips4350", "mips,mips4Kc";
  65                         device_type = "cpu";
  66                         reg = <1>;
  67                 };
  68         };
  69
  70         cpu_intc: interrupt-controller {
  71                 #address-cells = <0>;
  72                 compatible = "mti,cpu-interrupt-controller";
  73
  74                 interrupt-controller;
  75                 #interrupt-cells = <1>;
  76         };
  77
  78         memory@0 {
  79                 device_type = "memory";
  80                 reg = <0 0>;
  81         };
  82
  83         ubus {
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86
  87                 compatible = "simple-bus";
  88                 ranges;
  89
  90                 periph_clk: clock-controller@10000004 {
  91                         compatible = "brcm,bcm63268-clocks";
  92                         reg = <0x10000004 0x4>;
  93                         #clock-cells = <1>;
  94                 };
  95
  96                 pll_cntl: syscon@10000008 {
  97                         compatible = "syscon", "simple-mfd";
  98                         reg = <0x10000008 0x4>;
  99                         native-endian;
 100
 101                         syscon-reboot {
 102                                 compatible = "syscon-reboot";
 103                                 offset = <0x0>;
 104                                 mask = <0x1>;
 105                         };
 106                 };
 107
 108                 periph_rst: reset-controller@10000010 {
 109                         compatible = "brcm,bcm6345-reset";
 110                         reg = <0x10000010 0x4>;
 111                         #reset-cells = <1>;
 112                 };
 113
 114                 ext_intc: interrupt-controller@10000018 {
 115                         #address-cells = <1>;
 116                         compatible = "brcm,bcm6345-ext-intc";
 117                         reg = <0x10000018 0x4>;
 118
 119                         interrupt-controller;
 120                         #interrupt-cells = <2>;
 121
 122                         interrupt-parent = <&periph_intc>;
 123                         interrupts = <BCM63268_IRQ_EXT0>,
 124                                      <BCM63268_IRQ_EXT1>,
 125                                      <BCM63268_IRQ_EXT2>,
 126                                      <BCM63268_IRQ_EXT3>;
 127                 };
 128
 129                 periph_intc: interrupt-controller@10000020 {
 130                         #address-cells = <1>;
 131                         compatible = "brcm,bcm6345-l1-intc";
 132                         reg = <0x10000020 0x20>,
 133                               <0x10000040 0x20>;
 134
 135                         interrupt-controller;
 136                         #interrupt-cells = <1>;
 137
 138                         interrupt-parent = <&cpu_intc>;
 139                         interrupts = <2>, <3>;
 140                 };
 141
 142                 wdt: watchdog@1000009c {
 143                         compatible = "brcm,bcm7038-wdt";
 144                         reg = <0x1000009c 0xc>;
 145
 146                         clocks = <&periph_osc>;
 147
 148                         timeout-sec = <30>;
 149                 };
 150
 151                 timer_clk: clock-controller@100000ac {
 152                         compatible = "brcm,bcm63268-timer-clocks";
 153                         reg = <0x100000ac 0x4>;
 154                         #clock-cells = <1>;
 155                         #reset-cells = <1>;
 156                 };
 157
 158                 gpio_cntl: syscon@100000c0 {
 159                         #address-cells = <1>;
 160                         #size-cells = <1>;
 161                         compatible = "brcm,bcm63268-gpio-sysctl",
 162                                      "syscon", "simple-mfd";
 163                         reg = <0x100000c0 0x80>;
 164                         ranges = <0 0x100000c0 0x80>;
 165                         native-endian;
 166
 167                         gpio: gpio@0 {
 168                                 compatible = "brcm,bcm63268-gpio";
 169                                 reg-names = "dirout", "dat";
 170                                 reg = <0x0 0x8>, <0x8 0x8>;
 171
 172                                 gpio-controller;
 173                                 gpio-ranges = <&pinctrl 0 0 52>;
 174                                 #gpio-cells = <2>;
 175                         };
 176
 177                         pinctrl: pinctrl@10 {
 178                                 compatible = "brcm,bcm63268-pinctrl";
 179                                 reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
 180
 181                                 pinctrl_serial_led: serial_led-pins {
 182                                         pinctrl_serial_led_clk: serial_led_clk-pins {
 183                                                 function = "serial_led_clk";
 184                                                 pins = "gpio0";
 185                                         };
 186
 187                                         pinctrl_serial_led_data: serial_led_data-pins {
 188                                                 function = "serial_led_data";
 189                                                 pins = "gpio1";
 190                                         };
 191                                 };
 192
 193                                 pinctrl_hsspi_cs4: hsspi_cs4-pins {
 194                                         function = "hsspi_cs4";
 195                                         pins = "gpio16";
 196                                 };
 197
 198                                 pinctrl_hsspi_cs5: hsspi_cs5-pins {
 199                                         function = "hsspi_cs5";
 200                                         pins = "gpio17";
 201                                 };
 202
 203                                 pinctrl_hsspi_cs6: hsspi_cs6-pins {
 204                                         function = "hsspi_cs6";
 205                                         pins = "gpio8";
 206                                 };
 207
 208                                 pinctrl_hsspi_cs7: hsspi_cs7-pins {
 209                                         function = "hsspi_cs7";
 210                                         pins = "gpio9";
 211                                 };
 212
 213                                 pinctrl_adsl_spi: adsl_spi {
 214                                         pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
 215                                                 function = "adsl_spi_miso";
 216                                                 pins = "gpio18";
 217                                         };
 218
 219                                         pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
 220                                                 function = "adsl_spi_mosi";
 221                                                 pins = "gpio19";
 222                                         };
 223                                 };
 224
 225                                 pinctrl_vreq_clk: vreq_clk-pins {
 226                                         function = "vreq_clk";
 227                                         pins = "gpio22";
 228                                 };
 229
 230                                 pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
 231                                         function = "pcie_clkreq_b";
 232                                         pins = "gpio23";
 233                                 };
 234
 235                                 pinctrl_robosw_led_clk: robosw_led_clk-pins {
 236                                         function = "robosw_led_clk";
 237                                         pins = "gpio30";
 238                                 };
 239
 240                                 pinctrl_robosw_led_data: robosw_led_data-pins {
 241                                         function = "robosw_led_data";
 242                                         pins = "gpio31";
 243                                 };
 244
 245                                 pinctrl_nand: nand-pins {
 246                                         function = "nand";
 247                                         group = "nand_grp";
 248                                 };
 249
 250                                 pinctrl_gpio35_alt: gpio35_alt-pins {
 251                                         function = "gpio35_alt";
 252                                         pin = "gpio35";
 253                                 };
 254
 255                                 pinctrl_dectpd: dectpd-pins {
 256                                         function = "dectpd";
 257                                         group = "dectpd_grp";
 258                                 };
 259
 260                                 pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
 261                                         function = "vdsl_phy_override_0";
 262                                         group = "vdsl_phy_override_0_grp";
 263                                 };
 264
 265                                 pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
 266                                         function = "vdsl_phy_override_1";
 267                                         group = "vdsl_phy_override_1_grp";
 268                                 };
 269
 270                                 pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
 271                                         function = "vdsl_phy_override_2";
 272                                         group = "vdsl_phy_override_2_grp";
 273                                 };
 274
 275                                 pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
 276                                         function = "vdsl_phy_override_3";
 277                                         group = "vdsl_phy_override_3_grp";
 278                                 };
 279
 280                                 pinctrl_dsl_gpio8: dsl_gpio8-pins {
 281                                         function = "dsl_gpio8";
 282                                         group = "dsl_gpio8";
 283                                 };
 284
 285                                 pinctrl_dsl_gpio9: dsl_gpio9-pins {
 286                                         function = "dsl_gpio9";
 287                                         group = "dsl_gpio9";
 288                                 };
 289                         };
 290                 };
 291
 292                 uart0: serial@10000180 {
 293                         compatible = "brcm,bcm6345-uart";
 294                         reg = <0x10000180 0x18>;
 295
 296                         interrupt-parent = <&periph_intc>;
 297                         interrupts = <BCM63268_IRQ_UART0>;
 298
 299                         clocks = <&periph_osc>;
 300                         clock-names = "periph";
 301
 302                         status = "disabled";
 303                 };
 304
 305                 uart1: serial@100001a0 {
 306                         compatible = "brcm,bcm6345-uart";
 307                         reg = <0x100001a0 0x18>;
 308
 309                         interrupt-parent = <&periph_intc>;
 310                         interrupts = <BCM63268_IRQ_UART1>;
 311
 312                         clocks = <&periph_osc>;
 313                         clock-names = "periph";
 314
 315                         status = "disabled";
 316                 };
 317
 318                 nflash: nand@10000200 {
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321                         compatible = "brcm,nand-bcm6368",
 322                                      "brcm,brcmnand-v4.0",
 323                                      "brcm,brcmnand";
 324                         reg = <0x10000200 0x180>,
 325                               <0x10000600 0x200>,
 326                               <0x100000b0 0x10>;
 327                         reg-names = "nand",
 328                                     "nand-cache",
 329                                     "nand-int-base";
 330
 331                         interrupt-parent = <&periph_intc>;
 332                         interrupts = <BCM63268_IRQ_NAND>;
 333
 334                         clocks = <&periph_clk BCM63268_CLK_NAND>;
 335                         clock-names = "nand";
 336
 337                         pinctrl-names = "default";
 338                         pinctrl-0 = <&pinctrl_nand>;
 339
 340                         status = "disabled";
 341                 };
 342
 343                 lsspi: spi@10000800 {
 344                         #address-cells = <1>;
 345                         #size-cells = <0>;
 346                         compatible = "brcm,bcm6358-spi";
 347                         reg = <0x10000800 0x70c>;
 348
 349                         interrupt-parent = <&periph_intc>;
 350                         interrupts = <BCM63268_IRQ_LSSPI>;
 351
 352                         clocks = <&periph_clk BCM63268_CLK_SPI>;
 353                         clock-names = "spi";
 354
 355                         resets = <&periph_rst BCM63268_RST_SPI>;
 356
 357                         status = "disabled";
 358                 };
 359
 360                 hsspi: spi@10001000 {
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         compatible = "brcm,bcm6328-hsspi";
 364                         reg = <0x10001000 0x600>;
 365
 366                         interrupt-parent = <&periph_intc>;
 367                         interrupts = <BCM63268_IRQ_HSSPI>;
 368
 369                         clocks = <&periph_clk BCM63268_CLK_HSSPI>,
 370                                  <&hsspi_osc>;
 371                         clock-names = "hsspi",
 372                                       "pll";
 373
 374                         resets = <&periph_rst BCM63268_RST_SPI>;
 375
 376                         status = "disabled";
 377                 };
 378
 379                 serdes_cntl: syscon@10001804 {
 380                         compatible = "syscon";
 381                         reg = <0x10001804 0x4>;
 382                         native-endian;
 383                 };
 384
 385                 periph_pwr: power-controller@1000184c {
 386                         compatible = "brcm,bcm63268-power-controller";
 387                         reg = <0x1000184c 0x4>;
 388                         #power-domain-cells = <1>;
 389                 };
 390
 391                 leds: led-controller@10001900 {
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                         compatible = "brcm,bcm6328-leds";
 395                         reg = <0x10001900 0x24>;
 396
 397                         status = "disabled";
 398                 };
 399
 400                 ehci: usb@10002500 {
 401                         compatible = "brcm,bcm63268-ehci", "generic-ehci";
 402                         reg = <0x10002500 0x100>;
 403                         big-endian;
 404                         spurious-oc;
 405
 406                         interrupt-parent = <&periph_intc>;
 407                         interrupts = <BCM63268_IRQ_EHCI>;
 408
 409                         phys = <&usbh 0>;
 410                         phy-names = "usb";
 411
 412                         status = "disabled";
 413                 };
 414
 415                 ohci: usb@10002600 {
 416                         compatible = "brcm,bcm63268-ohci", "generic-ohci";
 417                         reg = <0x10002600 0x100>;
 418                         big-endian;
 419                         no-big-frame-no;
 420
 421                         interrupt-parent = <&periph_intc>;
 422                         interrupts = <BCM63268_IRQ_OHCI>;
 423
 424                         phys = <&usbh 0>;
 425                         phy-names = "usb";
 426
 427                         status = "disabled";
 428                 };
 429
 430                 usbh: usb-phy@10002700 {
 431                         compatible = "brcm,bcm63268-usbh-phy";
 432                         reg = <0x10002700 0x38>;
 433
 434                         #phy-cells = <1>;
 435
 436                         clocks = <&periph_clk BCM63268_CLK_USBH>,
 437                                  <&timer_clk BCM63268_TCLK_USB_REF>;
 438                         clock-names = "usbh",
 439                                       "usb_ref";
 440
 441                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;
 442                         resets = <&periph_rst BCM63268_RST_USBH>;
 443
 444                         status = "disabled";
 445                 };
 446
 447                 random: rng@10002880 {
 448                         compatible = "brcm,bcm6368-rng";
 449                         reg = <0x10002880 0x14>;
 450
 451                         clocks = <&periph_clk BCM63268_CLK_IPSEC>;
 452                         clock-names = "ipsec";
 453
 454                         resets = <&periph_rst BCM63268_RST_IPSEC>;
 455
 456                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_IPSEC>;
 457                 };
 458
 459                 ethernet: ethernet@1000d800 {
 460                         compatible = "brcm,bcm63268-enetsw";
 461                         reg = <0x1000d800 0x80>,
 462                               <0x1000da00 0x80>,
 463                               <0x1000dc00 0x80>;
 464                         reg-names = "dma",
 465                                     "dma-channels",
 466                                     "dma-sram";
 467
 468                         interrupt-parent = <&periph_intc>;
 469                         interrupts = <BCM63268_IRQ_ENETSW_RX_DMA0>,
 470                                      <BCM63268_IRQ_ENETSW_TX_DMA0>;
 471                         interrupt-names = "rx",
 472                                           "tx";
 473
 474                         clocks = <&periph_clk BCM63268_CLK_GMAC>,
 475                                  <&periph_clk BCM63268_CLK_ROBOSW>,
 476                                  <&periph_clk BCM63268_CLK_ROBOSW250>,
 477                                  <&timer_clk BCM63268_TCLK_EPHY1>,
 478                                  <&timer_clk BCM63268_TCLK_EPHY2>,
 479                                  <&timer_clk BCM63268_TCLK_EPHY3>,
 480                                  <&timer_clk BCM63268_TCLK_GPHY1>;
 481
 482                         resets = <&periph_rst BCM63268_RST_ENETSW>,
 483                                  <&periph_rst BCM63268_RST_EPHY>,
 484                                  <&periph_rst BCM63268_RST_GPHY>;
 485
 486                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;
 487
 488                         dma-rx = <0>;
 489                         dma-tx = <1>;
 490
 491                         status = "disabled";
 492                 };
 493
 494                 pcie: pcie@106e0000 {
 495                         compatible = "brcm,bcm6328-pcie";
 496                         reg = <0x106e0000 0x10000>;
 497                         #address-cells = <3>;
 498                         #size-cells = <2>;
 499
 500                         device_type = "pci";
 501                         bus-range = <0x00 0x01>;
 502                         ranges = <0x2000000 0 0x11000000 0x11000000 0 0xf00000>;
 503                         linux,pci-probe-only = <1>;
 504
 505                         interrupt-parent = <&periph_intc>;
 506                         interrupts = <BCM63268_IRQ_PCIE_RC>;
 507
 508                         clocks = <&periph_clk BCM63268_CLK_PCIE>;
 509                         clock-names = "pcie";
 510
 511                         resets = <&periph_rst BCM63268_RST_PCIE>,
 512                                  <&periph_rst BCM63268_RST_PCIE_EXT>,
 513                                  <&periph_rst BCM63268_RST_PCIE_CORE>,
 514                                  <&periph_rst BCM63268_RST_PCIE_HARD>;
 515                         reset-names = "pcie",
 516                                       "pcie-ext",
 517                                       "pcie-core",
 518                                       "pcie-hard";
 519
 520                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_PCIE>;
 521
 522                         brcm,serdes = <&serdes_cntl>;
 523
 524                         status = "disabled";
 525                 };
 526
 527                 switch0: switch@10700000 {
 528                         #address-cells = <1>;
 529                         #size-cells = <0>;
 530                         compatible = "brcm,bcm63268-switch";
 531                         reg = <0x10700000 0x8000>;
 532                         big-endian;
 533
 534                         ports {
 535                                 #address-cells = <1>;
 536                                 #size-cells = <0>;
 537
 538                                 port@8 {
 539                                         reg = <8>;
 540
 541                                         phy-mode = "internal";
 542                                         ethernet = <&ethernet>;
 543
 544                                         fixed-link {
 545                                                 speed = <1000>;
 546                                                 full-duplex;
 547                                         };
 548                                 };
 549                         };
 550                 };
 551
 552                 mdio: mdio@107000b0 {
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         compatible = "brcm,bcm6368-mdio-mux";
 556                         reg = <0x107000b0 0x8>;
 557
 558                         mdio_int: mdio@0 {
 559                                 #address-cells = <1>;
 560                                 #size-cells = <0>;
 561                                 reg = <0>;
 562
 563                                 phy1: ethernet-phy@1 {
 564                                         compatible = "ethernet-phy-ieee802.3-c22";
 565                                         reg = <1>;
 566                                 };
 567
 568                                 phy2: ethernet-phy@2 {
 569                                         compatible = "ethernet-phy-ieee802.3-c22";
 570                                         reg = <2>;
 571                                 };
 572
 573                                 phy3: ethernet-phy@3 {
 574                                         compatible = "ethernet-phy-ieee802.3-c22";
 575                                         reg = <3>;
 576                                 };
 577
 578                                 phy4: ethernet-phy@4 {
 579                                         compatible = "ethernet-phy-ieee802.3-c22";
 580                                         reg = <4>;
 581                                 };
 582                         };
 583
 584                         mdio_ext: mdio@1 {
 585                                 #address-cells = <1>;
 586                                 #size-cells = <0>;
 587                                 reg = <1>;
 588                         };
 589                 };
 590         };
 591 };