target/linux/bcm27xx/patches-6.1/950-0964-drm-vc4-crtc-Add-support-for-BCM2712-PixelValves.patch

   1 From 000f1b7d4dc5b515c755ee25db301e26bded00e1 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Fri, 17 Feb 2023 15:33:23 +0100
   4 Subject: [PATCH] drm/vc4: crtc: Add support for BCM2712 PixelValves
   5
   6 The PixelValves found on the BCM2712 are similar to the ones found in
   7 the previous generation.
   8
   9 Compared to BCM2711, the pixelvalves only drive one HDMI controller each
  10 and HDMI1 PixelValve has a FIFO long enough to support 4k at 60Hz.
  11
  12 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  13 ---
  14  drivers/gpu/drm/vc4/vc4_crtc.c | 53 ++++++++++++++++++++++++++++++++--
  15  drivers/gpu/drm/vc4/vc4_drv.h  |  2 ++
  16  drivers/gpu/drm/vc4/vc4_regs.h |  5 ++++
  17  3 files changed, 58 insertions(+), 2 deletions(-)
  18
  19 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  20 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  21 @@ -239,6 +239,11 @@ static u32 vc4_get_fifo_full_level(struc
  22         const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
  23         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
  24         struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
  25 +
  26 +       /*
  27 +        * NOTE: Could we use register 0x68 (PV_HW_CFG1) to get the FIFO
  28 +        * size?
  29 +        */
  30         u32 fifo_len_bytes = pv_data->fifo_depth;
  31
  32         /*
  33 @@ -393,6 +398,12 @@ static void vc4_crtc_config_pv(struct dr
  34
  35         vc4_crtc_pixelvalve_reset(crtc);
  36
  37 +       /*
  38 +        * NOTE: The BCM2712 has a H_OTE (Horizontal Odd Timing Enable)
  39 +        * bit that, when set, will allow to specify the timings in
  40 +        * pixels instead of cycles, thus allowing to specify odd
  41 +        * timings.
  42 +        */
  43         CRTC_WRITE(PV_HORZA,
  44                    VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
  45                                  PV_HORZA_HBP) |
  46 @@ -462,11 +473,17 @@ static void vc4_crtc_config_pv(struct dr
  47         if (is_dsi)
  48                 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
  49
  50 -       if (vc4->gen == VC4_GEN_5)
  51 +       if (vc4->gen >= VC4_GEN_5)
  52                 CRTC_WRITE(PV_MUX_CFG,
  53                            VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
  54                                          PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
  55
  56 +       if (vc4->gen >= VC4_GEN_6)
  57 +               CRTC_WRITE(PV_PIPE_INIT_CTRL,
  58 +                          VC4_SET_FIELD(1, PV_PIPE_INIT_CTRL_PV_INIT_WIDTH) |
  59 +                          VC4_SET_FIELD(1, PV_PIPE_INIT_CTRL_PV_INIT_IDLE) |
  60 +                          PV_PIPE_INIT_CTRL_PV_INIT_EN);
  61 +
  62         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
  63                    vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
  64                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
  65 @@ -565,7 +582,11 @@ int vc4_crtc_disable_at_boot(struct drm_
  66         if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
  67                                       "brcm,bcm2711-pixelvalve2") ||
  68               of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
  69 -                                     "brcm,bcm2711-pixelvalve4")))
  70 +                                     "brcm,bcm2711-pixelvalve4") ||
  71 +             of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
  72 +                                     "brcm,bcm2712-pixelvalve0") ||
  73 +             of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
  74 +                                     "brcm,bcm2712-pixelvalve1")))
  75                 return 0;
  76
  77         if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
  78 @@ -1304,6 +1325,32 @@ const struct vc4_pv_data bcm2711_pv4_dat
  79         },
  80  };
  81
  82 +const struct vc4_pv_data bcm2712_pv0_data = {
  83 +       .base = {
  84 +               .debugfs_name = "crtc0_regs",
  85 +               .hvs_available_channels = BIT(0),
  86 +               .hvs_output = 0,
  87 +       },
  88 +       .fifo_depth = 64,
  89 +       .pixels_per_clock = 2,
  90 +       .encoder_types = {
  91 +               [0] = VC4_ENCODER_TYPE_HDMI0,
  92 +       },
  93 +};
  94 +
  95 +const struct vc4_pv_data bcm2712_pv1_data = {
  96 +       .base = {
  97 +               .debugfs_name = "crtc1_regs",
  98 +               .hvs_available_channels = BIT(1),
  99 +               .hvs_output = 1,
 100 +       },
 101 +       .fifo_depth = 64,
 102 +       .pixels_per_clock = 2,
 103 +       .encoder_types = {
 104 +               [0] = VC4_ENCODER_TYPE_HDMI1,
 105 +       },
 106 +};
 107 +
 108  static const struct of_device_id vc4_crtc_dt_match[] = {
 109         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
 110         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
 111 @@ -1313,6 +1360,8 @@ static const struct of_device_id vc4_crt
 112         { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
 113         { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
 114         { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
 115 +       { .compatible = "brcm,bcm2712-pixelvalve0", .data = &bcm2712_pv0_data },
 116 +       { .compatible = "brcm,bcm2712-pixelvalve1", .data = &bcm2712_pv1_data },
 117         {}
 118  };
 119
 120 --- a/drivers/gpu/drm/vc4/vc4_drv.h
 121 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
 122 @@ -583,6 +583,8 @@ extern const struct vc4_pv_data bcm2711_
 123  extern const struct vc4_pv_data bcm2711_pv2_data;
 124  extern const struct vc4_pv_data bcm2711_pv3_data;
 125  extern const struct vc4_pv_data bcm2711_pv4_data;
 126 +extern const struct vc4_pv_data bcm2712_pv0_data;
 127 +extern const struct vc4_pv_data bcm2712_pv1_data;
 128
 129  struct vc5_gamma_entry {
 130         u32 x_c_terms;
 131 --- a/drivers/gpu/drm/vc4/vc4_regs.h
 132 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
 133 @@ -215,6 +215,11 @@
 134  # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT   2
 135  # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP 8
 136
 137 +#define PV_PIPE_INIT_CTRL                      0x94
 138 +# define PV_PIPE_INIT_CTRL_PV_INIT_WIDTH_MASK  VC4_MASK(11, 8)
 139 +# define PV_PIPE_INIT_CTRL_PV_INIT_IDLE_MASK   VC4_MASK(7, 4)
 140 +# define PV_PIPE_INIT_CTRL_PV_INIT_EN          BIT(0)
 141 +
 142  #define SCALER_CHANNELS_COUNT                  3
 143
 144  #define SCALER_DISPCTRL                         0x00000000