target/linux/bcm27xx/patches-6.1/950-0946-drm-vc4-plane-Change-ptr0_offset-to-an-array.patch

   1 From 531f66804eb95323f807d240273087fbe162aeee Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Fri, 24 Mar 2023 09:56:31 +0100
   4 Subject: [PATCH] drm/vc4: plane: Change ptr0_offset to an array
   5
   6 The BCM2712 will have a fairly different dlist, that will feature one
   7 Pointer 0 word for each plane.
   8
   9 Let's prepare by changing the ptr0_offset variable that holds the offset
  10 in a dlist of the pointer 0 word to an array.
  11
  12 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  13 ---
  14  drivers/gpu/drm/vc4/vc4_drv.h   |  3 ++-
  15  drivers/gpu/drm/vc4/vc4_plane.c | 18 +++++++++---------
  16  2 files changed, 11 insertions(+), 10 deletions(-)
  17
  18 --- a/drivers/gpu/drm/vc4/vc4_drv.h
  19 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
  20 @@ -14,6 +14,7 @@
  21  #include <drm/drm_debugfs.h>
  22  #include <drm/drm_device.h>
  23  #include <drm/drm_encoder.h>
  24 +#include <drm/drm_fourcc.h>
  25  #include <drm/drm_gem_dma_helper.h>
  26  #include <drm/drm_managed.h>
  27  #include <drm/drm_mm.h>
  28 @@ -430,7 +431,7 @@ struct vc4_plane_state {
  29          */
  30         u32 pos0_offset;
  31         u32 pos2_offset;
  32 -       u32 ptr0_offset;
  33 +       u32 ptr0_offset[DRM_FORMAT_MAX_PLANES];
  34         u32 lbm_offset;
  35
  36         /* Offset where the plane's dlist was last stored in the
  37 --- a/drivers/gpu/drm/vc4/vc4_plane.c
  38 +++ b/drivers/gpu/drm/vc4/vc4_plane.c
  39 @@ -1242,7 +1242,7 @@ static int vc4_plane_mode_set(struct drm
  40          *
  41          * The pointers may be any byte address.
  42          */
  43 -       vc4_state->ptr0_offset = vc4_state->dlist_count;
  44 +       vc4_state->ptr0_offset[0] = vc4_state->dlist_count;
  45         for (i = 0; i < num_planes; i++)
  46                 vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
  47
  48 @@ -1447,13 +1447,13 @@ void vc4_plane_async_set_fb(struct drm_p
  49          * scanout will start from this address as soon as the FIFO
  50          * needs to refill with pixels.
  51          */
  52 -       writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
  53 +       writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
  54
  55         /* Also update the CPU-side dlist copy, so that any later
  56          * atomic updates that don't do a new modeset on our plane
  57          * also use our updated address.
  58          */
  59 -       vc4_state->dlist[vc4_state->ptr0_offset] = addr;
  60 +       vc4_state->dlist[vc4_state->ptr0_offset[0]] = addr;
  61
  62         drm_dev_exit(idx);
  63  }
  64 @@ -1517,8 +1517,8 @@ static void vc4_plane_atomic_async_updat
  65                 new_vc4_state->dlist[vc4_state->pos0_offset];
  66         vc4_state->dlist[vc4_state->pos2_offset] =
  67                 new_vc4_state->dlist[vc4_state->pos2_offset];
  68 -       vc4_state->dlist[vc4_state->ptr0_offset] =
  69 -               new_vc4_state->dlist[vc4_state->ptr0_offset];
  70 +       vc4_state->dlist[vc4_state->ptr0_offset[0]] =
  71 +               new_vc4_state->dlist[vc4_state->ptr0_offset[0]];
  72
  73         /* Note that we can't just call vc4_plane_write_dlist()
  74          * because that would smash the context data that the HVS is
  75 @@ -1528,8 +1528,8 @@ static void vc4_plane_atomic_async_updat
  76                &vc4_state->hw_dlist[vc4_state->pos0_offset]);
  77         writel(vc4_state->dlist[vc4_state->pos2_offset],
  78                &vc4_state->hw_dlist[vc4_state->pos2_offset]);
  79 -       writel(vc4_state->dlist[vc4_state->ptr0_offset],
  80 -              &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
  81 +       writel(vc4_state->dlist[vc4_state->ptr0_offset[0]],
  82 +              &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
  83
  84         drm_dev_exit(idx);
  85  }
  86 @@ -1556,7 +1556,7 @@ static int vc4_plane_atomic_async_check(
  87         if (old_vc4_state->dlist_count != new_vc4_state->dlist_count ||
  88             old_vc4_state->pos0_offset != new_vc4_state->pos0_offset ||
  89             old_vc4_state->pos2_offset != new_vc4_state->pos2_offset ||
  90 -           old_vc4_state->ptr0_offset != new_vc4_state->ptr0_offset ||
  91 +           old_vc4_state->ptr0_offset[0] != new_vc4_state->ptr0_offset[0] ||
  92             vc4_lbm_size(plane->state) != vc4_lbm_size(new_plane_state))
  93                 return -EINVAL;
  94
  95 @@ -1566,7 +1566,7 @@ static int vc4_plane_atomic_async_check(
  96         for (i = 0; i < new_vc4_state->dlist_count; i++) {
  97                 if (i == new_vc4_state->pos0_offset ||
  98                     i == new_vc4_state->pos2_offset ||
  99 -                   i == new_vc4_state->ptr0_offset ||
 100 +                   i == new_vc4_state->ptr0_offset[0] ||
 101                     (new_vc4_state->lbm_offset &&
 102                      i == new_vc4_state->lbm_offset))
 103                         continue;