target/linux/bcm27xx/patches-6.1/950-0944-drm-vc4-hvs-Create-cob_init-function.patch

   1 From 99a13ce3a12303dfb54815637972627a7d207086 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Fri, 17 Feb 2023 15:14:55 +0100
   4 Subject: [PATCH] drm/vc4: hvs: Create cob_init function
   5
   6 Just like the HVS itself, the COB parameters will be fairly different in
   7 the BCM2712.
   8
   9 Let's move the COB parameters computation and its initialisation to a
  10 separate function that will be easier to extend in the future.
  11
  12 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  13 ---
  14  drivers/gpu/drm/vc4/vc4_hvs.c | 128 ++++++++++++++++++++--------------
  15  1 file changed, 74 insertions(+), 54 deletions(-)
  16
  17 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
  18 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
  19 @@ -1379,6 +1379,77 @@ static int vc4_hvs_hw_init(struct vc4_hv
  20         return 0;
  21  }
  22
  23 +static int vc4_hvs_cob_init(struct vc4_hvs *hvs)
  24 +{
  25 +       struct vc4_dev *vc4 = hvs->vc4;
  26 +       u32 reg, top;
  27 +
  28 +       /*
  29 +        * Recompute Composite Output Buffer (COB) allocations for the
  30 +        * displays
  31 +        */
  32 +       switch (vc4->gen) {
  33 +       case VC4_GEN_4:
  34 +               /* The COB is 20736 pixels, or just over 10 lines at 2048 wide.
  35 +                * The bottom 2048 pixels are full 32bpp RGBA (intended for the
  36 +                * TXP composing RGBA to memory), whilst the remainder are only
  37 +                * 24bpp RGB.
  38 +                *
  39 +                * Assign 3 lines to channels 1 & 2, and just over 4 lines to
  40 +                * channel 0.
  41 +                */
  42 +               #define VC4_COB_SIZE            20736
  43 +               #define VC4_COB_LINE_WIDTH      2048
  44 +               #define VC4_COB_NUM_LINES       3
  45 +               reg = 0;
  46 +               top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
  47 +               reg |= (top - 1) << 16;
  48 +               HVS_WRITE(SCALER_DISPBASE2, reg);
  49 +               reg = top;
  50 +               top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
  51 +               reg |= (top - 1) << 16;
  52 +               HVS_WRITE(SCALER_DISPBASE1, reg);
  53 +               reg = top;
  54 +               top = VC4_COB_SIZE;
  55 +               reg |= (top - 1) << 16;
  56 +               HVS_WRITE(SCALER_DISPBASE0, reg);
  57 +               break;
  58 +
  59 +       case VC4_GEN_5:
  60 +               /* The COB is 44416 pixels, or 10.8 lines at 4096 wide.
  61 +                * The bottom 4096 pixels are full RGBA (intended for the TXP
  62 +                * composing RGBA to memory), whilst the remainder are only
  63 +                * RGB. Addressing is always pixel wide.
  64 +                *
  65 +                * Assign 3 lines of 4096 to channels 1 & 2, and just over 4
  66 +                * lines. to channel 0.
  67 +                */
  68 +               #define VC5_COB_SIZE            44416
  69 +               #define VC5_COB_LINE_WIDTH      4096
  70 +               #define VC5_COB_NUM_LINES       3
  71 +               reg = 0;
  72 +               top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
  73 +               reg |= top << 16;
  74 +               HVS_WRITE(SCALER_DISPBASE2, reg);
  75 +               top += 16;
  76 +               reg = top;
  77 +               top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
  78 +               reg |= top << 16;
  79 +               HVS_WRITE(SCALER_DISPBASE1, reg);
  80 +               top += 16;
  81 +               reg = top;
  82 +               top = VC5_COB_SIZE;
  83 +               reg |= top << 16;
  84 +               HVS_WRITE(SCALER_DISPBASE0, reg);
  85 +               break;
  86 +
  87 +       default:
  88 +               return -EINVAL;
  89 +       }
  90 +
  91 +       return 0;
  92 +}
  93 +
  94  static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
  95  {
  96         struct platform_device *pdev = to_platform_device(dev);
  97 @@ -1386,7 +1457,6 @@ static int vc4_hvs_bind(struct device *d
  98         struct vc4_dev *vc4 = to_vc4_dev(drm);
  99         struct vc4_hvs *hvs = NULL;
 100         int ret;
 101 -       u32 reg, top;
 102
 103         hvs = __vc4_hvs_alloc(vc4, NULL);
 104         if (IS_ERR(hvs))
 105 @@ -1456,59 +1526,9 @@ static int vc4_hvs_bind(struct device *d
 106         if (ret)
 107                 return ret;
 108
 109 -       /* Recompute Composite Output Buffer (COB) allocations for the displays
 110 -        */
 111 -       if (vc4->gen == VC4_GEN_4) {
 112 -               /* The COB is 20736 pixels, or just over 10 lines at 2048 wide.
 113 -                * The bottom 2048 pixels are full 32bpp RGBA (intended for the
 114 -                * TXP composing RGBA to memory), whilst the remainder are only
 115 -                * 24bpp RGB.
 116 -                *
 117 -                * Assign 3 lines to channels 1 & 2, and just over 4 lines to
 118 -                * channel 0.
 119 -                */
 120 -               #define VC4_COB_SIZE            20736
 121 -               #define VC4_COB_LINE_WIDTH      2048
 122 -               #define VC4_COB_NUM_LINES       3
 123 -               reg = 0;
 124 -               top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
 125 -               reg |= (top - 1) << 16;
 126 -               HVS_WRITE(SCALER_DISPBASE2, reg);
 127 -               reg = top;
 128 -               top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
 129 -               reg |= (top - 1) << 16;
 130 -               HVS_WRITE(SCALER_DISPBASE1, reg);
 131 -               reg = top;
 132 -               top = VC4_COB_SIZE;
 133 -               reg |= (top - 1) << 16;
 134 -               HVS_WRITE(SCALER_DISPBASE0, reg);
 135 -       } else {
 136 -               /* The COB is 44416 pixels, or 10.8 lines at 4096 wide.
 137 -                * The bottom 4096 pixels are full RGBA (intended for the TXP
 138 -                * composing RGBA to memory), whilst the remainder are only
 139 -                * RGB. Addressing is always pixel wide.
 140 -                *
 141 -                * Assign 3 lines of 4096 to channels 1 & 2, and just over 4
 142 -                * lines. to channel 0.
 143 -                */
 144 -               #define VC5_COB_SIZE            44416
 145 -               #define VC5_COB_LINE_WIDTH      4096
 146 -               #define VC5_COB_NUM_LINES       3
 147 -               reg = 0;
 148 -               top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
 149 -               reg |= top << 16;
 150 -               HVS_WRITE(SCALER_DISPBASE2, reg);
 151 -               top += 16;
 152 -               reg = top;
 153 -               top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
 154 -               reg |= top << 16;
 155 -               HVS_WRITE(SCALER_DISPBASE1, reg);
 156 -               top += 16;
 157 -               reg = top;
 158 -               top = VC5_COB_SIZE;
 159 -               reg |= top << 16;
 160 -               HVS_WRITE(SCALER_DISPBASE0, reg);
 161 -       }
 162 +       ret = vc4_hvs_cob_init(hvs);
 163 +       if (ret)
 164 +               return ret;
 165
 166         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
 167                                vc4_hvs_irq_handler, 0, "vc4 hvs", drm);