bcm27xx: update 6.1 patches to latest version
[openwrt/staging/dangole.git] / target / linux / bcm27xx / patches-6.1 / 950-0916-dmaengine-bcm2835-Fix-dma-driver-for-BCM2835-38.patch
1 From 75f44d1416c5de17865247d6d012c37f7650437c Mon Sep 17 00:00:00 2001
2 From: Dom Cobley <popcornmix@gmail.com>
3 Date: Wed, 24 May 2023 19:32:16 +0100
4 Subject: [PATCH] dmaengine: bcm2835: Fix dma driver for BCM2835-38
5
6 The previous commit broke support on older devices.
7 Make the breaking parts of patch conditional on
8 the device being used.
9
10 Fixes: 6e1856ac7c39 ("dmaengine: bcm2835: HACK: Support DMA-Lite channels")
11
12 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
13 ---
14 drivers/dma/bcm2835-dma.c | 17 +++++++++++++----
15 1 file changed, 13 insertions(+), 4 deletions(-)
16
17 --- a/drivers/dma/bcm2835-dma.c
18 +++ b/drivers/dma/bcm2835-dma.c
19 @@ -102,6 +102,7 @@ struct bcm2835_chan {
20
21 bool is_lite_channel;
22 bool is_40bit_channel;
23 + bool is_2712;
24 };
25
26 struct bcm2835_desc {
27 @@ -550,7 +551,11 @@ static struct bcm2835_desc *bcm2835_dma_
28 control_block->info = info;
29 control_block->src = src;
30 control_block->dst = dst;
31 - control_block->stride = (upper_32_bits(dst) << 8) | upper_32_bits(src);
32 + if (c->is_2712)
33 + control_block->stride = (upper_32_bits(dst) << 8) |
34 + upper_32_bits(src);
35 + else
36 + control_block->stride = 0;
37 control_block->next = 0;
38 }
39
40 @@ -575,7 +580,8 @@ static struct bcm2835_desc *bcm2835_dma_
41 d->cb_list[frame - 1].cb)->next_cb =
42 to_40bit_cbaddr(cb_entry->paddr);
43 if (frame && !c->is_40bit_channel)
44 - d->cb_list[frame - 1].cb->next = to_40bit_cbaddr(cb_entry->paddr);
45 + d->cb_list[frame - 1].cb->next = c->is_2712 ?
46 + to_40bit_cbaddr(cb_entry->paddr) : cb_entry->paddr;
47
48 /* update src and dst and length */
49 if (src && (info & BCM2835_DMA_S_INC)) {
50 @@ -762,7 +768,7 @@ static void bcm2835_dma_start_desc(struc
51 } else {
52 writel(BIT(31), c->chan_base + BCM2835_DMA_CS);
53
54 - writel(to_40bit_cbaddr(d->cb_list[0].paddr),
55 + writel(c->is_2712 ? to_40bit_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr,
56 c->chan_base + BCM2835_DMA_ADDR);
57 writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),
58 c->chan_base + BCM2835_DMA_CS);
59 @@ -1132,7 +1138,8 @@ static struct dma_async_tx_descriptor *b
60 d->cb_list[frames - 1].cb)->next_cb =
61 to_40bit_cbaddr(d->cb_list[0].paddr);
62 else
63 - d->cb_list[d->frames - 1].cb->next = to_40bit_cbaddr(d->cb_list[0].paddr);
64 + d->cb_list[d->frames - 1].cb->next = c->is_2712 ?
65 + to_40bit_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr;
66
67 return vchan_tx_prep(&c->vc, &d->vd, flags);
68 }
69 @@ -1199,6 +1206,8 @@ static int bcm2835_dma_chan_init(struct
70 else if (readl(c->chan_base + BCM2835_DMA_DEBUG) &
71 BCM2835_DMA_DEBUG_LITE)
72 c->is_lite_channel = true;
73 + if (d->cfg_data->dma_mask == DMA_BIT_MASK(40))
74 + c->is_2712 = true;
75
76 return 0;
77 }