target/linux/bcm27xx/patches-6.1/950-0912-dmaengine-bcm2835-HACK-Support-DMA-Lite-channels.patch

   1 From a671a2774cb3bcfb144622149757f6821aa0604c Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Thu, 13 Apr 2023 16:52:19 +0200
   4 Subject: [PATCH] dmaengine: bcm2835: HACK: Support DMA-Lite channels
   5
   6 The BCM2712 has a DMA-Lite controller that is basically a BCM2835-style
   7 DMA controller that supports 40 bits DMA addresses.
   8
   9 We need it for HDMI audio to work, but this breaks BCM2835-38 so we
  10 should rework this later.
  11
  12 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  13 ---
  14  drivers/dma/bcm2835-dma.c | 11 +++++++----
  15  1 file changed, 7 insertions(+), 4 deletions(-)
  16
  17 --- a/drivers/dma/bcm2835-dma.c
  18 +++ b/drivers/dma/bcm2835-dma.c
  19 @@ -550,7 +550,7 @@ static struct bcm2835_desc *bcm2835_dma_
  20                         control_block->info = info;
  21                         control_block->src = src;
  22                         control_block->dst = dst;
  23 -                       control_block->stride = 0;
  24 +                       control_block->stride = (upper_32_bits(dst) << 8) | upper_32_bits(src);
  25                         control_block->next = 0;
  26                 }
  27
  28 @@ -575,7 +575,7 @@ static struct bcm2835_desc *bcm2835_dma_
  29                          d->cb_list[frame - 1].cb)->next_cb =
  30                                 to_bcm2711_cbaddr(cb_entry->paddr);
  31                 if (frame && !c->is_40bit_channel)
  32 -                       d->cb_list[frame - 1].cb->next = cb_entry->paddr;
  33 +                       d->cb_list[frame - 1].cb->next = to_bcm2711_cbaddr(cb_entry->paddr);
  34
  35                 /* update src and dst and length */
  36                 if (src && (info & BCM2835_DMA_S_INC)) {
  37 @@ -760,7 +760,10 @@ static void bcm2835_dma_start_desc(struc
  38                 writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT | BCM2711_DMA40_CS_FLAGS(c->dreq),
  39                        c->chan_base + BCM2711_DMA40_CS);
  40         } else {
  41 -               writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
  42 +               writel(BIT(31), c->chan_base + BCM2835_DMA_CS);
  43 +
  44 +               writel(to_bcm2711_cbaddr(d->cb_list[0].paddr),
  45 +                      c->chan_base + BCM2835_DMA_ADDR);
  46                 writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),
  47                        c->chan_base + BCM2835_DMA_CS);
  48         }
  49 @@ -1129,7 +1132,7 @@ static struct dma_async_tx_descriptor *b
  50                  d->cb_list[frames - 1].cb)->next_cb =
  51                         to_bcm2711_cbaddr(d->cb_list[0].paddr);
  52         else
  53 -               d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
  54 +               d->cb_list[d->frames - 1].cb->next = to_bcm2711_cbaddr(d->cb_list[0].paddr);
  55
  56         return vchan_tx_prep(&c->vc, &d->vd, flags);
  57  }