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bcm27xx: update 6.1 patches to latest version
[openwrt/staging/dangole.git] / target / linux / bcm27xx / patches-6.1 / 950-0887-drm-Add-RP1-VEC-driver.patch
1 From 09c2c6aad0fed44182defecd274579770feb0ae2 Mon Sep 17 00:00:00 2001
2 From: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
3 Date: Tue, 19 Sep 2023 17:54:41 +0100
4 Subject: [PATCH] drm: Add RP1 VEC driver
5
6 Add support for the RP1 VEC hardware.
7
8 Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
9 ---
10 drivers/gpu/drm/rp1/rp1-vec/Kconfig | 12 +
11 drivers/gpu/drm/rp1/rp1-vec/Makefile | 5 +
12 drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c | 539 ++++++++
13 drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h | 79 ++
14 drivers/gpu/drm/rp1/rp1-vec/rp1_vec_cfg.c | 508 ++++++++
15 drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c | 469 +++++++
16 drivers/gpu/drm/rp1/rp1-vec/vec_regs.h | 1420 +++++++++++++++++++++
17 7 files changed, 3032 insertions(+)
18 create mode 100644 drivers/gpu/drm/rp1/rp1-vec/Kconfig
19 create mode 100644 drivers/gpu/drm/rp1/rp1-vec/Makefile
20 create mode 100644 drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c
21 create mode 100644 drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h
22 create mode 100644 drivers/gpu/drm/rp1/rp1-vec/rp1_vec_cfg.c
23 create mode 100644 drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c
24 create mode 100644 drivers/gpu/drm/rp1/rp1-vec/vec_regs.h
25
26 --- /dev/null
27 +++ b/drivers/gpu/drm/rp1/rp1-vec/Kconfig
28 @@ -0,0 +1,12 @@
29 +# SPDX-License-Identifier: GPL-2.0-only
30 +config DRM_RP1_VEC
31 + tristate "DRM Support for RP1 VEC"
32 + depends on DRM
33 + select MFD_RP1
34 + select DRM_GEM_DMA_HELPER
35 + select DRM_KMS_HELPER
36 + select DRM_VRAM_HELPER
37 + select DRM_TTM
38 + select DRM_TTM_HELPER
39 + help
40 + Choose this option to enable Video Out on RP1
41 --- /dev/null
42 +++ b/drivers/gpu/drm/rp1/rp1-vec/Makefile
43 @@ -0,0 +1,5 @@
44 +# SPDX-License-Identifier: GPL-2.0-only
45 +
46 +drm-rp1-vec-y := rp1_vec.o rp1_vec_hw.o rp1_vec_cfg.o
47 +
48 +obj-$(CONFIG_DRM_RP1_VEC) += drm-rp1-vec.o
49 --- /dev/null
50 +++ b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c
51 @@ -0,0 +1,539 @@
52 +// SPDX-License-Identifier: GPL-2.0-or-later
53 +/*
54 + * DRM Driver for VEC output on Raspberry Pi RP1
55 + *
56 + * Copyright (c) 2023 Raspberry Pi Limited.
57 + */
58 +
59 +#include <linux/module.h>
60 +#include <linux/kernel.h>
61 +#include <linux/errno.h>
62 +#include <linux/string.h>
63 +#include <linux/slab.h>
64 +#include <linux/mm.h>
65 +#include <linux/fb.h>
66 +#include <linux/init.h>
67 +#include <linux/delay.h>
68 +#include <linux/interrupt.h>
69 +#include <linux/ioport.h>
70 +#include <linux/list.h>
71 +#include <linux/platform_device.h>
72 +#include <linux/clk.h>
73 +#include <linux/printk.h>
74 +#include <linux/console.h>
75 +#include <linux/debugfs.h>
76 +#include <linux/uaccess.h>
77 +#include <linux/io.h>
78 +#include <linux/dma-mapping.h>
79 +#include <linux/cred.h>
80 +#include <drm/drm_drv.h>
81 +#include <drm/drm_mm.h>
82 +#include <drm/drm_fourcc.h>
83 +#include <drm/drm_atomic_helper.h>
84 +#include <drm/drm_managed.h>
85 +#include <drm/drm_crtc.h>
86 +#include <drm/drm_crtc_helper.h>
87 +#include <drm/drm_encoder.h>
88 +#include <drm/drm_fb_helper.h>
89 +#include <drm/drm_framebuffer.h>
90 +#include <drm/drm_gem.h>
91 +#include <drm/drm_gem_atomic_helper.h>
92 +#include <drm/drm_gem_dma_helper.h>
93 +#include <drm/drm_gem_framebuffer_helper.h>
94 +#include <drm/drm_simple_kms_helper.h>
95 +#include <drm/drm_probe_helper.h>
96 +#include <drm/drm_modeset_helper_vtables.h>
97 +#include <drm/drm_vblank.h>
98 +#include <drm/drm_of.h>
99 +
100 +#include "rp1_vec.h"
101 +
102 +/*
103 + * Default TV standard parameter; it may be overridden by the OF
104 + * property "tv_norm" (which should be one of the strings below).
105 + *
106 + * The default (empty string) supports various 60Hz and 50Hz modes,
107 + * and will automatically select NTSC[-M] or PAL[-BDGHIKL]; the two
108 + * "fake" 60Hz standards NTSC-443 and PAL60 also support 50Hz PAL.
109 + * Other values will restrict the set of video modes offered.
110 + *
111 + * Finally, the DRM connector property "mode" (which is an integer)
112 + * can be used to override this value, but it does not prevent the
113 + * selection of an inapplicable video mode.
114 + */
115 +
116 +static char *rp1vec_tv_norm_str;
117 +module_param_named(tv_norm, rp1vec_tv_norm_str, charp, 0600);
118 +MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
119 + "\t\tSupported: NTSC, NTSC-J, NTSC-443, PAL, PAL-M, PAL-N,\n"
120 + "\t\t\tPAL60.\n"
121 + "\t\tDefault: empty string: infer PAL for a 50 Hz mode,\n"
122 + "\t\t\tNTSC otherwise");
123 +
124 +const char * const rp1vec_tvstd_names[] = {
125 + [RP1VEC_TVSTD_NTSC] = "NTSC",
126 + [RP1VEC_TVSTD_NTSC_J] = "NTSC-J",
127 + [RP1VEC_TVSTD_NTSC_443] = "NTSC-443",
128 + [RP1VEC_TVSTD_PAL] = "PAL",
129 + [RP1VEC_TVSTD_PAL_M] = "PAL-M",
130 + [RP1VEC_TVSTD_PAL_N] = "PAL-N",
131 + [RP1VEC_TVSTD_PAL60] = "PAL60",
132 + [RP1VEC_TVSTD_DEFAULT] = "",
133 +};
134 +
135 +static int rp1vec_parse_tv_norm(const char *str)
136 +{
137 + int i;
138 +
139 + if (str && *str) {
140 + for (i = 0; i < ARRAY_SIZE(rp1vec_tvstd_names); ++i) {
141 + if (strcasecmp(str, rp1vec_tvstd_names[i]) == 0)
142 + return i;
143 + }
144 + }
145 + return RP1VEC_TVSTD_DEFAULT;
146 +}
147 +
148 +static void rp1vec_pipe_update(struct drm_simple_display_pipe *pipe,
149 + struct drm_plane_state *old_state)
150 +{
151 + struct drm_pending_vblank_event *event;
152 + unsigned long flags;
153 + struct drm_framebuffer *fb = pipe->plane.state->fb;
154 + struct rp1_vec *vec = pipe->crtc.dev->dev_private;
155 + struct drm_gem_object *gem = fb ? drm_gem_fb_get_obj(fb, 0) : NULL;
156 + struct drm_gem_dma_object *dma_obj = gem ? to_drm_gem_dma_obj(gem) : NULL;
157 + bool can_update = fb && dma_obj && vec && vec->pipe_enabled;
158 +
159 + /* (Re-)start VEC where required; and update FB address */
160 + if (can_update) {
161 + if (!vec->vec_running || fb->format->format != vec->cur_fmt) {
162 + if (vec->vec_running && fb->format->format != vec->cur_fmt) {
163 + rp1vec_hw_stop(vec);
164 + vec->vec_running = false;
165 + }
166 + if (!vec->vec_running) {
167 + rp1vec_hw_setup(vec,
168 + fb->format->format,
169 + &pipe->crtc.state->mode,
170 + vec->connector.state->tv.mode);
171 + vec->vec_running = true;
172 + }
173 + vec->cur_fmt = fb->format->format;
174 + drm_crtc_vblank_on(&pipe->crtc);
175 + }
176 + rp1vec_hw_update(vec, dma_obj->dma_addr, fb->offsets[0], fb->pitches[0]);
177 + }
178 +
179 + /* Check if VBLANK callback needs to be armed (or sent immediately in some error cases).
180 + * Note there is a tiny probability of a race between rp1vec_dma_update() and IRQ;
181 + * ordering it this way around is safe, but theoretically might delay an extra frame.
182 + */
183 + spin_lock_irqsave(&pipe->crtc.dev->event_lock, flags);
184 + event = pipe->crtc.state->event;
185 + if (event) {
186 + pipe->crtc.state->event = NULL;
187 + if (can_update && drm_crtc_vblank_get(&pipe->crtc) == 0)
188 + drm_crtc_arm_vblank_event(&pipe->crtc, event);
189 + else
190 + drm_crtc_send_vblank_event(&pipe->crtc, event);
191 + }
192 + spin_unlock_irqrestore(&pipe->crtc.dev->event_lock, flags);
193 +}
194 +
195 +static void rp1vec_pipe_enable(struct drm_simple_display_pipe *pipe,
196 + struct drm_crtc_state *crtc_state,
197 + struct drm_plane_state *plane_state)
198 +{
199 + struct rp1_vec *vec = pipe->crtc.dev->dev_private;
200 +
201 + dev_info(&vec->pdev->dev, __func__);
202 + vec->pipe_enabled = true;
203 + vec->cur_fmt = 0xdeadbeef;
204 + rp1vec_vidout_setup(vec);
205 + rp1vec_pipe_update(pipe, 0);
206 +}
207 +
208 +static void rp1vec_pipe_disable(struct drm_simple_display_pipe *pipe)
209 +{
210 + struct rp1_vec *vec = pipe->crtc.dev->dev_private;
211 +
212 + dev_info(&vec->pdev->dev, __func__);
213 + drm_crtc_vblank_off(&pipe->crtc);
214 + if (vec) {
215 + if (vec->vec_running) {
216 + rp1vec_hw_stop(vec);
217 + vec->vec_running = false;
218 + }
219 + vec->pipe_enabled = false;
220 + }
221 +}
222 +
223 +static int rp1vec_pipe_enable_vblank(struct drm_simple_display_pipe *pipe)
224 +{
225 + if (pipe && pipe->crtc.dev) {
226 + struct rp1_vec *vec = pipe->crtc.dev->dev_private;
227 +
228 + if (vec)
229 + rp1vec_hw_vblank_ctrl(vec, 1);
230 + }
231 + return 0;
232 +}
233 +
234 +static void rp1vec_pipe_disable_vblank(struct drm_simple_display_pipe *pipe)
235 +{
236 + if (pipe && pipe->crtc.dev) {
237 + struct rp1_vec *vec = pipe->crtc.dev->dev_private;
238 +
239 + if (vec)
240 + rp1vec_hw_vblank_ctrl(vec, 0);
241 + }
242 +}
243 +
244 +static const struct drm_simple_display_pipe_funcs rp1vec_pipe_funcs = {
245 + .enable = rp1vec_pipe_enable,
246 + .update = rp1vec_pipe_update,
247 + .disable = rp1vec_pipe_disable,
248 + .prepare_fb = drm_gem_simple_display_pipe_prepare_fb,
249 + .enable_vblank = rp1vec_pipe_enable_vblank,
250 + .disable_vblank = rp1vec_pipe_disable_vblank,
251 +};
252 +
253 +static void rp1vec_connector_destroy(struct drm_connector *connector)
254 +{
255 + drm_connector_unregister(connector);
256 + drm_connector_cleanup(connector);
257 +}
258 +
259 +static const struct drm_display_mode rp1vec_modes[4] = {
260 + { /* Full size 525/60i with Rec.601 pixel rate */
261 + DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500,
262 + 720, 720 + 14, 720 + 14 + 64, 858, 0,
263 + 480, 480 + 7, 480 + 7 + 6, 525, 0,
264 + DRM_MODE_FLAG_INTERLACE)
265 + },
266 + { /* Cropped and horizontally squashed to be TV-safe */
267 + DRM_MODE("704x432i", DRM_MODE_TYPE_DRIVER, 15429,
268 + 704, 704 + 72, 704 + 72 + 72, 980, 0,
269 + 432, 432 + 31, 432 + 31 + 6, 525, 0,
270 + DRM_MODE_FLAG_INTERLACE)
271 + },
272 + { /* Full size 625/50i with Rec.601 pixel rate */
273 + DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500,
274 + 720, 720 + 20, 720 + 20 + 64, 864, 0,
275 + 576, 576 + 4, 576 + 4 + 6, 625, 0,
276 + DRM_MODE_FLAG_INTERLACE)
277 + },
278 + { /* Cropped and squashed, for square(ish) pixels */
279 + DRM_MODE("704x512i", DRM_MODE_TYPE_DRIVER, 15429,
280 + 704, 704 + 80, 704 + 80 + 72, 987, 0,
281 + 512, 512 + 36, 512 + 36 + 6, 625, 0,
282 + DRM_MODE_FLAG_INTERLACE)
283 + }
284 +};
285 +
286 +static int rp1vec_connector_get_modes(struct drm_connector *connector)
287 +{
288 + struct rp1_vec *vec = container_of(connector, struct rp1_vec, connector);
289 + bool ok525 = RP1VEC_TVSTD_SUPPORT_525(vec->tv_norm);
290 + bool ok625 = RP1VEC_TVSTD_SUPPORT_625(vec->tv_norm);
291 + int i, prog, n = 0;
292 +
293 + for (i = 0; i < ARRAY_SIZE(rp1vec_modes); i++) {
294 + if ((rp1vec_modes[i].vtotal == 625) ? ok625 : ok525) {
295 + for (prog = 0; prog < 2; prog++) {
296 + struct drm_display_mode *mode =
297 + drm_mode_duplicate(connector->dev,
298 + &rp1vec_modes[i]);
299 +
300 + if (prog) {
301 + mode->flags &= ~DRM_MODE_FLAG_INTERLACE;
302 + mode->vdisplay >>= 1;
303 + mode->vsync_start >>= 1;
304 + mode->vsync_end >>= 1;
305 + mode->vtotal >>= 1;
306 + }
307 +
308 + if (mode->hdisplay == 704 &&
309 + mode->vtotal == ((ok525) ? 525 : 625))
310 + mode->type |= DRM_MODE_TYPE_PREFERRED;
311 +
312 + drm_mode_set_name(mode);
313 + drm_mode_probed_add(connector, mode);
314 + n++;
315 + }
316 + }
317 + }
318 +
319 + return n;
320 +}
321 +
322 +static void rp1vec_connector_reset(struct drm_connector *connector)
323 +{
324 + struct rp1_vec *vec = container_of(connector, struct rp1_vec, connector);
325 +
326 + drm_atomic_helper_connector_reset(connector);
327 + if (connector->state)
328 + connector->state->tv.mode = vec->tv_norm;
329 +}
330 +
331 +static int rp1vec_connector_atomic_check(struct drm_connector *conn,
332 + struct drm_atomic_state *state)
333 +{ struct drm_connector_state *old_state =
334 + drm_atomic_get_old_connector_state(state, conn);
335 + struct drm_connector_state *new_state =
336 + drm_atomic_get_new_connector_state(state, conn);
337 +
338 + if (new_state->crtc && old_state->tv.mode != new_state->tv.mode) {
339 + struct drm_crtc_state *crtc_state =
340 + drm_atomic_get_new_crtc_state(state, new_state->crtc);
341 +
342 + crtc_state->mode_changed = true;
343 + }
344 +
345 + return 0;
346 +}
347 +
348 +static enum drm_mode_status rp1vec_mode_valid(struct drm_device *dev,
349 + const struct drm_display_mode *mode)
350 +{
351 + /*
352 + * Check the mode roughly matches one of our standard modes
353 + * (optionally half-height and progressive). Ignore H/V sync
354 + * timings which for interlaced TV are approximate at best.
355 + */
356 + int i, prog;
357 +
358 + prog = !(mode->flags & DRM_MODE_FLAG_INTERLACE);
359 +
360 + for (i = 0; i < ARRAY_SIZE(rp1vec_modes); i++) {
361 + const struct drm_display_mode *ref = rp1vec_modes + i;
362 +
363 + if (mode->hdisplay == ref->hdisplay &&
364 + mode->vdisplay == (ref->vdisplay >> prog) &&
365 + mode->clock + 2 >= ref->clock &&
366 + mode->clock <= ref->clock + 2 &&
367 + mode->htotal + 2 >= ref->htotal &&
368 + mode->htotal <= ref->htotal + 2 &&
369 + mode->vtotal + 2 >= (ref->vtotal >> prog) &&
370 + mode->vtotal <= (ref->vtotal >> prog) + 2)
371 + return MODE_OK;
372 + }
373 + return MODE_BAD;
374 +}
375 +
376 +static const struct drm_connector_helper_funcs rp1vec_connector_helper_funcs = {
377 + .get_modes = rp1vec_connector_get_modes,
378 + .atomic_check = rp1vec_connector_atomic_check,
379 +};
380 +
381 +static const struct drm_connector_funcs rp1vec_connector_funcs = {
382 + .fill_modes = drm_helper_probe_single_connector_modes,
383 + .destroy = rp1vec_connector_destroy,
384 + .reset = rp1vec_connector_reset,
385 + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
386 + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
387 +};
388 +
389 +static const struct drm_mode_config_funcs rp1vec_mode_funcs = {
390 + .fb_create = drm_gem_fb_create,
391 + .atomic_check = drm_atomic_helper_check,
392 + .atomic_commit = drm_atomic_helper_commit,
393 + .mode_valid = rp1vec_mode_valid,
394 +};
395 +
396 +static const u32 rp1vec_formats[] = {
397 + DRM_FORMAT_XRGB8888,
398 + DRM_FORMAT_XBGR8888,
399 + DRM_FORMAT_RGB888,
400 + DRM_FORMAT_BGR888,
401 + DRM_FORMAT_RGB565
402 +};
403 +
404 +static void rp1vec_stopall(struct drm_device *drm)
405 +{
406 + if (drm->dev_private) {
407 + struct rp1_vec *vec = drm->dev_private;
408 +
409 + if (vec->vec_running || rp1vec_hw_busy(vec)) {
410 + rp1vec_hw_stop(vec);
411 + vec->vec_running = false;
412 + }
413 + rp1vec_vidout_poweroff(vec);
414 + }
415 +}
416 +
417 +DEFINE_DRM_GEM_DMA_FOPS(rp1vec_fops);
418 +
419 +static struct drm_driver rp1vec_driver = {
420 + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
421 + .fops = &rp1vec_fops,
422 + .name = "drm-rp1-vec",
423 + .desc = "drm-rp1-vec",
424 + .date = "0",
425 + .major = 1,
426 + .minor = 0,
427 + DRM_GEM_DMA_DRIVER_OPS,
428 + .release = rp1vec_stopall,
429 +};
430 +
431 +static int rp1vec_platform_probe(struct platform_device *pdev)
432 +{
433 + struct device *dev = &pdev->dev;
434 + struct drm_device *drm;
435 + struct rp1_vec *vec;
436 + const char *str;
437 + int i, ret;
438 +
439 + dev_info(dev, __func__);
440 + drm = drm_dev_alloc(&rp1vec_driver, dev);
441 + if (IS_ERR(drm)) {
442 + ret = PTR_ERR(drm);
443 + dev_err(dev, "%s drm_dev_alloc %d", __func__, ret);
444 + return ret;
445 + }
446 +
447 + vec = drmm_kzalloc(drm, sizeof(*vec), GFP_KERNEL);
448 + if (!vec) {
449 + dev_err(dev, "%s drmm_kzalloc failed", __func__);
450 + ret = -ENOMEM;
451 + goto err_free_drm;
452 + }
453 + init_completion(&vec->finished);
454 + vec->drm = drm;
455 + vec->pdev = pdev;
456 + drm->dev_private = vec;
457 + platform_set_drvdata(pdev, drm);
458 +
459 + str = rp1vec_tv_norm_str;
460 + of_property_read_string(dev->of_node, "tv_norm", &str);
461 + vec->tv_norm = rp1vec_parse_tv_norm(str);
462 +
463 + for (i = 0; i < RP1VEC_NUM_HW_BLOCKS; i++) {
464 + vec->hw_base[i] =
465 + devm_ioremap_resource(dev,
466 + platform_get_resource(vec->pdev, IORESOURCE_MEM, i));
467 + if (IS_ERR(vec->hw_base[i])) {
468 + ret = PTR_ERR(vec->hw_base[i]);
469 + dev_err(dev, "Error memory mapping regs[%d]\n", i);
470 + goto err_free_drm;
471 + }
472 + }
473 + ret = platform_get_irq(vec->pdev, 0);
474 + if (ret > 0)
475 + ret = devm_request_irq(dev, ret, rp1vec_hw_isr,
476 + IRQF_SHARED, "rp1-vec", vec);
477 + if (ret) {
478 + dev_err(dev, "Unable to request interrupt\n");
479 + ret = -EINVAL;
480 + goto err_free_drm;
481 + }
482 + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
483 +
484 + vec->vec_clock = devm_clk_get(dev, NULL);
485 + if (IS_ERR(vec->vec_clock)) {
486 + ret = PTR_ERR(vec->vec_clock);
487 + goto err_free_drm;
488 + }
489 + ret = clk_prepare_enable(vec->vec_clock);
490 +
491 + ret = drmm_mode_config_init(drm);
492 + if (ret)
493 + goto err_free_drm;
494 + drm->mode_config.max_width = 768;
495 + drm->mode_config.max_height = 576;
496 + drm->mode_config.fb_base = 0;
497 + drm->mode_config.preferred_depth = 32;
498 + drm->mode_config.prefer_shadow = 0;
499 + drm->mode_config.prefer_shadow_fbdev = 1;
500 + //drm->mode_config.fbdev_use_iomem = false;
501 + drm->mode_config.quirk_addfb_prefer_host_byte_order = true;
502 + drm->mode_config.funcs = &rp1vec_mode_funcs;
503 + drm_vblank_init(drm, 1);
504 +
505 + ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(rp1vec_tvstd_names),
506 + rp1vec_tvstd_names);
507 + if (ret)
508 + goto err_free_drm;
509 +
510 + drm_connector_init(drm, &vec->connector, &rp1vec_connector_funcs,
511 + DRM_MODE_CONNECTOR_Composite);
512 + if (ret)
513 + goto err_free_drm;
514 +
515 + vec->connector.interlace_allowed = true;
516 + drm_connector_helper_add(&vec->connector, &rp1vec_connector_helper_funcs);
517 +
518 + drm_object_attach_property(&vec->connector.base,
519 + drm->mode_config.tv_mode_property,
520 + vec->tv_norm);
521 +
522 + ret = drm_simple_display_pipe_init(drm,
523 + &vec->pipe,
524 + &rp1vec_pipe_funcs,
525 + rp1vec_formats,
526 + ARRAY_SIZE(rp1vec_formats),
527 + NULL,
528 + &vec->connector);
529 + if (ret)
530 + goto err_free_drm;
531 +
532 + drm_mode_config_reset(drm);
533 +
534 + ret = drm_dev_register(drm, 0);
535 + if (ret)
536 + goto err_free_drm;
537 +
538 + drm_fbdev_generic_setup(drm, 32); /* the "32" is preferred BPP */
539 + return ret;
540 +
541 +err_free_drm:
542 + dev_info(dev, "%s fail %d", __func__, ret);
543 + drm_dev_put(drm);
544 + return ret;
545 +}
546 +
547 +static int rp1vec_platform_remove(struct platform_device *pdev)
548 +{
549 + struct drm_device *drm = platform_get_drvdata(pdev);
550 +
551 + rp1vec_stopall(drm);
552 + drm_dev_unregister(drm);
553 + drm_atomic_helper_shutdown(drm);
554 + drm_dev_put(drm);
555 +
556 + return 0;
557 +}
558 +
559 +static void rp1vec_platform_shutdown(struct platform_device *pdev)
560 +{
561 + struct drm_device *drm = platform_get_drvdata(pdev);
562 +
563 + rp1vec_stopall(drm);
564 +}
565 +
566 +static const struct of_device_id rp1vec_of_match[] = {
567 + {
568 + .compatible = "raspberrypi,rp1vec",
569 + },
570 + { /* sentinel */ },
571 +};
572 +
573 +MODULE_DEVICE_TABLE(of, rp1vec_of_match);
574 +
575 +static struct platform_driver rp1vec_platform_driver = {
576 + .probe = rp1vec_platform_probe,
577 + .remove = rp1vec_platform_remove,
578 + .shutdown = rp1vec_platform_shutdown,
579 + .driver = {
580 + .name = DRIVER_NAME,
581 + .owner = THIS_MODULE,
582 + .of_match_table = rp1vec_of_match,
583 + },
584 +};
585 +
586 +module_platform_driver(rp1vec_platform_driver);
587 +
588 +MODULE_LICENSE("GPL");
589 +MODULE_DESCRIPTION("DRM driver for Composite Video on Raspberry Pi RP1");
590 +MODULE_AUTHOR("Nick Hollinghurst");
591 --- /dev/null
592 +++ b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h
593 @@ -0,0 +1,79 @@
594 +/* SPDX-License-Identifier: GPL-2.0 */
595 +/*
596 + * DRM Driver for DSI output on Raspberry Pi RP1
597 + *
598 + * Copyright (c) 2023 Raspberry Pi Limited.
599 + */
600 +
601 +#include <linux/types.h>
602 +#include <linux/io.h>
603 +#include <linux/clk.h>
604 +#include <drm/drm_device.h>
605 +#include <drm/drm_simple_kms_helper.h>
606 +
607 +#define MODULE_NAME "drm-rp1-vec"
608 +#define DRIVER_NAME "drm-rp1-vec"
609 +
610 +/* ---------------------------------------------------------------------- */
611 +
612 +#define RP1VEC_HW_BLOCK_VEC 0
613 +#define RP1VEC_HW_BLOCK_CFG 1
614 +#define RP1VEC_NUM_HW_BLOCKS 2
615 +
616 +enum {
617 + RP1VEC_TVSTD_NTSC = 0, /* +525 => NTSC 625 => PAL */
618 + RP1VEC_TVSTD_NTSC_J, /* +525 => NTSC-J 625 => PAL */
619 + RP1VEC_TVSTD_NTSC_443, /* +525 => NTSC-443 +625 => PAL */
620 + RP1VEC_TVSTD_PAL, /* 525 => NTSC +625 => PAL */
621 + RP1VEC_TVSTD_PAL_M, /* +525 => PAL-M 625 => PAL */
622 + RP1VEC_TVSTD_PAL_N, /* 525 => NTSC +625 => PAL-N */
623 + RP1VEC_TVSTD_PAL60, /* +525 => PAL60 +625 => PAL */
624 + RP1VEC_TVSTD_DEFAULT, /* +525 => NTSC +625 => PAL */
625 +};
626 +
627 +/* Which standards support which modes? Those marked with + above */
628 +#define RP1VEC_TVSTD_SUPPORT_525(n) ((0xD7 >> (n)) & 1)
629 +#define RP1VEC_TVSTD_SUPPORT_625(n) ((0xEC >> (n)) & 1)
630 +
631 +/* ---------------------------------------------------------------------- */
632 +
633 +struct rp1_vec {
634 + /* DRM and platform device pointers */
635 + struct drm_device *drm;
636 + struct platform_device *pdev;
637 +
638 + /* Framework and helper objects */
639 + struct drm_simple_display_pipe pipe;
640 + struct drm_connector connector;
641 +
642 + /* Clock. We assume this is always at 108 MHz. */
643 + struct clk *vec_clock;
644 +
645 + /* Block (VCC, CFG) base addresses, and current state */
646 + void __iomem *hw_base[RP1VEC_NUM_HW_BLOCKS];
647 + u32 cur_fmt;
648 + int tv_norm;
649 + bool vec_running, pipe_enabled;
650 + struct completion finished;
651 +};
652 +
653 +extern const char * const rp1vec_tvstd_names[];
654 +
655 +/* ---------------------------------------------------------------------- */
656 +/* Functions to control the VEC/DMA block */
657 +
658 +void rp1vec_hw_setup(struct rp1_vec *vec,
659 + u32 in_format,
660 + struct drm_display_mode const *mode,
661 + int tvstd);
662 +void rp1vec_hw_update(struct rp1_vec *vec, dma_addr_t addr, u32 offset, u32 stride);
663 +void rp1vec_hw_stop(struct rp1_vec *vec);
664 +int rp1vec_hw_busy(struct rp1_vec *vec);
665 +irqreturn_t rp1vec_hw_isr(int irq, void *dev);
666 +void rp1vec_hw_vblank_ctrl(struct rp1_vec *vec, int enable);
667 +
668 +/* ---------------------------------------------------------------------- */
669 +/* Functions to control the VIDEO OUT CFG block and check RP1 platform */
670 +
671 +void rp1vec_vidout_setup(struct rp1_vec *vec);
672 +void rp1vec_vidout_poweroff(struct rp1_vec *vec);
673 --- /dev/null
674 +++ b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_cfg.c
675 @@ -0,0 +1,508 @@
676 +// SPDX-License-Identifier: GPL-2.0-or-later
677 +/*
678 + * DRM Driver for DSI output on Raspberry Pi RP1
679 + *
680 + * Copyright (c) 2023 Raspberry Pi Limited.
681 + */
682 +
683 +#include <linux/kernel.h>
684 +#include <linux/errno.h>
685 +#include <linux/mm.h>
686 +#include <linux/delay.h>
687 +#include <linux/interrupt.h>
688 +#include <linux/platform_device.h>
689 +#include <linux/printk.h>
690 +#include <linux/rp1_platform.h>
691 +
692 +#include "rp1_vec.h"
693 +
694 +// =============================================================================
695 +// Register : VIDEO_OUT_CFG_SEL
696 +// JTAG access : synchronous
697 +// Description : Selects source: VEC or DPI
698 +#define VIDEO_OUT_CFG_SEL_OFFSET 0x00000000
699 +#define VIDEO_OUT_CFG_SEL_BITS 0x00000013
700 +#define VIDEO_OUT_CFG_SEL_RESET 0x00000000
701 +// -----------------------------------------------------------------------------
702 +// Field : VIDEO_OUT_CFG_SEL_PCLK_INV
703 +// Description : Select dpi_pclk output port polarity inversion.
704 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_RESET 0x0
705 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_BITS 0x00000010
706 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_MSB 4
707 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_LSB 4
708 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_ACCESS "RW"
709 +// -----------------------------------------------------------------------------
710 +// Field : VIDEO_OUT_CFG_SEL_PAD_MUX
711 +// Description : VEC 1 DPI 0
712 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_RESET 0x0
713 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_BITS 0x00000002
714 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_MSB 1
715 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_LSB 1
716 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_ACCESS "RW"
717 +// -----------------------------------------------------------------------------
718 +// Field : VIDEO_OUT_CFG_SEL_VDAC_MUX
719 +// Description : VEC 1 DPI 0
720 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_RESET 0x0
721 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_BITS 0x00000001
722 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_MSB 0
723 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_LSB 0
724 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_ACCESS "RW"
725 +// =============================================================================
726 +// Register : VIDEO_OUT_CFG_VDAC_CFG
727 +// JTAG access : synchronous
728 +// Description : Configure SNPS VDAC
729 +#define VIDEO_OUT_CFG_VDAC_CFG_OFFSET 0x00000004
730 +#define VIDEO_OUT_CFG_VDAC_CFG_BITS 0x1fffffff
731 +#define VIDEO_OUT_CFG_VDAC_CFG_RESET 0x0003ffff
732 +// -----------------------------------------------------------------------------
733 +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENCTR
734 +// Description : None
735 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_RESET 0x0
736 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_BITS 0x1c000000
737 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_MSB 28
738 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_LSB 26
739 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_ACCESS "RW"
740 +// -----------------------------------------------------------------------------
741 +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENSC
742 +// Description : None
743 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_RESET 0x0
744 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_BITS 0x03800000
745 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_MSB 25
746 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_LSB 23
747 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_ACCESS "RW"
748 +// -----------------------------------------------------------------------------
749 +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENDAC
750 +// Description : None
751 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_RESET 0x0
752 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_BITS 0x00700000
753 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_MSB 22
754 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_LSB 20
755 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_ACCESS "RW"
756 +// -----------------------------------------------------------------------------
757 +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENVBG
758 +// Description : None
759 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_RESET 0x0
760 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_BITS 0x00080000
761 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_MSB 19
762 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_LSB 19
763 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_ACCESS "RW"
764 +// -----------------------------------------------------------------------------
765 +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF
766 +// Description : None
767 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_RESET 0x0
768 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_BITS 0x00040000
769 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_MSB 18
770 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_LSB 18
771 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_ACCESS "RW"
772 +// -----------------------------------------------------------------------------
773 +// Field : VIDEO_OUT_CFG_VDAC_CFG_DAC2GC
774 +// Description : dac2 gain control
775 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_RESET 0x3f
776 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_BITS 0x0003f000
777 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_MSB 17
778 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_LSB 12
779 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_ACCESS "RW"
780 +// -----------------------------------------------------------------------------
781 +// Field : VIDEO_OUT_CFG_VDAC_CFG_DAC1GC
782 +// Description : dac1 gain control
783 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_RESET 0x3f
784 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_BITS 0x00000fc0
785 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_MSB 11
786 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_LSB 6
787 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_ACCESS "RW"
788 +// -----------------------------------------------------------------------------
789 +// Field : VIDEO_OUT_CFG_VDAC_CFG_DAC0GC
790 +// Description : dac0 gain control
791 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_RESET 0x3f
792 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_BITS 0x0000003f
793 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_MSB 5
794 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_LSB 0
795 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_ACCESS "RW"
796 +// =============================================================================
797 +// Register : VIDEO_OUT_CFG_VDAC_STATUS
798 +// JTAG access : synchronous
799 +// Description : Read VDAC status
800 +#define VIDEO_OUT_CFG_VDAC_STATUS_OFFSET 0x00000008
801 +#define VIDEO_OUT_CFG_VDAC_STATUS_BITS 0x00000017
802 +#define VIDEO_OUT_CFG_VDAC_STATUS_RESET 0x00000000
803 +// -----------------------------------------------------------------------------
804 +// Field : VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3
805 +// Description : None
806 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_RESET 0x0
807 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_BITS 0x00000010
808 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_MSB 4
809 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_LSB 4
810 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_ACCESS "RO"
811 +// -----------------------------------------------------------------------------
812 +// Field : VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT
813 +// Description : None
814 +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_RESET "-"
815 +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_BITS 0x00000007
816 +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_MSB 2
817 +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_LSB 0
818 +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_ACCESS "RO"
819 +// =============================================================================
820 +// Register : VIDEO_OUT_CFG_MEM_PD
821 +// JTAG access : synchronous
822 +// Description : Control memory power down
823 +#define VIDEO_OUT_CFG_MEM_PD_OFFSET 0x0000000c
824 +#define VIDEO_OUT_CFG_MEM_PD_BITS 0x00000003
825 +#define VIDEO_OUT_CFG_MEM_PD_RESET 0x00000000
826 +// -----------------------------------------------------------------------------
827 +// Field : VIDEO_OUT_CFG_MEM_PD_VEC
828 +// Description : None
829 +#define VIDEO_OUT_CFG_MEM_PD_VEC_RESET 0x0
830 +#define VIDEO_OUT_CFG_MEM_PD_VEC_BITS 0x00000002
831 +#define VIDEO_OUT_CFG_MEM_PD_VEC_MSB 1
832 +#define VIDEO_OUT_CFG_MEM_PD_VEC_LSB 1
833 +#define VIDEO_OUT_CFG_MEM_PD_VEC_ACCESS "RW"
834 +// -----------------------------------------------------------------------------
835 +// Field : VIDEO_OUT_CFG_MEM_PD_DPI
836 +// Description : None
837 +#define VIDEO_OUT_CFG_MEM_PD_DPI_RESET 0x0
838 +#define VIDEO_OUT_CFG_MEM_PD_DPI_BITS 0x00000001
839 +#define VIDEO_OUT_CFG_MEM_PD_DPI_MSB 0
840 +#define VIDEO_OUT_CFG_MEM_PD_DPI_LSB 0
841 +#define VIDEO_OUT_CFG_MEM_PD_DPI_ACCESS "RW"
842 +// =============================================================================
843 +// Register : VIDEO_OUT_CFG_TEST_OVERRIDE
844 +// JTAG access : synchronous
845 +// Description : None
846 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_OFFSET 0x00000010
847 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_BITS 0xffffffff
848 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RESET 0x00000000
849 +// -----------------------------------------------------------------------------
850 +// Field : VIDEO_OUT_CFG_TEST_OVERRIDE_PAD
851 +// Description : None
852 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_RESET 0x0
853 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_BITS 0x80000000
854 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_MSB 31
855 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_LSB 31
856 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_ACCESS "RW"
857 +// -----------------------------------------------------------------------------
858 +// Field : VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC
859 +// Description : None
860 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_RESET 0x0
861 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_BITS 0x40000000
862 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_MSB 30
863 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_LSB 30
864 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_ACCESS "RW"
865 +// -----------------------------------------------------------------------------
866 +// Field : VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL
867 +// Description : None
868 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_RESET 0x00000000
869 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_BITS 0x3fffffff
870 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_MSB 29
871 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_LSB 0
872 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_ACCESS "RW"
873 +// =============================================================================
874 +// Register : VIDEO_OUT_CFG_INTR
875 +// JTAG access : synchronous
876 +// Description : Raw Interrupts
877 +#define VIDEO_OUT_CFG_INTR_OFFSET 0x00000014
878 +#define VIDEO_OUT_CFG_INTR_BITS 0x00000003
879 +#define VIDEO_OUT_CFG_INTR_RESET 0x00000000
880 +// -----------------------------------------------------------------------------
881 +// Field : VIDEO_OUT_CFG_INTR_DPI
882 +// Description : None
883 +#define VIDEO_OUT_CFG_INTR_DPI_RESET 0x0
884 +#define VIDEO_OUT_CFG_INTR_DPI_BITS 0x00000002
885 +#define VIDEO_OUT_CFG_INTR_DPI_MSB 1
886 +#define VIDEO_OUT_CFG_INTR_DPI_LSB 1
887 +#define VIDEO_OUT_CFG_INTR_DPI_ACCESS "RO"
888 +// -----------------------------------------------------------------------------
889 +// Field : VIDEO_OUT_CFG_INTR_VEC
890 +// Description : None
891 +#define VIDEO_OUT_CFG_INTR_VEC_RESET 0x0
892 +#define VIDEO_OUT_CFG_INTR_VEC_BITS 0x00000001
893 +#define VIDEO_OUT_CFG_INTR_VEC_MSB 0
894 +#define VIDEO_OUT_CFG_INTR_VEC_LSB 0
895 +#define VIDEO_OUT_CFG_INTR_VEC_ACCESS "RO"
896 +// =============================================================================
897 +// Register : VIDEO_OUT_CFG_INTE
898 +// JTAG access : synchronous
899 +// Description : Interrupt Enable
900 +#define VIDEO_OUT_CFG_INTE_OFFSET 0x00000018
901 +#define VIDEO_OUT_CFG_INTE_BITS 0x00000003
902 +#define VIDEO_OUT_CFG_INTE_RESET 0x00000000
903 +// -----------------------------------------------------------------------------
904 +// Field : VIDEO_OUT_CFG_INTE_DPI
905 +// Description : None
906 +#define VIDEO_OUT_CFG_INTE_DPI_RESET 0x0
907 +#define VIDEO_OUT_CFG_INTE_DPI_BITS 0x00000002
908 +#define VIDEO_OUT_CFG_INTE_DPI_MSB 1
909 +#define VIDEO_OUT_CFG_INTE_DPI_LSB 1
910 +#define VIDEO_OUT_CFG_INTE_DPI_ACCESS "RW"
911 +// -----------------------------------------------------------------------------
912 +// Field : VIDEO_OUT_CFG_INTE_VEC
913 +// Description : None
914 +#define VIDEO_OUT_CFG_INTE_VEC_RESET 0x0
915 +#define VIDEO_OUT_CFG_INTE_VEC_BITS 0x00000001
916 +#define VIDEO_OUT_CFG_INTE_VEC_MSB 0
917 +#define VIDEO_OUT_CFG_INTE_VEC_LSB 0
918 +#define VIDEO_OUT_CFG_INTE_VEC_ACCESS "RW"
919 +// =============================================================================
920 +// Register : VIDEO_OUT_CFG_INTF
921 +// JTAG access : synchronous
922 +// Description : Interrupt Force
923 +#define VIDEO_OUT_CFG_INTF_OFFSET 0x0000001c
924 +#define VIDEO_OUT_CFG_INTF_BITS 0x00000003
925 +#define VIDEO_OUT_CFG_INTF_RESET 0x00000000
926 +// -----------------------------------------------------------------------------
927 +// Field : VIDEO_OUT_CFG_INTF_DPI
928 +// Description : None
929 +#define VIDEO_OUT_CFG_INTF_DPI_RESET 0x0
930 +#define VIDEO_OUT_CFG_INTF_DPI_BITS 0x00000002
931 +#define VIDEO_OUT_CFG_INTF_DPI_MSB 1
932 +#define VIDEO_OUT_CFG_INTF_DPI_LSB 1
933 +#define VIDEO_OUT_CFG_INTF_DPI_ACCESS "RW"
934 +// -----------------------------------------------------------------------------
935 +// Field : VIDEO_OUT_CFG_INTF_VEC
936 +// Description : None
937 +#define VIDEO_OUT_CFG_INTF_VEC_RESET 0x0
938 +#define VIDEO_OUT_CFG_INTF_VEC_BITS 0x00000001
939 +#define VIDEO_OUT_CFG_INTF_VEC_MSB 0
940 +#define VIDEO_OUT_CFG_INTF_VEC_LSB 0
941 +#define VIDEO_OUT_CFG_INTF_VEC_ACCESS "RW"
942 +// =============================================================================
943 +// Register : VIDEO_OUT_CFG_INTS
944 +// JTAG access : synchronous
945 +// Description : Interrupt status after masking & forcing
946 +#define VIDEO_OUT_CFG_INTS_OFFSET 0x00000020
947 +#define VIDEO_OUT_CFG_INTS_BITS 0x00000003
948 +#define VIDEO_OUT_CFG_INTS_RESET 0x00000000
949 +// -----------------------------------------------------------------------------
950 +// Field : VIDEO_OUT_CFG_INTS_DPI
951 +// Description : None
952 +#define VIDEO_OUT_CFG_INTS_DPI_RESET 0x0
953 +#define VIDEO_OUT_CFG_INTS_DPI_BITS 0x00000002
954 +#define VIDEO_OUT_CFG_INTS_DPI_MSB 1
955 +#define VIDEO_OUT_CFG_INTS_DPI_LSB 1
956 +#define VIDEO_OUT_CFG_INTS_DPI_ACCESS "RO"
957 +// -----------------------------------------------------------------------------
958 +// Field : VIDEO_OUT_CFG_INTS_VEC
959 +// Description : None
960 +#define VIDEO_OUT_CFG_INTS_VEC_RESET 0x0
961 +#define VIDEO_OUT_CFG_INTS_VEC_BITS 0x00000001
962 +#define VIDEO_OUT_CFG_INTS_VEC_MSB 0
963 +#define VIDEO_OUT_CFG_INTS_VEC_LSB 0
964 +#define VIDEO_OUT_CFG_INTS_VEC_ACCESS "RO"
965 +// =============================================================================
966 +// Register : VIDEO_OUT_CFG_BLOCK_ID
967 +// JTAG access : synchronous
968 +// Description : Block Identifier
969 +// Hexadecimal representation of "VOCF"
970 +#define VIDEO_OUT_CFG_BLOCK_ID_OFFSET 0x00000024
971 +#define VIDEO_OUT_CFG_BLOCK_ID_BITS 0xffffffff
972 +#define VIDEO_OUT_CFG_BLOCK_ID_RESET 0x564f4346
973 +#define VIDEO_OUT_CFG_BLOCK_ID_MSB 31
974 +#define VIDEO_OUT_CFG_BLOCK_ID_LSB 0
975 +#define VIDEO_OUT_CFG_BLOCK_ID_ACCESS "RO"
976 +// =============================================================================
977 +// Register : VIDEO_OUT_CFG_INSTANCE_ID
978 +// JTAG access : synchronous
979 +// Description : Block Instance Identifier
980 +#define VIDEO_OUT_CFG_INSTANCE_ID_OFFSET 0x00000028
981 +#define VIDEO_OUT_CFG_INSTANCE_ID_BITS 0x0000000f
982 +#define VIDEO_OUT_CFG_INSTANCE_ID_RESET 0x00000000
983 +#define VIDEO_OUT_CFG_INSTANCE_ID_MSB 3
984 +#define VIDEO_OUT_CFG_INSTANCE_ID_LSB 0
985 +#define VIDEO_OUT_CFG_INSTANCE_ID_ACCESS "RO"
986 +// =============================================================================
987 +// Register : VIDEO_OUT_CFG_RSTSEQ_AUTO
988 +// JTAG access : synchronous
989 +// Description : None
990 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_OFFSET 0x0000002c
991 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BITS 0x00000007
992 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_RESET 0x00000007
993 +// -----------------------------------------------------------------------------
994 +// Field : VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC
995 +// Description : 1 = reset is controlled by the sequencer
996 +// 0 = reset is controlled by rstseq_ctrl
997 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_RESET 0x1
998 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_BITS 0x00000004
999 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_MSB 2
1000 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_LSB 2
1001 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_ACCESS "RW"
1002 +// -----------------------------------------------------------------------------
1003 +// Field : VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI
1004 +// Description : 1 = reset is controlled by the sequencer
1005 +// 0 = reset is controlled by rstseq_ctrl
1006 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_RESET 0x1
1007 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_BITS 0x00000002
1008 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_MSB 1
1009 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_LSB 1
1010 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_ACCESS "RW"
1011 +// -----------------------------------------------------------------------------
1012 +// Field : VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER
1013 +// Description : 1 = reset is controlled by the sequencer
1014 +// 0 = reset is controlled by rstseq_ctrl
1015 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_RESET 0x1
1016 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_BITS 0x00000001
1017 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_MSB 0
1018 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_LSB 0
1019 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_ACCESS "RW"
1020 +// =============================================================================
1021 +// Register : VIDEO_OUT_CFG_RSTSEQ_PARALLEL
1022 +// JTAG access : synchronous
1023 +// Description : None
1024 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_OFFSET 0x00000030
1025 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BITS 0x00000007
1026 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_RESET 0x00000006
1027 +// -----------------------------------------------------------------------------
1028 +// Field : VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC
1029 +// Description : Is this reset parallel (i.e. not part of the sequence)
1030 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_RESET 0x1
1031 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_BITS 0x00000004
1032 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_MSB 2
1033 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_LSB 2
1034 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_ACCESS "RO"
1035 +// -----------------------------------------------------------------------------
1036 +// Field : VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI
1037 +// Description : Is this reset parallel (i.e. not part of the sequence)
1038 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_RESET 0x1
1039 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_BITS 0x00000002
1040 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_MSB 1
1041 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_LSB 1
1042 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_ACCESS "RO"
1043 +// -----------------------------------------------------------------------------
1044 +// Field : VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER
1045 +// Description : Is this reset parallel (i.e. not part of the sequence)
1046 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_RESET 0x0
1047 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_BITS 0x00000001
1048 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_MSB 0
1049 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_LSB 0
1050 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_ACCESS "RO"
1051 +// =============================================================================
1052 +// Register : VIDEO_OUT_CFG_RSTSEQ_CTRL
1053 +// JTAG access : synchronous
1054 +// Description : None
1055 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_OFFSET 0x00000034
1056 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BITS 0x00000007
1057 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_RESET 0x00000000
1058 +// -----------------------------------------------------------------------------
1059 +// Field : VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC
1060 +// Description : 1 = keep the reset asserted
1061 +// 0 = keep the reset deasserted
1062 +// This is ignored if rstseq_auto=1
1063 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_RESET 0x0
1064 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_BITS 0x00000004
1065 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_MSB 2
1066 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_LSB 2
1067 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_ACCESS "RW"
1068 +// -----------------------------------------------------------------------------
1069 +// Field : VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI
1070 +// Description : 1 = keep the reset asserted
1071 +// 0 = keep the reset deasserted
1072 +// This is ignored if rstseq_auto=1
1073 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_RESET 0x0
1074 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_BITS 0x00000002
1075 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_MSB 1
1076 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_LSB 1
1077 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_ACCESS "RW"
1078 +// -----------------------------------------------------------------------------
1079 +// Field : VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER
1080 +// Description : 1 = keep the reset asserted
1081 +// 0 = keep the reset deasserted
1082 +// This is ignored if rstseq_auto=1
1083 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_RESET 0x0
1084 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_BITS 0x00000001
1085 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_MSB 0
1086 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_LSB 0
1087 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_ACCESS "RW"
1088 +// =============================================================================
1089 +// Register : VIDEO_OUT_CFG_RSTSEQ_TRIG
1090 +// JTAG access : synchronous
1091 +// Description : None
1092 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_OFFSET 0x00000038
1093 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BITS 0x00000007
1094 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_RESET 0x00000000
1095 +// -----------------------------------------------------------------------------
1096 +// Field : VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC
1097 +// Description : Pulses the reset output
1098 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_RESET 0x0
1099 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_BITS 0x00000004
1100 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_MSB 2
1101 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_LSB 2
1102 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_ACCESS "SC"
1103 +// -----------------------------------------------------------------------------
1104 +// Field : VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI
1105 +// Description : Pulses the reset output
1106 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_RESET 0x0
1107 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_BITS 0x00000002
1108 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_MSB 1
1109 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_LSB 1
1110 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_ACCESS "SC"
1111 +// -----------------------------------------------------------------------------
1112 +// Field : VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER
1113 +// Description : Pulses the reset output
1114 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_RESET 0x0
1115 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_BITS 0x00000001
1116 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_MSB 0
1117 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_LSB 0
1118 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_ACCESS "SC"
1119 +// =============================================================================
1120 +// Register : VIDEO_OUT_CFG_RSTSEQ_DONE
1121 +// JTAG access : synchronous
1122 +// Description : None
1123 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_OFFSET 0x0000003c
1124 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BITS 0x00000007
1125 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_RESET 0x00000000
1126 +// -----------------------------------------------------------------------------
1127 +// Field : VIDEO_OUT_CFG_RSTSEQ_DONE_VEC
1128 +// Description : Indicates the current state of the reset
1129 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_RESET 0x0
1130 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_BITS 0x00000004
1131 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_MSB 2
1132 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_LSB 2
1133 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_ACCESS "RO"
1134 +// -----------------------------------------------------------------------------
1135 +// Field : VIDEO_OUT_CFG_RSTSEQ_DONE_DPI
1136 +// Description : Indicates the current state of the reset
1137 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_RESET 0x0
1138 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_BITS 0x00000002
1139 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_MSB 1
1140 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_LSB 1
1141 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_ACCESS "RO"
1142 +// -----------------------------------------------------------------------------
1143 +// Field : VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER
1144 +// Description : Indicates the current state of the reset
1145 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_RESET 0x0
1146 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_BITS 0x00000001
1147 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_MSB 0
1148 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_LSB 0
1149 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_ACCESS "RO"
1150 +// =============================================================================
1151 +
1152 +#define CFG_WRITE(reg, val) writel((val), vec->hw_base[RP1VEC_HW_BLOCK_CFG] + (reg ## _OFFSET))
1153 +#define CFG_READ(reg) readl(vec->hw_base[RP1VEC_HW_BLOCK_CFG] + (reg ## _OFFSET))
1154 +
1155 +void rp1vec_vidout_setup(struct rp1_vec *vec)
1156 +{
1157 + /*
1158 + * We assume DPI and VEC can't be used at the same time (due to
1159 + * clashing requirements for PLL_VIDEO, and potentially for VDAC).
1160 + * We therefore leave DPI memories powered down.
1161 + */
1162 + CFG_WRITE(VIDEO_OUT_CFG_MEM_PD, VIDEO_OUT_CFG_MEM_PD_DPI_BITS);
1163 + CFG_WRITE(VIDEO_OUT_CFG_TEST_OVERRIDE, 0x00000000);
1164 +
1165 + /* DPI->Pads; VEC->VDAC */
1166 + CFG_WRITE(VIDEO_OUT_CFG_SEL, VIDEO_OUT_CFG_SEL_VDAC_MUX_BITS);
1167 +
1168 + /* configure VDAC for 1 channel, bandgap on, 1.28V swing */
1169 + CFG_WRITE(VIDEO_OUT_CFG_VDAC_CFG, 0x0019ffff);
1170 +
1171 + /* enable VEC interrupt */
1172 + CFG_WRITE(VIDEO_OUT_CFG_INTE, VIDEO_OUT_CFG_INTE_VEC_BITS);
1173 +}
1174 +
1175 +void rp1vec_vidout_poweroff(struct rp1_vec *vec)
1176 +{
1177 + /* disable VEC interrupt */
1178 + CFG_WRITE(VIDEO_OUT_CFG_INTE, 0);
1179 +
1180 + /* Ensure VDAC is turned off; power down DPI,VEC memories */
1181 + CFG_WRITE(VIDEO_OUT_CFG_VDAC_CFG, 0);
1182 + CFG_WRITE(VIDEO_OUT_CFG_MEM_PD, VIDEO_OUT_CFG_MEM_PD_BITS);
1183 +}
1184 --- /dev/null
1185 +++ b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c
1186 @@ -0,0 +1,469 @@
1187 +// SPDX-License-Identifier: GPL-2.0-or-later
1188 +/*
1189 + * DRM Driver for VEC output on Raspberry Pi RP1
1190 + *
1191 + * Copyright (c) 2023 Raspberry Pi Limited.
1192 + */
1193 +
1194 +#include <linux/kernel.h>
1195 +#include <linux/errno.h>
1196 +#include <linux/mm.h>
1197 +#include <linux/delay.h>
1198 +#include <linux/interrupt.h>
1199 +#include <linux/platform_device.h>
1200 +#include <linux/printk.h>
1201 +#include <drm/drm_fourcc.h>
1202 +#include <drm/drm_print.h>
1203 +#include <drm/drm_vblank.h>
1204 +
1205 +#include "rp1_vec.h"
1206 +#include "vec_regs.h"
1207 +
1208 +#define BITS(field, val) (((val) << (field ## _LSB)) & (field ## _BITS))
1209 +
1210 +#define VEC_WRITE(reg, val) writel((val), vec->hw_base[RP1VEC_HW_BLOCK_VEC] + (reg ## _OFFSET))
1211 +#define VEC_READ(reg) readl(vec->hw_base[RP1VEC_HW_BLOCK_VEC] + (reg ## _OFFSET))
1212 +
1213 +int rp1vec_hw_busy(struct rp1_vec *vec)
1214 +{
1215 + /* Read the undocumented "pline_busy" flag */
1216 + return VEC_READ(VEC_STATUS) & 1;
1217 +}
1218 +
1219 +/* Table of supported input (in-memory/DMA) pixel formats. */
1220 +struct rp1vec_ipixfmt {
1221 + u32 format; /* DRM format code */
1222 + u32 mask; /* RGB masks (10 bits each, left justified) */
1223 + u32 shift; /* RGB MSB positions in the memory word */
1224 + u32 rgbsz; /* Shifts used for scaling; also (BPP/8-1) */
1225 +};
1226 +
1227 +#define MASK_RGB(r, g, b) \
1228 + (BITS(VEC_IMASK_MASK_R, r) | BITS(VEC_IMASK_MASK_G, g) | BITS(VEC_IMASK_MASK_B, b))
1229 +#define SHIFT_RGB(r, g, b) \
1230 + (BITS(VEC_SHIFT_SHIFT_R, r) | BITS(VEC_SHIFT_SHIFT_G, g) | BITS(VEC_SHIFT_SHIFT_B, b))
1231 +
1232 +static const struct rp1vec_ipixfmt my_formats[] = {
1233 + {
1234 + .format = DRM_FORMAT_XRGB8888,
1235 + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc),
1236 + .shift = SHIFT_RGB(23, 15, 7),
1237 + .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 3),
1238 + },
1239 + {
1240 + .format = DRM_FORMAT_XBGR8888,
1241 + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc),
1242 + .shift = SHIFT_RGB(7, 15, 23),
1243 + .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 3),
1244 + },
1245 + {
1246 + .format = DRM_FORMAT_RGB888,
1247 + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc),
1248 + .shift = SHIFT_RGB(23, 15, 7),
1249 + .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 2),
1250 + },
1251 + {
1252 + .format = DRM_FORMAT_BGR888,
1253 + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc),
1254 + .shift = SHIFT_RGB(7, 15, 23),
1255 + .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 2),
1256 + },
1257 + {
1258 + .format = DRM_FORMAT_RGB565,
1259 + .mask = MASK_RGB(0x3e0, 0x3f0, 0x3e0),
1260 + .shift = SHIFT_RGB(15, 10, 4),
1261 + .rgbsz = BITS(VEC_RGBSZ_SCALE_R, 5) |
1262 + BITS(VEC_RGBSZ_SCALE_G, 6) |
1263 + BITS(VEC_RGBSZ_SCALE_B, 5) |
1264 + BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 1),
1265 + }
1266 +};
1267 +
1268 +/*
1269 + * Hardware mode descriptions (@ 108 MHz clock rate).
1270 + * These rely largely on "canned" register settings.
1271 + * TODO: Port the generating software from FP to integer,
1272 + * or better factorize the differences between modes.
1273 + */
1274 +
1275 +struct rp1vec_hwmode {
1276 + u16 total_cols; /* active columns, plus padding for filter context */
1277 + u16 rows_per_field; /* active lines per field (including partial ones) */
1278 + bool interlaced; /* set for interlaced */
1279 + bool first_field_odd; /* set for interlaced and 30fps */
1280 + u32 yuv_scaling; /* three 10-bit fields {Y, U, V} in 2.8 format */
1281 + u32 back_end_regs[28]; /* All registers 0x80 .. 0xEC */
1282 +};
1283 +
1284 +/* { NTSC, PAL, PAL-M } x { progressive, interlaced } x { 13.5 MHz, 15.428571 MHz } */
1285 +static const struct rp1vec_hwmode rp1vec_hwmodes[3][2][2] = {
1286 + {
1287 + /* NTSC */
1288 + {
1289 + {
1290 + .total_cols = 724,
1291 + .rows_per_field = 240,
1292 + .interlaced = false,
1293 + .first_field_odd = false,
1294 + .yuv_scaling = 0x1071d0cf,
1295 + .back_end_regs = {
1296 + 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023d034c,
1297 + 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011,
1298 + 0x000a0106, 0x00000000, 0x00000000, 0x00000000,
1299 + 0x00000000, 0x00170106, 0x00000000, 0x004c020e,
1300 + 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561,
1301 + 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000,
1302 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ec,
1303 + },
1304 + }, {
1305 + .total_cols = 815,
1306 + .rows_per_field = 240,
1307 + .interlaced = false,
1308 + .first_field_odd = false,
1309 + .yuv_scaling = 0x1c131962,
1310 + .back_end_regs = {
1311 + 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023d034c,
1312 + 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011,
1313 + 0x000a0106, 0x00000000, 0x00000000, 0x00000000,
1314 + 0x00000000, 0x00170106, 0x00000000, 0x004c020e,
1315 + 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561,
1316 + 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000,
1317 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ac,
1318 + },
1319 + },
1320 + }, {
1321 + {
1322 + .total_cols = 724,
1323 + .rows_per_field = 243,
1324 + .interlaced = true,
1325 + .first_field_odd = true,
1326 + .yuv_scaling = 0x1071d0cf,
1327 + .back_end_regs = {
1328 + 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023d034c,
1329 + 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011,
1330 + 0x000a0107, 0x0111020d, 0x00000000, 0x00000000,
1331 + 0x011c020d, 0x00150106, 0x0107011b, 0x004c020d,
1332 + 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561,
1333 + 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000,
1334 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x00094dee,
1335 + },
1336 + }, {
1337 + .total_cols = 815,
1338 + .rows_per_field = 243,
1339 + .interlaced = true,
1340 + .first_field_odd = true,
1341 + .yuv_scaling = 0x1c131962,
1342 + .back_end_regs = {
1343 + 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023d034c,
1344 + 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011,
1345 + 0x000a0107, 0x0111020d, 0x00000000, 0x00000000,
1346 + 0x011c020d, 0x00150106, 0x0107011b, 0x004c020d,
1347 + 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561,
1348 + 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000,
1349 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x00094dae,
1350 + },
1351 + },
1352 + },
1353 + }, {
1354 + /* PAL */
1355 + {
1356 + {
1357 + .total_cols = 724,
1358 + .rows_per_field = 288,
1359 + .interlaced = false,
1360 + .first_field_odd = false,
1361 + .yuv_scaling = 0x11c1f8e0,
1362 + .back_end_regs = {
1363 + 0x04061aa6, 0x046e0cee, 0x0d8001fb, 0x025c034f,
1364 + 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009,
1365 + 0x00070135, 0x00000000, 0x00000000, 0x00000000,
1366 + 0x00000000, 0x00170136, 0x00000000, 0x000a0270,
1367 + 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5,
1368 + 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000,
1369 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ed,
1370 + },
1371 + }, {
1372 + .total_cols = 804,
1373 + .rows_per_field = 288,
1374 + .interlaced = false,
1375 + .first_field_odd = false,
1376 + .yuv_scaling = 0x1e635d7f,
1377 + .back_end_regs = {
1378 + 0x045b1a57, 0x046e0cee, 0x0d8001fb, 0x025c034f,
1379 + 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009,
1380 + 0x00070135, 0x00000000, 0x00000000, 0x00000000,
1381 + 0x00000000, 0x00170136, 0x00000000, 0x000a0270,
1382 + 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5,
1383 + 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000,
1384 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ad,
1385 + },
1386 + },
1387 + }, {
1388 + {
1389 + .total_cols = 724,
1390 + .rows_per_field = 288,
1391 + .interlaced = true,
1392 + .first_field_odd = false,
1393 + .yuv_scaling = 0x11c1f8e0,
1394 + .back_end_regs = {
1395 + 0x04061aa6, 0x046e0cee, 0x0d8001fb, 0x025c034f,
1396 + 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009,
1397 + 0x00070135, 0x013f026d, 0x00060136, 0x0140026e,
1398 + 0x0150026e, 0x00180136, 0x026f0017, 0x000a0271,
1399 + 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5,
1400 + 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000,
1401 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddef,
1402 + },
1403 + }, {
1404 + .total_cols = 804,
1405 + .rows_per_field = 288,
1406 + .interlaced = true,
1407 + .first_field_odd = false,
1408 + .yuv_scaling = 0x1e635d7f,
1409 + .back_end_regs = {
1410 + 0x045b1a57, 0x046e0cee, 0x0d8001fb, 0x025c034f,
1411 + 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009,
1412 + 0x00070135, 0x013f026d, 0x00060136, 0x0140026e,
1413 + 0x0150026e, 0x00180136, 0x026f0017, 0x000a0271,
1414 + 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5,
1415 + 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000,
1416 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddaf,
1417 + },
1418 + },
1419 + },
1420 + }, {
1421 + /* PAL-M */
1422 + {
1423 + {
1424 + .total_cols = 724,
1425 + .rows_per_field = 240,
1426 + .interlaced = false,
1427 + .first_field_odd = false,
1428 + .yuv_scaling = 0x11c1f8e0,
1429 + .back_end_regs = {
1430 + 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023c034c,
1431 + 0x00f80b6e, 0x00000005, 0x0006000b, 0x000c0011,
1432 + 0x000a0106, 0x00000000, 0x00000000, 0x00000000,
1433 + 0x00000000, 0x00170106, 0x00000000, 0x000a020c,
1434 + 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5,
1435 + 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000,
1436 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ed,
1437 + },
1438 + }, {
1439 + .total_cols = 815,
1440 + .rows_per_field = 240,
1441 + .interlaced = false,
1442 + .first_field_odd = false,
1443 + .yuv_scaling = 0x1e635d7f,
1444 + .back_end_regs = {
1445 + 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023c034c,
1446 + 0x00f80b6e, 0x00000005, 0x0006000b, 0x000c0011,
1447 + 0x000a0106, 0x00000000, 0x00000000, 0x00000000,
1448 + 0x00000000, 0x00170106, 0x00000000, 0x000a020c,
1449 + 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5,
1450 + 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000,
1451 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ad,
1452 + },
1453 + },
1454 + }, {
1455 + {
1456 + .total_cols = 724,
1457 + .rows_per_field = 243,
1458 + .interlaced = true,
1459 + .first_field_odd = true,
1460 + .yuv_scaling = 0x11c1f8e0,
1461 + .back_end_regs = {
1462 + 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023c034c,
1463 + 0x00f80b6e, 0x00140019, 0x00000005, 0x0006000b,
1464 + 0x00090103, 0x010f0209, 0x00080102, 0x010e020a,
1465 + 0x0119020a, 0x00120103, 0x01040118, 0x000a020d,
1466 + 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5,
1467 + 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000,
1468 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddef,
1469 + },
1470 + }, {
1471 + .total_cols = 815,
1472 + .rows_per_field = 243,
1473 + .interlaced = true,
1474 + .first_field_odd = true,
1475 + .yuv_scaling = 0x1e635d7f,
1476 + .back_end_regs = {
1477 + 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023c034c,
1478 + 0x00f80b6e, 0x00140019, 0x00000005, 0x0006000b,
1479 + 0x00090103, 0x010f0209, 0x00080102, 0x010e020a,
1480 + 0x0119020a, 0x00120103, 0x01040118, 0x000a020d,
1481 + 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5,
1482 + 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000,
1483 + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddaf,
1484 + },
1485 + },
1486 + },
1487 + },
1488 +};
1489 +
1490 +void rp1vec_hw_setup(struct rp1_vec *vec,
1491 + u32 in_format,
1492 + struct drm_display_mode const *mode,
1493 + int tvstd)
1494 +{
1495 + unsigned int i, mode_family, mode_ilaced, mode_narrow;
1496 + const struct rp1vec_hwmode *hwm;
1497 + unsigned int w, h;
1498 +
1499 + /* Pick the appropriate "base" mode, which we may modify */
1500 + mode_ilaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1501 + if (mode->vtotal > 263 * (1 + mode_ilaced))
1502 + mode_family = 1;
1503 + else
1504 + mode_family = (tvstd == RP1VEC_TVSTD_PAL_M || tvstd == RP1VEC_TVSTD_PAL60) ? 2 : 0;
1505 + mode_narrow = (mode->clock >= 14336);
1506 + hwm = &rp1vec_hwmodes[mode_family][mode_ilaced][mode_narrow];
1507 + dev_info(&vec->pdev->dev,
1508 + "%s: in_fmt=\'%c%c%c%c\' mode=%dx%d%s [%d%d%d] tvstd=%d (%s)",
1509 + __func__, in_format, in_format >> 8, in_format >> 16, in_format >> 24,
1510 + mode->hdisplay, mode->vdisplay, (mode_ilaced) ? "i" : "",
1511 + mode_family, mode_ilaced, mode_narrow,
1512 + tvstd, rp1vec_tvstd_names[tvstd]);
1513 +
1514 + w = mode->hdisplay;
1515 + h = mode->vdisplay;
1516 + if (mode_ilaced)
1517 + h >>= 1;
1518 + if (w > hwm->total_cols)
1519 + w = hwm->total_cols;
1520 + if (h > hwm->rows_per_field)
1521 + w = hwm->rows_per_field;
1522 +
1523 + /* Configure the hardware */
1524 + VEC_WRITE(VEC_APB_TIMEOUT, 0x38);
1525 + VEC_WRITE(VEC_QOS,
1526 + BITS(VEC_QOS_DQOS, 0x0) |
1527 + BITS(VEC_QOS_ULEV, 0x8) |
1528 + BITS(VEC_QOS_UQOS, 0x2) |
1529 + BITS(VEC_QOS_LLEV, 0x4) |
1530 + BITS(VEC_QOS_LQOS, 0x7));
1531 + VEC_WRITE(VEC_DMA_AREA,
1532 + BITS(VEC_DMA_AREA_COLS_MINUS1, w - 1) |
1533 + BITS(VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1, h - 1));
1534 + VEC_WRITE(VEC_YUV_SCALING, hwm->yuv_scaling);
1535 + VEC_WRITE(VEC_BACK_PORCH,
1536 + BITS(VEC_BACK_PORCH_HBP_MINUS1, (hwm->total_cols - w - 1) >> 1) |
1537 + BITS(VEC_BACK_PORCH_VBP_MINUS1, (hwm->rows_per_field - h - 1) >> 1));
1538 + VEC_WRITE(VEC_FRONT_PORCH,
1539 + BITS(VEC_FRONT_PORCH_HFP_MINUS1, (hwm->total_cols - w - 2) >> 1) |
1540 + BITS(VEC_FRONT_PORCH_VFP_MINUS1, (hwm->rows_per_field - h - 2) >> 1));
1541 + VEC_WRITE(VEC_MODE,
1542 + BITS(VEC_MODE_HIGH_WATER, 0xE0) |
1543 + BITS(VEC_MODE_ALIGN16, !((w | mode->hdisplay) & 15)) |
1544 + BITS(VEC_MODE_VFP_EN, (hwm->rows_per_field > h + 1)) |
1545 + BITS(VEC_MODE_VBP_EN, (hwm->rows_per_field > h)) |
1546 + BITS(VEC_MODE_HFP_EN, (hwm->total_cols > w + 1)) |
1547 + BITS(VEC_MODE_HBP_EN, (hwm->total_cols > w)) |
1548 + BITS(VEC_MODE_FIELDS_PER_FRAME_MINUS1, hwm->interlaced) |
1549 + BITS(VEC_MODE_FIRST_FIELD_ODD, hwm->first_field_odd));
1550 + for (i = 0; i < ARRAY_SIZE(hwm->back_end_regs); ++i) {
1551 + writel(hwm->back_end_regs[i],
1552 + vec->hw_base[RP1VEC_HW_BLOCK_VEC] + 0x80 + 4 * i);
1553 + }
1554 +
1555 + /* Apply modifications */
1556 + if (tvstd == RP1VEC_TVSTD_NTSC_J && mode_family == 0) {
1557 + /* Reduce pedestal (not quite to zero, for FIR overshoot); increase gain */
1558 + VEC_WRITE(VEC_DAC_BC,
1559 + BITS(VEC_DAC_BC_S11_PEDESTAL, 10) |
1560 + (hwm->back_end_regs[(0xBC - 0x80) / 4] & ~VEC_DAC_BC_S11_PEDESTAL_BITS));
1561 + VEC_WRITE(VEC_DAC_C8,
1562 + BITS(VEC_DAC_C8_U16_SCALE_LUMA, 0x9400) |
1563 + (hwm->back_end_regs[(0xC8 - 0x80) / 4] &
1564 + ~VEC_DAC_C8_U16_SCALE_LUMA_BITS));
1565 + } else if ((tvstd == RP1VEC_TVSTD_NTSC_443 || tvstd == RP1VEC_TVSTD_PAL60) &&
1566 + mode_family != 1) {
1567 + /* Change colour carrier frequency to 4433618.75 Hz; disable hard sync */
1568 + VEC_WRITE(VEC_DAC_D4, 0xcc48c1d1);
1569 + VEC_WRITE(VEC_DAC_D8, 0x0a8262b2);
1570 + VEC_WRITE(VEC_DAC_EC,
1571 + hwm->back_end_regs[(0xEC - 0x80) / 4] & ~VEC_DAC_EC_SEQ_EN_BITS);
1572 + } else if (tvstd == RP1VEC_TVSTD_PAL_N && mode_family == 1) {
1573 + /* Change colour carrier frequency to 3582056.25 Hz */
1574 + VEC_WRITE(VEC_DAC_D4, 0x9ce075f7);
1575 + VEC_WRITE(VEC_DAC_D8, 0x087da511);
1576 + }
1577 +
1578 + /* Input pixel format conversion */
1579 + for (i = 0; i < ARRAY_SIZE(my_formats); ++i) {
1580 + if (my_formats[i].format == in_format)
1581 + break;
1582 + }
1583 + if (i >= ARRAY_SIZE(my_formats)) {
1584 + dev_err(&vec->pdev->dev, "%s: bad input format\n", __func__);
1585 + i = 0;
1586 + }
1587 + VEC_WRITE(VEC_IMASK, my_formats[i].mask);
1588 + VEC_WRITE(VEC_SHIFT, my_formats[i].shift);
1589 + VEC_WRITE(VEC_RGBSZ, my_formats[i].rgbsz);
1590 +
1591 + VEC_WRITE(VEC_IRQ_FLAGS, 0xffffffff);
1592 + rp1vec_hw_vblank_ctrl(vec, 1);
1593 +
1594 + i = rp1vec_hw_busy(vec);
1595 + if (i)
1596 + dev_warn(&vec->pdev->dev,
1597 + "%s: VEC unexpectedly busy at start (0x%08x)",
1598 + __func__, VEC_READ(VEC_STATUS));
1599 +
1600 + VEC_WRITE(VEC_CONTROL,
1601 + BITS(VEC_CONTROL_START_ARM, (!i)) |
1602 + BITS(VEC_CONTROL_AUTO_REPEAT, 1));
1603 +}
1604 +
1605 +void rp1vec_hw_update(struct rp1_vec *vec, dma_addr_t addr, u32 offset, u32 stride)
1606 +{
1607 + /*
1608 + * Update STRIDE, DMAH and DMAL only. When called after rp1vec_hw_setup(),
1609 + * DMA starts immediately; if already running, the buffer will flip at
1610 + * the next vertical sync event.
1611 + */
1612 + u64 a = addr + offset;
1613 +
1614 + VEC_WRITE(VEC_DMA_STRIDE, stride);
1615 + VEC_WRITE(VEC_DMA_ADDR_H, a >> 32);
1616 + VEC_WRITE(VEC_DMA_ADDR_L, a & 0xFFFFFFFFu);
1617 +}
1618 +
1619 +void rp1vec_hw_stop(struct rp1_vec *vec)
1620 +{
1621 + /*
1622 + * Stop DMA by turning off the Auto-Repeat flag, and wait up to 100ms for
1623 + * the current and any queued frame to end. "Force drain" flags are not used,
1624 + * as they seem to prevent DMA from re-starting properly; it's safer to wait.
1625 + */
1626 +
1627 + reinit_completion(&vec->finished);
1628 + VEC_WRITE(VEC_CONTROL, 0);
1629 + if (!wait_for_completion_timeout(&vec->finished, HZ / 10))
1630 + drm_err(vec->drm, "%s: timed out waiting for idle\n", __func__);
1631 + VEC_WRITE(VEC_IRQ_ENABLES, 0);
1632 +}
1633 +
1634 +void rp1vec_hw_vblank_ctrl(struct rp1_vec *vec, int enable)
1635 +{
1636 + VEC_WRITE(VEC_IRQ_ENABLES,
1637 + BITS(VEC_IRQ_ENABLES_DONE, 1) |
1638 + BITS(VEC_IRQ_ENABLES_DMA, (enable ? 1 : 0)) |
1639 + BITS(VEC_IRQ_ENABLES_MATCH_ROW, 1023));
1640 +}
1641 +
1642 +irqreturn_t rp1vec_hw_isr(int irq, void *dev)
1643 +{
1644 + struct rp1_vec *vec = dev;
1645 + u32 u = VEC_READ(VEC_IRQ_FLAGS);
1646 +
1647 + if (u) {
1648 + VEC_WRITE(VEC_IRQ_FLAGS, u);
1649 + if (u & VEC_IRQ_FLAGS_DMA_BITS)
1650 + drm_crtc_handle_vblank(&vec->pipe.crtc);
1651 + if (u & VEC_IRQ_FLAGS_DONE_BITS)
1652 + complete(&vec->finished);
1653 + }
1654 + return u ? IRQ_HANDLED : IRQ_NONE;
1655 +}
1656 --- /dev/null
1657 +++ b/drivers/gpu/drm/rp1/rp1-vec/vec_regs.h
1658 @@ -0,0 +1,1420 @@
1659 +/* SPDX-License-Identifier: GPL-2.0-or-later */
1660 +// =============================================================================
1661 +// Copyright Raspberry Pi Ltd. 2023
1662 +// vrbuild version: 56aac1a23c016cbbd229108f3b6efc1343842156-clean
1663 +// THIS FILE IS GENERATED BY VRBUILD - DO NOT EDIT
1664 +// =============================================================================
1665 +// Register block : VEC
1666 +// Version : 1
1667 +// Bus type : apb
1668 +// Description : None
1669 +// =============================================================================
1670 +#ifndef VEC_REGS_DEFINED
1671 +#define VEC_REGS_DEFINED
1672 +#define VEC_REGS_RWTYPE_MSB 13
1673 +#define VEC_REGS_RWTYPE_LSB 12
1674 +// =============================================================================
1675 +// Register : VEC_CONTROL
1676 +// JTAG access : synchronous
1677 +// Description : None
1678 +#define VEC_CONTROL_OFFSET 0x00000000
1679 +#define VEC_CONTROL_BITS 0x00000007
1680 +#define VEC_CONTROL_RESET 0x00000000
1681 +// -----------------------------------------------------------------------------
1682 +// Field : VEC_CONTROL_BARS
1683 +// Description : Write '1' to display colour bar test pattern
1684 +#define VEC_CONTROL_BARS_RESET 0x0
1685 +#define VEC_CONTROL_BARS_BITS 0x00000004
1686 +#define VEC_CONTROL_BARS_MSB 2
1687 +#define VEC_CONTROL_BARS_LSB 2
1688 +#define VEC_CONTROL_BARS_ACCESS "RW"
1689 +// -----------------------------------------------------------------------------
1690 +// Field : VEC_CONTROL_AUTO_REPEAT
1691 +// Description : Write '1' to re-display same frame continuously
1692 +#define VEC_CONTROL_AUTO_REPEAT_RESET 0x0
1693 +#define VEC_CONTROL_AUTO_REPEAT_BITS 0x00000002
1694 +#define VEC_CONTROL_AUTO_REPEAT_MSB 1
1695 +#define VEC_CONTROL_AUTO_REPEAT_LSB 1
1696 +#define VEC_CONTROL_AUTO_REPEAT_ACCESS "RW"
1697 +// -----------------------------------------------------------------------------
1698 +// Field : VEC_CONTROL_START_ARM
1699 +// Description : Write '1' before first DMA address is written This bit always
1700 +// reads back as '0'
1701 +#define VEC_CONTROL_START_ARM_RESET 0x0
1702 +#define VEC_CONTROL_START_ARM_BITS 0x00000001
1703 +#define VEC_CONTROL_START_ARM_MSB 0
1704 +#define VEC_CONTROL_START_ARM_LSB 0
1705 +#define VEC_CONTROL_START_ARM_ACCESS "SC"
1706 +// =============================================================================
1707 +// Register : VEC_IRQ_ENABLES
1708 +// JTAG access : synchronous
1709 +// Description : None
1710 +#define VEC_IRQ_ENABLES_OFFSET 0x00000004
1711 +#define VEC_IRQ_ENABLES_BITS 0x03ff003f
1712 +#define VEC_IRQ_ENABLES_RESET 0x00000000
1713 +// -----------------------------------------------------------------------------
1714 +// Field : VEC_IRQ_ENABLES_MATCH_ROW
1715 +// Description : Raster line at which MATCH interrupt is signalled
1716 +#define VEC_IRQ_ENABLES_MATCH_ROW_RESET 0x000
1717 +#define VEC_IRQ_ENABLES_MATCH_ROW_BITS 0x03ff0000
1718 +#define VEC_IRQ_ENABLES_MATCH_ROW_MSB 25
1719 +#define VEC_IRQ_ENABLES_MATCH_ROW_LSB 16
1720 +#define VEC_IRQ_ENABLES_MATCH_ROW_ACCESS "RW"
1721 +// -----------------------------------------------------------------------------
1722 +// Field : VEC_IRQ_ENABLES_MATCH
1723 +// Description : Output raster == match_row reached
1724 +#define VEC_IRQ_ENABLES_MATCH_RESET 0x0
1725 +#define VEC_IRQ_ENABLES_MATCH_BITS 0x00000020
1726 +#define VEC_IRQ_ENABLES_MATCH_MSB 5
1727 +#define VEC_IRQ_ENABLES_MATCH_LSB 5
1728 +#define VEC_IRQ_ENABLES_MATCH_ACCESS "RW"
1729 +// -----------------------------------------------------------------------------
1730 +// Field : VEC_IRQ_ENABLES_ERROR
1731 +// Description : DMA address overwritten before it was taken
1732 +#define VEC_IRQ_ENABLES_ERROR_RESET 0x0
1733 +#define VEC_IRQ_ENABLES_ERROR_BITS 0x00000010
1734 +#define VEC_IRQ_ENABLES_ERROR_MSB 4
1735 +#define VEC_IRQ_ENABLES_ERROR_LSB 4
1736 +#define VEC_IRQ_ENABLES_ERROR_ACCESS "RW"
1737 +// -----------------------------------------------------------------------------
1738 +// Field : VEC_IRQ_ENABLES_DONE
1739 +// Description : Last word sent to DAC after end of video (= all clear)
1740 +#define VEC_IRQ_ENABLES_DONE_RESET 0x0
1741 +#define VEC_IRQ_ENABLES_DONE_BITS 0x00000008
1742 +#define VEC_IRQ_ENABLES_DONE_MSB 3
1743 +#define VEC_IRQ_ENABLES_DONE_LSB 3
1744 +#define VEC_IRQ_ENABLES_DONE_ACCESS "RW"
1745 +// -----------------------------------------------------------------------------
1746 +// Field : VEC_IRQ_ENABLES_FRAME
1747 +// Description : Start of frame
1748 +#define VEC_IRQ_ENABLES_FRAME_RESET 0x0
1749 +#define VEC_IRQ_ENABLES_FRAME_BITS 0x00000004
1750 +#define VEC_IRQ_ENABLES_FRAME_MSB 2
1751 +#define VEC_IRQ_ENABLES_FRAME_LSB 2
1752 +#define VEC_IRQ_ENABLES_FRAME_ACCESS "RW"
1753 +// -----------------------------------------------------------------------------
1754 +// Field : VEC_IRQ_ENABLES_UNDERFLOW
1755 +// Description : Underflow has occurred
1756 +#define VEC_IRQ_ENABLES_UNDERFLOW_RESET 0x0
1757 +#define VEC_IRQ_ENABLES_UNDERFLOW_BITS 0x00000002
1758 +#define VEC_IRQ_ENABLES_UNDERFLOW_MSB 1
1759 +#define VEC_IRQ_ENABLES_UNDERFLOW_LSB 1
1760 +#define VEC_IRQ_ENABLES_UNDERFLOW_ACCESS "RW"
1761 +// -----------------------------------------------------------------------------
1762 +// Field : VEC_IRQ_ENABLES_DMA
1763 +// Description : DMA ready to accept next frame start address
1764 +#define VEC_IRQ_ENABLES_DMA_RESET 0x0
1765 +#define VEC_IRQ_ENABLES_DMA_BITS 0x00000001
1766 +#define VEC_IRQ_ENABLES_DMA_MSB 0
1767 +#define VEC_IRQ_ENABLES_DMA_LSB 0
1768 +#define VEC_IRQ_ENABLES_DMA_ACCESS "RW"
1769 +// =============================================================================
1770 +// Register : VEC_IRQ_FLAGS
1771 +// JTAG access : synchronous
1772 +// Description : None
1773 +#define VEC_IRQ_FLAGS_OFFSET 0x00000008
1774 +#define VEC_IRQ_FLAGS_BITS 0x0000003f
1775 +#define VEC_IRQ_FLAGS_RESET 0x00000000
1776 +// -----------------------------------------------------------------------------
1777 +// Field : VEC_IRQ_FLAGS_MATCH
1778 +// Description : Output raster == match_row reached
1779 +#define VEC_IRQ_FLAGS_MATCH_RESET 0x0
1780 +#define VEC_IRQ_FLAGS_MATCH_BITS 0x00000020
1781 +#define VEC_IRQ_FLAGS_MATCH_MSB 5
1782 +#define VEC_IRQ_FLAGS_MATCH_LSB 5
1783 +#define VEC_IRQ_FLAGS_MATCH_ACCESS "WC"
1784 +// -----------------------------------------------------------------------------
1785 +// Field : VEC_IRQ_FLAGS_ERROR
1786 +// Description : DMA address overwritten before it was taken
1787 +#define VEC_IRQ_FLAGS_ERROR_RESET 0x0
1788 +#define VEC_IRQ_FLAGS_ERROR_BITS 0x00000010
1789 +#define VEC_IRQ_FLAGS_ERROR_MSB 4
1790 +#define VEC_IRQ_FLAGS_ERROR_LSB 4
1791 +#define VEC_IRQ_FLAGS_ERROR_ACCESS "WC"
1792 +// -----------------------------------------------------------------------------
1793 +// Field : VEC_IRQ_FLAGS_DONE
1794 +// Description : Last word sent to DAC after end of video (= all clear)
1795 +#define VEC_IRQ_FLAGS_DONE_RESET 0x0
1796 +#define VEC_IRQ_FLAGS_DONE_BITS 0x00000008
1797 +#define VEC_IRQ_FLAGS_DONE_MSB 3
1798 +#define VEC_IRQ_FLAGS_DONE_LSB 3
1799 +#define VEC_IRQ_FLAGS_DONE_ACCESS "WC"
1800 +// -----------------------------------------------------------------------------
1801 +// Field : VEC_IRQ_FLAGS_FRAME
1802 +// Description : Start of frame
1803 +#define VEC_IRQ_FLAGS_FRAME_RESET 0x0
1804 +#define VEC_IRQ_FLAGS_FRAME_BITS 0x00000004
1805 +#define VEC_IRQ_FLAGS_FRAME_MSB 2
1806 +#define VEC_IRQ_FLAGS_FRAME_LSB 2
1807 +#define VEC_IRQ_FLAGS_FRAME_ACCESS "WC"
1808 +// -----------------------------------------------------------------------------
1809 +// Field : VEC_IRQ_FLAGS_UNDERFLOW
1810 +// Description : Underflow has occurred
1811 +#define VEC_IRQ_FLAGS_UNDERFLOW_RESET 0x0
1812 +#define VEC_IRQ_FLAGS_UNDERFLOW_BITS 0x00000002
1813 +#define VEC_IRQ_FLAGS_UNDERFLOW_MSB 1
1814 +#define VEC_IRQ_FLAGS_UNDERFLOW_LSB 1
1815 +#define VEC_IRQ_FLAGS_UNDERFLOW_ACCESS "WC"
1816 +// -----------------------------------------------------------------------------
1817 +// Field : VEC_IRQ_FLAGS_DMA
1818 +// Description : DMA ready to accept next frame start address
1819 +#define VEC_IRQ_FLAGS_DMA_RESET 0x0
1820 +#define VEC_IRQ_FLAGS_DMA_BITS 0x00000001
1821 +#define VEC_IRQ_FLAGS_DMA_MSB 0
1822 +#define VEC_IRQ_FLAGS_DMA_LSB 0
1823 +#define VEC_IRQ_FLAGS_DMA_ACCESS "WC"
1824 +// =============================================================================
1825 +// Register : VEC_QOS
1826 +// JTAG access : synchronous
1827 +// Description : This register configures panic levels for the AXI ar_qos
1828 +// quality of service field. Panic status is driven by the number
1829 +// of rows held in the SRAM cache:
1830 +#define VEC_QOS_OFFSET 0x0000000c
1831 +#define VEC_QOS_BITS 0x000fffff
1832 +#define VEC_QOS_RESET 0x00000000
1833 +// -----------------------------------------------------------------------------
1834 +// Field : VEC_QOS_UQOS
1835 +// Description : Upper AXI QOS
1836 +#define VEC_QOS_UQOS_RESET 0x0
1837 +#define VEC_QOS_UQOS_BITS 0x000f0000
1838 +#define VEC_QOS_UQOS_MSB 19
1839 +#define VEC_QOS_UQOS_LSB 16
1840 +#define VEC_QOS_UQOS_ACCESS "RW"
1841 +// -----------------------------------------------------------------------------
1842 +// Field : VEC_QOS_ULEV
1843 +// Description : Upper trip level (resolution = 1 / 16 of cache size)
1844 +#define VEC_QOS_ULEV_RESET 0x0
1845 +#define VEC_QOS_ULEV_BITS 0x0000f000
1846 +#define VEC_QOS_ULEV_MSB 15
1847 +#define VEC_QOS_ULEV_LSB 12
1848 +#define VEC_QOS_ULEV_ACCESS "RW"
1849 +// -----------------------------------------------------------------------------
1850 +// Field : VEC_QOS_LQOS
1851 +// Description : Lower AXI QOS
1852 +#define VEC_QOS_LQOS_RESET 0x0
1853 +#define VEC_QOS_LQOS_BITS 0x00000f00
1854 +#define VEC_QOS_LQOS_MSB 11
1855 +#define VEC_QOS_LQOS_LSB 8
1856 +#define VEC_QOS_LQOS_ACCESS "RW"
1857 +// -----------------------------------------------------------------------------
1858 +// Field : VEC_QOS_LLEV
1859 +// Description : Lower trip level (resolution = 1 / 16 of cache size)
1860 +#define VEC_QOS_LLEV_RESET 0x0
1861 +#define VEC_QOS_LLEV_BITS 0x000000f0
1862 +#define VEC_QOS_LLEV_MSB 7
1863 +#define VEC_QOS_LLEV_LSB 4
1864 +#define VEC_QOS_LLEV_ACCESS "RW"
1865 +// -----------------------------------------------------------------------------
1866 +// Field : VEC_QOS_DQOS
1867 +// Description : Default QOS
1868 +#define VEC_QOS_DQOS_RESET 0x0
1869 +#define VEC_QOS_DQOS_BITS 0x0000000f
1870 +#define VEC_QOS_DQOS_MSB 3
1871 +#define VEC_QOS_DQOS_LSB 0
1872 +#define VEC_QOS_DQOS_ACCESS "RW"
1873 +// =============================================================================
1874 +// Register : VEC_DMA_ADDR_L
1875 +// JTAG access : synchronous
1876 +// Description : Lower 32-bits
1877 +#define VEC_DMA_ADDR_L_OFFSET 0x00000010
1878 +#define VEC_DMA_ADDR_L_BITS 0xffffffff
1879 +#define VEC_DMA_ADDR_L_RESET 0x00000000
1880 +// -----------------------------------------------------------------------------
1881 +// Field : VEC_DMA_ADDR_L_AXI_ADDR
1882 +// Description : Byte address of DMA transfer frame buffer.
1883 +#define VEC_DMA_ADDR_L_AXI_ADDR_RESET 0x00000000
1884 +#define VEC_DMA_ADDR_L_AXI_ADDR_BITS 0xffffffff
1885 +#define VEC_DMA_ADDR_L_AXI_ADDR_MSB 31
1886 +#define VEC_DMA_ADDR_L_AXI_ADDR_LSB 0
1887 +#define VEC_DMA_ADDR_L_AXI_ADDR_ACCESS "RWF"
1888 +// =============================================================================
1889 +// Register : VEC_DMA_STRIDE
1890 +// JTAG access : synchronous
1891 +// Description : This register sets the line byte stride.
1892 +#define VEC_DMA_STRIDE_OFFSET 0x00000014
1893 +#define VEC_DMA_STRIDE_BITS 0xffffffff
1894 +#define VEC_DMA_STRIDE_RESET 0x00000000
1895 +// -----------------------------------------------------------------------------
1896 +// Field : VEC_DMA_STRIDE_STRIDE
1897 +// Description : Byte stride
1898 +#define VEC_DMA_STRIDE_STRIDE_RESET 0x00000000
1899 +#define VEC_DMA_STRIDE_STRIDE_BITS 0xffffffff
1900 +#define VEC_DMA_STRIDE_STRIDE_MSB 31
1901 +#define VEC_DMA_STRIDE_STRIDE_LSB 0
1902 +#define VEC_DMA_STRIDE_STRIDE_ACCESS "RW"
1903 +// =============================================================================
1904 +// Register : VEC_DMA_AREA
1905 +// JTAG access : synchronous
1906 +// Description : Interlaced pixel area. See example driver code.
1907 +#define VEC_DMA_AREA_OFFSET 0x00000018
1908 +#define VEC_DMA_AREA_BITS 0x03ff03ff
1909 +#define VEC_DMA_AREA_RESET 0x00000000
1910 +// -----------------------------------------------------------------------------
1911 +// Field : VEC_DMA_AREA_COLS_MINUS1
1912 +// Description : Width
1913 +#define VEC_DMA_AREA_COLS_MINUS1_RESET 0x000
1914 +#define VEC_DMA_AREA_COLS_MINUS1_BITS 0x03ff0000
1915 +#define VEC_DMA_AREA_COLS_MINUS1_MSB 25
1916 +#define VEC_DMA_AREA_COLS_MINUS1_LSB 16
1917 +#define VEC_DMA_AREA_COLS_MINUS1_ACCESS "RW"
1918 +// -----------------------------------------------------------------------------
1919 +// Field : VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1
1920 +// Description : Lines per field = half of lines per interlaced frame
1921 +#define VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1_RESET 0x000
1922 +#define VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1_BITS 0x000003ff
1923 +#define VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1_MSB 9
1924 +#define VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1_LSB 0
1925 +#define VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1_ACCESS "RW"
1926 +// =============================================================================
1927 +// Register : VEC_YUV_SCALING
1928 +// JTAG access : synchronous
1929 +// Description : None
1930 +#define VEC_YUV_SCALING_OFFSET 0x0000001c
1931 +#define VEC_YUV_SCALING_BITS 0x3fffffff
1932 +#define VEC_YUV_SCALING_RESET 0x00000000
1933 +// -----------------------------------------------------------------------------
1934 +// Field : VEC_YUV_SCALING_U10_SCALE_Y
1935 +// Description : Y unsigned scaling factor - 8 binary places
1936 +#define VEC_YUV_SCALING_U10_SCALE_Y_RESET 0x000
1937 +#define VEC_YUV_SCALING_U10_SCALE_Y_BITS 0x3ff00000
1938 +#define VEC_YUV_SCALING_U10_SCALE_Y_MSB 29
1939 +#define VEC_YUV_SCALING_U10_SCALE_Y_LSB 20
1940 +#define VEC_YUV_SCALING_U10_SCALE_Y_ACCESS "RW"
1941 +// -----------------------------------------------------------------------------
1942 +// Field : VEC_YUV_SCALING_S10_SCALE_U
1943 +// Description : U signed scaling factor - 8 binary places
1944 +#define VEC_YUV_SCALING_S10_SCALE_U_RESET 0x000
1945 +#define VEC_YUV_SCALING_S10_SCALE_U_BITS 0x000ffc00
1946 +#define VEC_YUV_SCALING_S10_SCALE_U_MSB 19
1947 +#define VEC_YUV_SCALING_S10_SCALE_U_LSB 10
1948 +#define VEC_YUV_SCALING_S10_SCALE_U_ACCESS "RW"
1949 +// -----------------------------------------------------------------------------
1950 +// Field : VEC_YUV_SCALING_S10_SCALE_V
1951 +// Description : V signed scaling factor - 8 binary please
1952 +#define VEC_YUV_SCALING_S10_SCALE_V_RESET 0x000
1953 +#define VEC_YUV_SCALING_S10_SCALE_V_BITS 0x000003ff
1954 +#define VEC_YUV_SCALING_S10_SCALE_V_MSB 9
1955 +#define VEC_YUV_SCALING_S10_SCALE_V_LSB 0
1956 +#define VEC_YUV_SCALING_S10_SCALE_V_ACCESS "RW"
1957 +// =============================================================================
1958 +// Register : VEC_BACK_PORCH
1959 +// JTAG access : synchronous
1960 +// Description : None
1961 +#define VEC_BACK_PORCH_OFFSET 0x00000020
1962 +#define VEC_BACK_PORCH_BITS 0x03ff03ff
1963 +#define VEC_BACK_PORCH_RESET 0x00000000
1964 +// -----------------------------------------------------------------------------
1965 +// Field : VEC_BACK_PORCH_HBP_MINUS1
1966 +// Description : Horizontal back porch
1967 +#define VEC_BACK_PORCH_HBP_MINUS1_RESET 0x000
1968 +#define VEC_BACK_PORCH_HBP_MINUS1_BITS 0x03ff0000
1969 +#define VEC_BACK_PORCH_HBP_MINUS1_MSB 25
1970 +#define VEC_BACK_PORCH_HBP_MINUS1_LSB 16
1971 +#define VEC_BACK_PORCH_HBP_MINUS1_ACCESS "RW"
1972 +// -----------------------------------------------------------------------------
1973 +// Field : VEC_BACK_PORCH_VBP_MINUS1
1974 +// Description : Vertical back porch
1975 +#define VEC_BACK_PORCH_VBP_MINUS1_RESET 0x000
1976 +#define VEC_BACK_PORCH_VBP_MINUS1_BITS 0x000003ff
1977 +#define VEC_BACK_PORCH_VBP_MINUS1_MSB 9
1978 +#define VEC_BACK_PORCH_VBP_MINUS1_LSB 0
1979 +#define VEC_BACK_PORCH_VBP_MINUS1_ACCESS "RW"
1980 +// =============================================================================
1981 +// Register : VEC_FRONT_PORCH
1982 +// JTAG access : synchronous
1983 +// Description : None
1984 +#define VEC_FRONT_PORCH_OFFSET 0x00000024
1985 +#define VEC_FRONT_PORCH_BITS 0x03ff03ff
1986 +#define VEC_FRONT_PORCH_RESET 0x00000000
1987 +// -----------------------------------------------------------------------------
1988 +// Field : VEC_FRONT_PORCH_HFP_MINUS1
1989 +// Description : Horizontal front porch
1990 +#define VEC_FRONT_PORCH_HFP_MINUS1_RESET 0x000
1991 +#define VEC_FRONT_PORCH_HFP_MINUS1_BITS 0x03ff0000
1992 +#define VEC_FRONT_PORCH_HFP_MINUS1_MSB 25
1993 +#define VEC_FRONT_PORCH_HFP_MINUS1_LSB 16
1994 +#define VEC_FRONT_PORCH_HFP_MINUS1_ACCESS "RW"
1995 +// -----------------------------------------------------------------------------
1996 +// Field : VEC_FRONT_PORCH_VFP_MINUS1
1997 +// Description : Vertical front porch
1998 +#define VEC_FRONT_PORCH_VFP_MINUS1_RESET 0x000
1999 +#define VEC_FRONT_PORCH_VFP_MINUS1_BITS 0x000003ff
2000 +#define VEC_FRONT_PORCH_VFP_MINUS1_MSB 9
2001 +#define VEC_FRONT_PORCH_VFP_MINUS1_LSB 0
2002 +#define VEC_FRONT_PORCH_VFP_MINUS1_ACCESS "RW"
2003 +// =============================================================================
2004 +// Register : VEC_SHIFT
2005 +// JTAG access : synchronous
2006 +// Description : Positions of R,G,B MS bits in the memory word. Note: due to an
2007 +// unintended red/blue swap, these fields have been renamed since
2008 +// a previous version. There is no functional change.
2009 +#define VEC_SHIFT_OFFSET 0x00000028
2010 +#define VEC_SHIFT_BITS 0x00007fff
2011 +#define VEC_SHIFT_RESET 0x00000000
2012 +// -----------------------------------------------------------------------------
2013 +// Field : VEC_SHIFT_SHIFT_R
2014 +// Description : Red MSB
2015 +#define VEC_SHIFT_SHIFT_R_RESET 0x00
2016 +#define VEC_SHIFT_SHIFT_R_BITS 0x00007c00
2017 +#define VEC_SHIFT_SHIFT_R_MSB 14
2018 +#define VEC_SHIFT_SHIFT_R_LSB 10
2019 +#define VEC_SHIFT_SHIFT_R_ACCESS "RW"
2020 +// -----------------------------------------------------------------------------
2021 +// Field : VEC_SHIFT_SHIFT_G
2022 +// Description : Green MSB
2023 +#define VEC_SHIFT_SHIFT_G_RESET 0x00
2024 +#define VEC_SHIFT_SHIFT_G_BITS 0x000003e0
2025 +#define VEC_SHIFT_SHIFT_G_MSB 9
2026 +#define VEC_SHIFT_SHIFT_G_LSB 5
2027 +#define VEC_SHIFT_SHIFT_G_ACCESS "RW"
2028 +// -----------------------------------------------------------------------------
2029 +// Field : VEC_SHIFT_SHIFT_B
2030 +// Description : Blue MSB
2031 +#define VEC_SHIFT_SHIFT_B_RESET 0x00
2032 +#define VEC_SHIFT_SHIFT_B_BITS 0x0000001f
2033 +#define VEC_SHIFT_SHIFT_B_MSB 4
2034 +#define VEC_SHIFT_SHIFT_B_LSB 0
2035 +#define VEC_SHIFT_SHIFT_B_ACCESS "RW"
2036 +// =============================================================================
2037 +// Register : VEC_IMASK
2038 +// JTAG access : synchronous
2039 +// Description : Masks for R,G,B significant bits, left-justified within 10-bit
2040 +// fields.
2041 +#define VEC_IMASK_OFFSET 0x0000002c
2042 +#define VEC_IMASK_BITS 0x3fffffff
2043 +#define VEC_IMASK_RESET 0x00000000
2044 +// -----------------------------------------------------------------------------
2045 +// Field : VEC_IMASK_MASK_R
2046 +// Description : Red mask
2047 +#define VEC_IMASK_MASK_R_RESET 0x000
2048 +#define VEC_IMASK_MASK_R_BITS 0x3ff00000
2049 +#define VEC_IMASK_MASK_R_MSB 29
2050 +#define VEC_IMASK_MASK_R_LSB 20
2051 +#define VEC_IMASK_MASK_R_ACCESS "RW"
2052 +// -----------------------------------------------------------------------------
2053 +// Field : VEC_IMASK_MASK_G
2054 +// Description : Green mask
2055 +#define VEC_IMASK_MASK_G_RESET 0x000
2056 +#define VEC_IMASK_MASK_G_BITS 0x000ffc00
2057 +#define VEC_IMASK_MASK_G_MSB 19
2058 +#define VEC_IMASK_MASK_G_LSB 10
2059 +#define VEC_IMASK_MASK_G_ACCESS "RW"
2060 +// -----------------------------------------------------------------------------
2061 +// Field : VEC_IMASK_MASK_B
2062 +// Description : Blue mask
2063 +#define VEC_IMASK_MASK_B_RESET 0x000
2064 +#define VEC_IMASK_MASK_B_BITS 0x000003ff
2065 +#define VEC_IMASK_MASK_B_MSB 9
2066 +#define VEC_IMASK_MASK_B_LSB 0
2067 +#define VEC_IMASK_MASK_B_ACCESS "RW"
2068 +// =============================================================================
2069 +// Register : VEC_MODE
2070 +// JTAG access : synchronous
2071 +// Description : None
2072 +#define VEC_MODE_OFFSET 0x00000030
2073 +#define VEC_MODE_BITS 0x01ff003f
2074 +#define VEC_MODE_RESET 0x01c00000
2075 +// -----------------------------------------------------------------------------
2076 +// Field : VEC_MODE_HIGH_WATER
2077 +// Description : ALWAYS WRITE 8'hE0
2078 +#define VEC_MODE_HIGH_WATER_RESET 0xe0
2079 +#define VEC_MODE_HIGH_WATER_BITS 0x01fe0000
2080 +#define VEC_MODE_HIGH_WATER_MSB 24
2081 +#define VEC_MODE_HIGH_WATER_LSB 17
2082 +#define VEC_MODE_HIGH_WATER_ACCESS "RW"
2083 +// -----------------------------------------------------------------------------
2084 +// Field : VEC_MODE_ALIGN16
2085 +// Description : Data: 0=BYTE aligned; 1=BEAT aligned
2086 +#define VEC_MODE_ALIGN16_RESET 0x0
2087 +#define VEC_MODE_ALIGN16_BITS 0x00010000
2088 +#define VEC_MODE_ALIGN16_MSB 16
2089 +#define VEC_MODE_ALIGN16_LSB 16
2090 +#define VEC_MODE_ALIGN16_ACCESS "RW"
2091 +// -----------------------------------------------------------------------------
2092 +// Field : VEC_MODE_VFP_EN
2093 +// Description : Enable vertical front porch
2094 +#define VEC_MODE_VFP_EN_RESET 0x0
2095 +#define VEC_MODE_VFP_EN_BITS 0x00000020
2096 +#define VEC_MODE_VFP_EN_MSB 5
2097 +#define VEC_MODE_VFP_EN_LSB 5
2098 +#define VEC_MODE_VFP_EN_ACCESS "RW"
2099 +// -----------------------------------------------------------------------------
2100 +// Field : VEC_MODE_VBP_EN
2101 +// Description : Enable vertical back porch
2102 +#define VEC_MODE_VBP_EN_RESET 0x0
2103 +#define VEC_MODE_VBP_EN_BITS 0x00000010
2104 +#define VEC_MODE_VBP_EN_MSB 4
2105 +#define VEC_MODE_VBP_EN_LSB 4
2106 +#define VEC_MODE_VBP_EN_ACCESS "RW"
2107 +// -----------------------------------------------------------------------------
2108 +// Field : VEC_MODE_HFP_EN
2109 +// Description : Enable horizontal front porch
2110 +#define VEC_MODE_HFP_EN_RESET 0x0
2111 +#define VEC_MODE_HFP_EN_BITS 0x00000008
2112 +#define VEC_MODE_HFP_EN_MSB 3
2113 +#define VEC_MODE_HFP_EN_LSB 3
2114 +#define VEC_MODE_HFP_EN_ACCESS "RW"
2115 +// -----------------------------------------------------------------------------
2116 +// Field : VEC_MODE_HBP_EN
2117 +// Description : Enable horizontal back porch
2118 +#define VEC_MODE_HBP_EN_RESET 0x0
2119 +#define VEC_MODE_HBP_EN_BITS 0x00000004
2120 +#define VEC_MODE_HBP_EN_MSB 2
2121 +#define VEC_MODE_HBP_EN_LSB 2
2122 +#define VEC_MODE_HBP_EN_ACCESS "RW"
2123 +// -----------------------------------------------------------------------------
2124 +// Field : VEC_MODE_FIELDS_PER_FRAME_MINUS1
2125 +// Description : Interlaced / progressive
2126 +#define VEC_MODE_FIELDS_PER_FRAME_MINUS1_RESET 0x0
2127 +#define VEC_MODE_FIELDS_PER_FRAME_MINUS1_BITS 0x00000002
2128 +#define VEC_MODE_FIELDS_PER_FRAME_MINUS1_MSB 1
2129 +#define VEC_MODE_FIELDS_PER_FRAME_MINUS1_LSB 1
2130 +#define VEC_MODE_FIELDS_PER_FRAME_MINUS1_ACCESS "RW"
2131 +// -----------------------------------------------------------------------------
2132 +// Field : VEC_MODE_FIRST_FIELD_ODD
2133 +// Description : Interlacing order: odd/even or even/odd
2134 +#define VEC_MODE_FIRST_FIELD_ODD_RESET 0x0
2135 +#define VEC_MODE_FIRST_FIELD_ODD_BITS 0x00000001
2136 +#define VEC_MODE_FIRST_FIELD_ODD_MSB 0
2137 +#define VEC_MODE_FIRST_FIELD_ODD_LSB 0
2138 +#define VEC_MODE_FIRST_FIELD_ODD_ACCESS "RW"
2139 +// =============================================================================
2140 +// Register : VEC_RGBSZ
2141 +// JTAG access : synchronous
2142 +// Description : None
2143 +#define VEC_RGBSZ_OFFSET 0x00000034
2144 +#define VEC_RGBSZ_BITS 0x00030fff
2145 +#define VEC_RGBSZ_RESET 0x00000000
2146 +// -----------------------------------------------------------------------------
2147 +// Field : VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1
2148 +// Description : Pixel stride
2149 +#define VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1_RESET 0x0
2150 +#define VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1_BITS 0x00030000
2151 +#define VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1_MSB 17
2152 +#define VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1_LSB 16
2153 +#define VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1_ACCESS "RW"
2154 +// -----------------------------------------------------------------------------
2155 +// Field : VEC_RGBSZ_SCALE_R
2156 +// Description : Red number of bits for shift-and-OR scaling
2157 +#define VEC_RGBSZ_SCALE_R_RESET 0x0
2158 +#define VEC_RGBSZ_SCALE_R_BITS 0x00000f00
2159 +#define VEC_RGBSZ_SCALE_R_MSB 11
2160 +#define VEC_RGBSZ_SCALE_R_LSB 8
2161 +#define VEC_RGBSZ_SCALE_R_ACCESS "RW"
2162 +// -----------------------------------------------------------------------------
2163 +// Field : VEC_RGBSZ_SCALE_G
2164 +// Description : Green number of bits for shift-and-OR scaling
2165 +#define VEC_RGBSZ_SCALE_G_RESET 0x0
2166 +#define VEC_RGBSZ_SCALE_G_BITS 0x000000f0
2167 +#define VEC_RGBSZ_SCALE_G_MSB 7
2168 +#define VEC_RGBSZ_SCALE_G_LSB 4
2169 +#define VEC_RGBSZ_SCALE_G_ACCESS "RW"
2170 +// -----------------------------------------------------------------------------
2171 +// Field : VEC_RGBSZ_SCALE_B
2172 +// Description : Blue number of bits for shift-and-OR scaling
2173 +#define VEC_RGBSZ_SCALE_B_RESET 0x0
2174 +#define VEC_RGBSZ_SCALE_B_BITS 0x0000000f
2175 +#define VEC_RGBSZ_SCALE_B_MSB 3
2176 +#define VEC_RGBSZ_SCALE_B_LSB 0
2177 +#define VEC_RGBSZ_SCALE_B_ACCESS "RW"
2178 +// =============================================================================
2179 +// Register : VEC_PANICS
2180 +// JTAG access : synchronous
2181 +// Description : None
2182 +#define VEC_PANICS_OFFSET 0x00000038
2183 +#define VEC_PANICS_BITS 0xffffffff
2184 +#define VEC_PANICS_RESET 0x00000000
2185 +// -----------------------------------------------------------------------------
2186 +// Field : VEC_PANICS_UCOUNT
2187 +// Description : Upper panic count
2188 +#define VEC_PANICS_UCOUNT_RESET 0x0000
2189 +#define VEC_PANICS_UCOUNT_BITS 0xffff0000
2190 +#define VEC_PANICS_UCOUNT_MSB 31
2191 +#define VEC_PANICS_UCOUNT_LSB 16
2192 +#define VEC_PANICS_UCOUNT_ACCESS "WC"
2193 +// -----------------------------------------------------------------------------
2194 +// Field : VEC_PANICS_LCOUNT
2195 +// Description : Lower panic count
2196 +#define VEC_PANICS_LCOUNT_RESET 0x0000
2197 +#define VEC_PANICS_LCOUNT_BITS 0x0000ffff
2198 +#define VEC_PANICS_LCOUNT_MSB 15
2199 +#define VEC_PANICS_LCOUNT_LSB 0
2200 +#define VEC_PANICS_LCOUNT_ACCESS "WC"
2201 +// =============================================================================
2202 +// Register : VEC_STATUS
2203 +// JTAG access : synchronous
2204 +// Description : None
2205 +#define VEC_STATUS_OFFSET 0x0000003c
2206 +#define VEC_STATUS_BITS 0xff000000
2207 +#define VEC_STATUS_RESET 0x0d000000
2208 +// -----------------------------------------------------------------------------
2209 +// Field : VEC_STATUS_VERSION
2210 +// Description : VEC module version code
2211 +#define VEC_STATUS_VERSION_RESET 0x0d
2212 +#define VEC_STATUS_VERSION_BITS 0xff000000
2213 +#define VEC_STATUS_VERSION_MSB 31
2214 +#define VEC_STATUS_VERSION_LSB 24
2215 +#define VEC_STATUS_VERSION_ACCESS "RO"
2216 +// =============================================================================
2217 +// Register : VEC_DMA_ADDR_H
2218 +// JTAG access : synchronous
2219 +// Description : Upper 32-bits
2220 +#define VEC_DMA_ADDR_H_OFFSET 0x00000040
2221 +#define VEC_DMA_ADDR_H_BITS 0xffffffff
2222 +#define VEC_DMA_ADDR_H_RESET 0x00000000
2223 +// -----------------------------------------------------------------------------
2224 +// Field : VEC_DMA_ADDR_H_AXI_ADDR
2225 +// Description : Byte address of DMA transfer frame buffer.
2226 +#define VEC_DMA_ADDR_H_AXI_ADDR_RESET 0x00000000
2227 +#define VEC_DMA_ADDR_H_AXI_ADDR_BITS 0xffffffff
2228 +#define VEC_DMA_ADDR_H_AXI_ADDR_MSB 31
2229 +#define VEC_DMA_ADDR_H_AXI_ADDR_LSB 0
2230 +#define VEC_DMA_ADDR_H_AXI_ADDR_ACCESS "RW"
2231 +// =============================================================================
2232 +// Register : VEC_BURST_ADDR_L
2233 +// JTAG access : synchronous
2234 +// Description : None
2235 +#define VEC_BURST_ADDR_L_OFFSET 0x00000044
2236 +#define VEC_BURST_ADDR_L_BITS 0xffffffff
2237 +#define VEC_BURST_ADDR_L_RESET 0x00000000
2238 +// -----------------------------------------------------------------------------
2239 +// Field : VEC_BURST_ADDR_L_BURST_ADDR
2240 +// Description : the lower 32-bits of the most recent read request sent to AXI
2241 +// memory.
2242 +#define VEC_BURST_ADDR_L_BURST_ADDR_RESET 0x00000000
2243 +#define VEC_BURST_ADDR_L_BURST_ADDR_BITS 0xffffffff
2244 +#define VEC_BURST_ADDR_L_BURST_ADDR_MSB 31
2245 +#define VEC_BURST_ADDR_L_BURST_ADDR_LSB 0
2246 +#define VEC_BURST_ADDR_L_BURST_ADDR_ACCESS "RO"
2247 +// =============================================================================
2248 +// Register : VEC_APB_TIMEOUT
2249 +// JTAG access : synchronous
2250 +// Description : None
2251 +#define VEC_APB_TIMEOUT_OFFSET 0x00000048
2252 +#define VEC_APB_TIMEOUT_BITS 0x000103ff
2253 +#define VEC_APB_TIMEOUT_RESET 0x00000014
2254 +// -----------------------------------------------------------------------------
2255 +// Field : VEC_APB_TIMEOUT_SLVERR_EN
2256 +// Description : 1 = Assert PREADY and PSLVERR on timeout 0 = Assert PREADY only
2257 +#define VEC_APB_TIMEOUT_SLVERR_EN_RESET 0x0
2258 +#define VEC_APB_TIMEOUT_SLVERR_EN_BITS 0x00010000
2259 +#define VEC_APB_TIMEOUT_SLVERR_EN_MSB 16
2260 +#define VEC_APB_TIMEOUT_SLVERR_EN_LSB 16
2261 +#define VEC_APB_TIMEOUT_SLVERR_EN_ACCESS "RW"
2262 +// -----------------------------------------------------------------------------
2263 +// Field : VEC_APB_TIMEOUT_TIMEOUT
2264 +// Description : Maximum AXI clock cycles to wait for responses from DAC clock
2265 +// domain APB block
2266 +#define VEC_APB_TIMEOUT_TIMEOUT_RESET 0x014
2267 +#define VEC_APB_TIMEOUT_TIMEOUT_BITS 0x000003ff
2268 +#define VEC_APB_TIMEOUT_TIMEOUT_MSB 9
2269 +#define VEC_APB_TIMEOUT_TIMEOUT_LSB 0
2270 +#define VEC_APB_TIMEOUT_TIMEOUT_ACCESS "RW"
2271 +// =============================================================================
2272 +// Register : VEC_DAC_80
2273 +// JTAG access : synchronous
2274 +// Description : None
2275 +#define VEC_DAC_80_OFFSET 0x00000080
2276 +#define VEC_DAC_80_BITS 0x3fff3fff
2277 +#define VEC_DAC_80_RESET 0x00000000
2278 +// -----------------------------------------------------------------------------
2279 +// Field : VEC_DAC_80_U14_DE_BGN
2280 +// Description : Beginning of active data enable within each visible line
2281 +#define VEC_DAC_80_U14_DE_BGN_RESET 0x0000
2282 +#define VEC_DAC_80_U14_DE_BGN_BITS 0x3fff0000
2283 +#define VEC_DAC_80_U14_DE_BGN_MSB 29
2284 +#define VEC_DAC_80_U14_DE_BGN_LSB 16
2285 +#define VEC_DAC_80_U14_DE_BGN_ACCESS "RW"
2286 +// -----------------------------------------------------------------------------
2287 +// Field : VEC_DAC_80_U14_DE_END
2288 +// Description : End of active data enable within each visible line
2289 +#define VEC_DAC_80_U14_DE_END_RESET 0x0000
2290 +#define VEC_DAC_80_U14_DE_END_BITS 0x00003fff
2291 +#define VEC_DAC_80_U14_DE_END_MSB 13
2292 +#define VEC_DAC_80_U14_DE_END_LSB 0
2293 +#define VEC_DAC_80_U14_DE_END_ACCESS "RW"
2294 +// =============================================================================
2295 +// Register : VEC_DAC_84
2296 +// JTAG access : synchronous
2297 +// Description : None
2298 +#define VEC_DAC_84_OFFSET 0x00000084
2299 +#define VEC_DAC_84_BITS 0x1fff1fff
2300 +#define VEC_DAC_84_RESET 0x00000000
2301 +// -----------------------------------------------------------------------------
2302 +// Field : VEC_DAC_84_U13_ACTIVE_RISE
2303 +// Description : Horizontal blanking interval
2304 +#define VEC_DAC_84_U13_ACTIVE_RISE_RESET 0x0000
2305 +#define VEC_DAC_84_U13_ACTIVE_RISE_BITS 0x1fff0000
2306 +#define VEC_DAC_84_U13_ACTIVE_RISE_MSB 28
2307 +#define VEC_DAC_84_U13_ACTIVE_RISE_LSB 16
2308 +#define VEC_DAC_84_U13_ACTIVE_RISE_ACCESS "RW"
2309 +// -----------------------------------------------------------------------------
2310 +// Field : VEC_DAC_84_U13_ACTIVE_FALL
2311 +// Description : Horizontal blanking interval
2312 +#define VEC_DAC_84_U13_ACTIVE_FALL_RESET 0x0000
2313 +#define VEC_DAC_84_U13_ACTIVE_FALL_BITS 0x00001fff
2314 +#define VEC_DAC_84_U13_ACTIVE_FALL_MSB 12
2315 +#define VEC_DAC_84_U13_ACTIVE_FALL_LSB 0
2316 +#define VEC_DAC_84_U13_ACTIVE_FALL_ACCESS "RW"
2317 +// =============================================================================
2318 +// Register : VEC_DAC_88
2319 +// JTAG access : synchronous
2320 +// Description : None
2321 +#define VEC_DAC_88_OFFSET 0x00000088
2322 +#define VEC_DAC_88_BITS 0x1fff1fff
2323 +#define VEC_DAC_88_RESET 0x00000000
2324 +// -----------------------------------------------------------------------------
2325 +// Field : VEC_DAC_88_U13_HALF_LINE_PERIOD
2326 +// Description : Ratio of DAC clock to horizontal line rate, halved
2327 +#define VEC_DAC_88_U13_HALF_LINE_PERIOD_RESET 0x0000
2328 +#define VEC_DAC_88_U13_HALF_LINE_PERIOD_BITS 0x1fff0000
2329 +#define VEC_DAC_88_U13_HALF_LINE_PERIOD_MSB 28
2330 +#define VEC_DAC_88_U13_HALF_LINE_PERIOD_LSB 16
2331 +#define VEC_DAC_88_U13_HALF_LINE_PERIOD_ACCESS "RW"
2332 +// -----------------------------------------------------------------------------
2333 +// Field : VEC_DAC_88_U13_HORZ_SYNC
2334 +// Description : Width of horizontal sync pulses
2335 +#define VEC_DAC_88_U13_HORZ_SYNC_RESET 0x0000
2336 +#define VEC_DAC_88_U13_HORZ_SYNC_BITS 0x00001fff
2337 +#define VEC_DAC_88_U13_HORZ_SYNC_MSB 12
2338 +#define VEC_DAC_88_U13_HORZ_SYNC_LSB 0
2339 +#define VEC_DAC_88_U13_HORZ_SYNC_ACCESS "RW"
2340 +// =============================================================================
2341 +// Register : VEC_DAC_8C
2342 +// JTAG access : synchronous
2343 +// Description : None
2344 +#define VEC_DAC_8C_OFFSET 0x0000008c
2345 +#define VEC_DAC_8C_BITS 0x1fff1fff
2346 +#define VEC_DAC_8C_RESET 0x00000000
2347 +// -----------------------------------------------------------------------------
2348 +// Field : VEC_DAC_8C_U13_BURST_RISE
2349 +// Description : Start of raised-cosine colour burst envelope
2350 +#define VEC_DAC_8C_U13_BURST_RISE_RESET 0x0000
2351 +#define VEC_DAC_8C_U13_BURST_RISE_BITS 0x1fff0000
2352 +#define VEC_DAC_8C_U13_BURST_RISE_MSB 28
2353 +#define VEC_DAC_8C_U13_BURST_RISE_LSB 16
2354 +#define VEC_DAC_8C_U13_BURST_RISE_ACCESS "RW"
2355 +// -----------------------------------------------------------------------------
2356 +// Field : VEC_DAC_8C_U13_BURST_FALL
2357 +// Description : End of raised-cosine colour burst envelope
2358 +#define VEC_DAC_8C_U13_BURST_FALL_RESET 0x0000
2359 +#define VEC_DAC_8C_U13_BURST_FALL_BITS 0x00001fff
2360 +#define VEC_DAC_8C_U13_BURST_FALL_MSB 12
2361 +#define VEC_DAC_8C_U13_BURST_FALL_LSB 0
2362 +#define VEC_DAC_8C_U13_BURST_FALL_ACCESS "RW"
2363 +// =============================================================================
2364 +// Register : VEC_DAC_90
2365 +// JTAG access : synchronous
2366 +// Description : None
2367 +#define VEC_DAC_90_OFFSET 0x00000090
2368 +#define VEC_DAC_90_BITS 0x1fff3fff
2369 +#define VEC_DAC_90_RESET 0x00000000
2370 +// -----------------------------------------------------------------------------
2371 +// Field : VEC_DAC_90_U13_VERT_EQ
2372 +// Description : Width of vertical equalisation pulses (= half line minus
2373 +// serration)
2374 +#define VEC_DAC_90_U13_VERT_EQ_RESET 0x0000
2375 +#define VEC_DAC_90_U13_VERT_EQ_BITS 0x1fff0000
2376 +#define VEC_DAC_90_U13_VERT_EQ_MSB 28
2377 +#define VEC_DAC_90_U13_VERT_EQ_LSB 16
2378 +#define VEC_DAC_90_U13_VERT_EQ_ACCESS "RW"
2379 +// -----------------------------------------------------------------------------
2380 +// Field : VEC_DAC_90_U14_VERT_SYNC
2381 +// Description : Width of vertical sync pulses
2382 +#define VEC_DAC_90_U14_VERT_SYNC_RESET 0x0000
2383 +#define VEC_DAC_90_U14_VERT_SYNC_BITS 0x00003fff
2384 +#define VEC_DAC_90_U14_VERT_SYNC_MSB 13
2385 +#define VEC_DAC_90_U14_VERT_SYNC_LSB 0
2386 +#define VEC_DAC_90_U14_VERT_SYNC_ACCESS "RW"
2387 +// =============================================================================
2388 +// Register : VEC_DAC_94
2389 +// JTAG access : synchronous
2390 +// Description : None
2391 +#define VEC_DAC_94_OFFSET 0x00000094
2392 +#define VEC_DAC_94_BITS 0x03ff03ff
2393 +#define VEC_DAC_94_RESET 0x00000000
2394 +// -----------------------------------------------------------------------------
2395 +// Field : VEC_DAC_94_U10_PRE_EQ_BGN
2396 +// Description : Half-lines, inclusive, relative to field datum, where vertical
2397 +// pre-equalisation pulses start
2398 +#define VEC_DAC_94_U10_PRE_EQ_BGN_RESET 0x000
2399 +#define VEC_DAC_94_U10_PRE_EQ_BGN_BITS 0x03ff0000
2400 +#define VEC_DAC_94_U10_PRE_EQ_BGN_MSB 25
2401 +#define VEC_DAC_94_U10_PRE_EQ_BGN_LSB 16
2402 +#define VEC_DAC_94_U10_PRE_EQ_BGN_ACCESS "RW"
2403 +// -----------------------------------------------------------------------------
2404 +// Field : VEC_DAC_94_U10_PRE_EQ_END
2405 +// Description : Half-lines, inclusive, relative to field datum, where vertical
2406 +// pre-equalisation pulses end
2407 +#define VEC_DAC_94_U10_PRE_EQ_END_RESET 0x000
2408 +#define VEC_DAC_94_U10_PRE_EQ_END_BITS 0x000003ff
2409 +#define VEC_DAC_94_U10_PRE_EQ_END_MSB 9
2410 +#define VEC_DAC_94_U10_PRE_EQ_END_LSB 0
2411 +#define VEC_DAC_94_U10_PRE_EQ_END_ACCESS "RW"
2412 +// =============================================================================
2413 +// Register : VEC_DAC_98
2414 +// JTAG access : synchronous
2415 +// Description : None
2416 +#define VEC_DAC_98_OFFSET 0x00000098
2417 +#define VEC_DAC_98_BITS 0x03ff03ff
2418 +#define VEC_DAC_98_RESET 0x00000000
2419 +// -----------------------------------------------------------------------------
2420 +// Field : VEC_DAC_98_U10_FIELD_SYNC_BGN
2421 +// Description : Half-lines containing vertical sync pulses (inclusive)
2422 +#define VEC_DAC_98_U10_FIELD_SYNC_BGN_RESET 0x000
2423 +#define VEC_DAC_98_U10_FIELD_SYNC_BGN_BITS 0x03ff0000
2424 +#define VEC_DAC_98_U10_FIELD_SYNC_BGN_MSB 25
2425 +#define VEC_DAC_98_U10_FIELD_SYNC_BGN_LSB 16
2426 +#define VEC_DAC_98_U10_FIELD_SYNC_BGN_ACCESS "RW"
2427 +// -----------------------------------------------------------------------------
2428 +// Field : VEC_DAC_98_U10_FIELD_SYNC_END
2429 +// Description : Half-lines containing vertical sync pulses (inclusive)
2430 +#define VEC_DAC_98_U10_FIELD_SYNC_END_RESET 0x000
2431 +#define VEC_DAC_98_U10_FIELD_SYNC_END_BITS 0x000003ff
2432 +#define VEC_DAC_98_U10_FIELD_SYNC_END_MSB 9
2433 +#define VEC_DAC_98_U10_FIELD_SYNC_END_LSB 0
2434 +#define VEC_DAC_98_U10_FIELD_SYNC_END_ACCESS "RW"
2435 +// =============================================================================
2436 +// Register : VEC_DAC_9C
2437 +// JTAG access : synchronous
2438 +// Description : None
2439 +#define VEC_DAC_9C_OFFSET 0x0000009c
2440 +#define VEC_DAC_9C_BITS 0x03ff03ff
2441 +#define VEC_DAC_9C_RESET 0x00000000
2442 +// -----------------------------------------------------------------------------
2443 +// Field : VEC_DAC_9C_U10_POST_EQ_BGN
2444 +// Description : Half-lines containing vertical post-equalisation pulses
2445 +#define VEC_DAC_9C_U10_POST_EQ_BGN_RESET 0x000
2446 +#define VEC_DAC_9C_U10_POST_EQ_BGN_BITS 0x03ff0000
2447 +#define VEC_DAC_9C_U10_POST_EQ_BGN_MSB 25
2448 +#define VEC_DAC_9C_U10_POST_EQ_BGN_LSB 16
2449 +#define VEC_DAC_9C_U10_POST_EQ_BGN_ACCESS "RW"
2450 +// -----------------------------------------------------------------------------
2451 +// Field : VEC_DAC_9C_U10_POST_EQ_END
2452 +// Description : Half-lines containing vertical post-equalisation pulses
2453 +#define VEC_DAC_9C_U10_POST_EQ_END_RESET 0x000
2454 +#define VEC_DAC_9C_U10_POST_EQ_END_BITS 0x000003ff
2455 +#define VEC_DAC_9C_U10_POST_EQ_END_MSB 9
2456 +#define VEC_DAC_9C_U10_POST_EQ_END_LSB 0
2457 +#define VEC_DAC_9C_U10_POST_EQ_END_ACCESS "RW"
2458 +// =============================================================================
2459 +// Register : VEC_DAC_A0
2460 +// JTAG access : synchronous
2461 +// Description : None
2462 +#define VEC_DAC_A0_OFFSET 0x000000a0
2463 +#define VEC_DAC_A0_BITS 0x03ff03ff
2464 +#define VEC_DAC_A0_RESET 0x00000000
2465 +// -----------------------------------------------------------------------------
2466 +// Field : VEC_DAC_A0_U10_FLD1_BURST_BGN
2467 +// Description : First and last full frame lines (1-based numbering) within the
2468 +// PAL/NTSC four field sequence which require a colour burst
2469 +#define VEC_DAC_A0_U10_FLD1_BURST_BGN_RESET 0x000
2470 +#define VEC_DAC_A0_U10_FLD1_BURST_BGN_BITS 0x03ff0000
2471 +#define VEC_DAC_A0_U10_FLD1_BURST_BGN_MSB 25
2472 +#define VEC_DAC_A0_U10_FLD1_BURST_BGN_LSB 16
2473 +#define VEC_DAC_A0_U10_FLD1_BURST_BGN_ACCESS "RW"
2474 +// -----------------------------------------------------------------------------
2475 +// Field : VEC_DAC_A0_U10_FLD1_BURST_END
2476 +// Description : First and last full frame lines (1-based numbering) within the
2477 +// PAL/NTSC four field sequence which require a colour burst
2478 +#define VEC_DAC_A0_U10_FLD1_BURST_END_RESET 0x000
2479 +#define VEC_DAC_A0_U10_FLD1_BURST_END_BITS 0x000003ff
2480 +#define VEC_DAC_A0_U10_FLD1_BURST_END_MSB 9
2481 +#define VEC_DAC_A0_U10_FLD1_BURST_END_LSB 0
2482 +#define VEC_DAC_A0_U10_FLD1_BURST_END_ACCESS "RW"
2483 +// =============================================================================
2484 +// Register : VEC_DAC_A4
2485 +// JTAG access : synchronous
2486 +// Description : None
2487 +#define VEC_DAC_A4_OFFSET 0x000000a4
2488 +#define VEC_DAC_A4_BITS 0x03ff03ff
2489 +#define VEC_DAC_A4_RESET 0x00000000
2490 +// -----------------------------------------------------------------------------
2491 +// Field : VEC_DAC_A4_U10_FLD2_BURST_BGN
2492 +// Description : First and last full frame lines (1-based numbering) within the
2493 +// PAL/NTSC four field sequence which require a colour burst
2494 +#define VEC_DAC_A4_U10_FLD2_BURST_BGN_RESET 0x000
2495 +#define VEC_DAC_A4_U10_FLD2_BURST_BGN_BITS 0x03ff0000
2496 +#define VEC_DAC_A4_U10_FLD2_BURST_BGN_MSB 25
2497 +#define VEC_DAC_A4_U10_FLD2_BURST_BGN_LSB 16
2498 +#define VEC_DAC_A4_U10_FLD2_BURST_BGN_ACCESS "RW"
2499 +// -----------------------------------------------------------------------------
2500 +// Field : VEC_DAC_A4_U10_FLD2_BURST_END
2501 +// Description : First and last full frame lines (1-based numbering) within the
2502 +// PAL/NTSC four field sequence which require a colour burst
2503 +#define VEC_DAC_A4_U10_FLD2_BURST_END_RESET 0x000
2504 +#define VEC_DAC_A4_U10_FLD2_BURST_END_BITS 0x000003ff
2505 +#define VEC_DAC_A4_U10_FLD2_BURST_END_MSB 9
2506 +#define VEC_DAC_A4_U10_FLD2_BURST_END_LSB 0
2507 +#define VEC_DAC_A4_U10_FLD2_BURST_END_ACCESS "RW"
2508 +// =============================================================================
2509 +// Register : VEC_DAC_A8
2510 +// JTAG access : synchronous
2511 +// Description : None
2512 +#define VEC_DAC_A8_OFFSET 0x000000a8
2513 +#define VEC_DAC_A8_BITS 0x03ff03ff
2514 +#define VEC_DAC_A8_RESET 0x00000000
2515 +// -----------------------------------------------------------------------------
2516 +// Field : VEC_DAC_A8_U10_FLD3_BURST_BGN
2517 +// Description : First and last full frame lines (1-based numbering) within the
2518 +// PAL/NTSC four field sequence which require a colour burst
2519 +#define VEC_DAC_A8_U10_FLD3_BURST_BGN_RESET 0x000
2520 +#define VEC_DAC_A8_U10_FLD3_BURST_BGN_BITS 0x03ff0000
2521 +#define VEC_DAC_A8_U10_FLD3_BURST_BGN_MSB 25
2522 +#define VEC_DAC_A8_U10_FLD3_BURST_BGN_LSB 16
2523 +#define VEC_DAC_A8_U10_FLD3_BURST_BGN_ACCESS "RW"
2524 +// -----------------------------------------------------------------------------
2525 +// Field : VEC_DAC_A8_U10_FLD3_BURST_END
2526 +// Description : First and last full frame lines (1-based numbering) within the
2527 +// PAL/NTSC four field sequence which require a colour burst
2528 +#define VEC_DAC_A8_U10_FLD3_BURST_END_RESET 0x000
2529 +#define VEC_DAC_A8_U10_FLD3_BURST_END_BITS 0x000003ff
2530 +#define VEC_DAC_A8_U10_FLD3_BURST_END_MSB 9
2531 +#define VEC_DAC_A8_U10_FLD3_BURST_END_LSB 0
2532 +#define VEC_DAC_A8_U10_FLD3_BURST_END_ACCESS "RW"
2533 +// =============================================================================
2534 +// Register : VEC_DAC_AC
2535 +// JTAG access : synchronous
2536 +// Description : None
2537 +#define VEC_DAC_AC_OFFSET 0x000000ac
2538 +#define VEC_DAC_AC_BITS 0x03ff03ff
2539 +#define VEC_DAC_AC_RESET 0x00000000
2540 +// -----------------------------------------------------------------------------
2541 +// Field : VEC_DAC_AC_U10_FLD4_BURST_BGN
2542 +// Description : First and last full frame lines (1-based numbering) within the
2543 +// PAL/NTSC four field sequence which require a colour burst
2544 +#define VEC_DAC_AC_U10_FLD4_BURST_BGN_RESET 0x000
2545 +#define VEC_DAC_AC_U10_FLD4_BURST_BGN_BITS 0x03ff0000
2546 +#define VEC_DAC_AC_U10_FLD4_BURST_BGN_MSB 25
2547 +#define VEC_DAC_AC_U10_FLD4_BURST_BGN_LSB 16
2548 +#define VEC_DAC_AC_U10_FLD4_BURST_BGN_ACCESS "RW"
2549 +// -----------------------------------------------------------------------------
2550 +// Field : VEC_DAC_AC_U10_FLD4_BURST_END
2551 +// Description : First and last full frame lines (1-based numbering) within the
2552 +// PAL/NTSC four field sequence which require a colour burst
2553 +#define VEC_DAC_AC_U10_FLD4_BURST_END_RESET 0x000
2554 +#define VEC_DAC_AC_U10_FLD4_BURST_END_BITS 0x000003ff
2555 +#define VEC_DAC_AC_U10_FLD4_BURST_END_MSB 9
2556 +#define VEC_DAC_AC_U10_FLD4_BURST_END_LSB 0
2557 +#define VEC_DAC_AC_U10_FLD4_BURST_END_ACCESS "RW"
2558 +// =============================================================================
2559 +// Register : VEC_DAC_B0
2560 +// JTAG access : synchronous
2561 +// Description : None
2562 +#define VEC_DAC_B0_OFFSET 0x000000b0
2563 +#define VEC_DAC_B0_BITS 0x03ff03ff
2564 +#define VEC_DAC_B0_RESET 0x00000000
2565 +// -----------------------------------------------------------------------------
2566 +// Field : VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN
2567 +// Description : First and last full visible lines (1-based numbering) in the
2568 +// PAL/NTSC four field sequence
2569 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN_RESET 0x000
2570 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN_BITS 0x03ff0000
2571 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN_MSB 25
2572 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN_LSB 16
2573 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN_ACCESS "RW"
2574 +// -----------------------------------------------------------------------------
2575 +// Field : VEC_DAC_B0_U10_FLD24_FULL_LINE_END
2576 +// Description : First and last full visible lines (1-based numbering) in the
2577 +// PAL/NTSC four field sequence
2578 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_END_RESET 0x000
2579 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_END_BITS 0x000003ff
2580 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_END_MSB 9
2581 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_END_LSB 0
2582 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_END_ACCESS "RW"
2583 +// =============================================================================
2584 +// Register : VEC_DAC_B4
2585 +// JTAG access : synchronous
2586 +// Description : None
2587 +#define VEC_DAC_B4_OFFSET 0x000000b4
2588 +#define VEC_DAC_B4_BITS 0x03ff03ff
2589 +#define VEC_DAC_B4_RESET 0x00000000
2590 +// -----------------------------------------------------------------------------
2591 +// Field : VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN
2592 +// Description : First and last full visible lines (1-based numbering) in the
2593 +// PAL/NTSC four field sequence
2594 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN_RESET 0x000
2595 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN_BITS 0x03ff0000
2596 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN_MSB 25
2597 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN_LSB 16
2598 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN_ACCESS "RW"
2599 +// -----------------------------------------------------------------------------
2600 +// Field : VEC_DAC_B4_U10_FLD13_FULL_LINE_END
2601 +// Description : First and last full visible lines (1-based numbering) in the
2602 +// PAL/NTSC four field sequence
2603 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_END_RESET 0x000
2604 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_END_BITS 0x000003ff
2605 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_END_MSB 9
2606 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_END_LSB 0
2607 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_END_ACCESS "RW"
2608 +// =============================================================================
2609 +// Register : VEC_DAC_B8
2610 +// JTAG access : synchronous
2611 +// Description : None
2612 +#define VEC_DAC_B8_OFFSET 0x000000b8
2613 +#define VEC_DAC_B8_BITS 0x03ff03ff
2614 +#define VEC_DAC_B8_RESET 0x00000000
2615 +// -----------------------------------------------------------------------------
2616 +// Field : VEC_DAC_B8_U10_BOT_HALF_LINE
2617 +// Description : Top and bottom visible half-lines in 1-based standard full
2618 +// frame numbering, for interlaced modes. Set to zero to disable.
2619 +#define VEC_DAC_B8_U10_BOT_HALF_LINE_RESET 0x000
2620 +#define VEC_DAC_B8_U10_BOT_HALF_LINE_BITS 0x03ff0000
2621 +#define VEC_DAC_B8_U10_BOT_HALF_LINE_MSB 25
2622 +#define VEC_DAC_B8_U10_BOT_HALF_LINE_LSB 16
2623 +#define VEC_DAC_B8_U10_BOT_HALF_LINE_ACCESS "RW"
2624 +// -----------------------------------------------------------------------------
2625 +// Field : VEC_DAC_B8_U10_TOP_HALF_LINE
2626 +// Description : Top and bottom visible half-lines in 1-based standard full
2627 +// frame numbering, for interlaced modes. Set to zero to disable.
2628 +#define VEC_DAC_B8_U10_TOP_HALF_LINE_RESET 0x000
2629 +#define VEC_DAC_B8_U10_TOP_HALF_LINE_BITS 0x000003ff
2630 +#define VEC_DAC_B8_U10_TOP_HALF_LINE_MSB 9
2631 +#define VEC_DAC_B8_U10_TOP_HALF_LINE_LSB 0
2632 +#define VEC_DAC_B8_U10_TOP_HALF_LINE_ACCESS "RW"
2633 +// =============================================================================
2634 +// Register : VEC_DAC_BC
2635 +// JTAG access : synchronous
2636 +// Description : None
2637 +#define VEC_DAC_BC_OFFSET 0x000000bc
2638 +#define VEC_DAC_BC_BITS 0x07ff07ff
2639 +#define VEC_DAC_BC_RESET 0x00000000
2640 +// -----------------------------------------------------------------------------
2641 +// Field : VEC_DAC_BC_S11_PEDESTAL
2642 +// Description : NTSC pedestal. For 7.5 IRE, this field is 1024 * 7.5/100. For
2643 +// PAL, or Japanese NTSC, this field should be zero.
2644 +#define VEC_DAC_BC_S11_PEDESTAL_RESET 0x000
2645 +#define VEC_DAC_BC_S11_PEDESTAL_BITS 0x07ff0000
2646 +#define VEC_DAC_BC_S11_PEDESTAL_MSB 26
2647 +#define VEC_DAC_BC_S11_PEDESTAL_LSB 16
2648 +#define VEC_DAC_BC_S11_PEDESTAL_ACCESS "RW"
2649 +// -----------------------------------------------------------------------------
2650 +// Field : VEC_DAC_BC_U11_HALF_LINES_PER_FIELD
2651 +// Description : Mode = 625 PAL, Lines per field = 312.5,
2652 +// u11_half_lines_per_field = 1+2*312 Mode = 525 NTSC, Lines per
2653 +// field = 262.5, u11_half_lines_per_field = 1+2*262
2654 +#define VEC_DAC_BC_U11_HALF_LINES_PER_FIELD_RESET 0x000
2655 +#define VEC_DAC_BC_U11_HALF_LINES_PER_FIELD_BITS 0x000007ff
2656 +#define VEC_DAC_BC_U11_HALF_LINES_PER_FIELD_MSB 10
2657 +#define VEC_DAC_BC_U11_HALF_LINES_PER_FIELD_LSB 0
2658 +#define VEC_DAC_BC_U11_HALF_LINES_PER_FIELD_ACCESS "RW"
2659 +// =============================================================================
2660 +// Register : VEC_DAC_C0
2661 +// JTAG access : synchronous
2662 +// Description : Synopsis DesignWare control
2663 +#define VEC_DAC_C0_OFFSET 0x000000c0
2664 +#define VEC_DAC_C0_BITS 0x000fffff
2665 +#define VEC_DAC_C0_RESET 0x00000000
2666 +// -----------------------------------------------------------------------------
2667 +// Field : VEC_DAC_C0_DWC_CABLE_ENCTR3
2668 +// Description : Synopsis test input
2669 +#define VEC_DAC_C0_DWC_CABLE_ENCTR3_RESET 0x0
2670 +#define VEC_DAC_C0_DWC_CABLE_ENCTR3_BITS 0x00080000
2671 +#define VEC_DAC_C0_DWC_CABLE_ENCTR3_MSB 19
2672 +#define VEC_DAC_C0_DWC_CABLE_ENCTR3_LSB 19
2673 +#define VEC_DAC_C0_DWC_CABLE_ENCTR3_ACCESS "RO"
2674 +// -----------------------------------------------------------------------------
2675 +// Field : VEC_DAC_C0_DWC_CABLE_CABLEOUT
2676 +// Description : cable detect state
2677 +#define VEC_DAC_C0_DWC_CABLE_CABLEOUT_RESET 0x0
2678 +#define VEC_DAC_C0_DWC_CABLE_CABLEOUT_BITS 0x00070000
2679 +#define VEC_DAC_C0_DWC_CABLE_CABLEOUT_MSB 18
2680 +#define VEC_DAC_C0_DWC_CABLE_CABLEOUT_LSB 16
2681 +#define VEC_DAC_C0_DWC_CABLE_CABLEOUT_ACCESS "RO"
2682 +// -----------------------------------------------------------------------------
2683 +// Field : VEC_DAC_C0_DWC_MUX_2
2684 +// Description : Select DAC channel 2 output
2685 +#define VEC_DAC_C0_DWC_MUX_2_RESET 0x0
2686 +#define VEC_DAC_C0_DWC_MUX_2_BITS 0x0000c000
2687 +#define VEC_DAC_C0_DWC_MUX_2_MSB 15
2688 +#define VEC_DAC_C0_DWC_MUX_2_LSB 14
2689 +#define VEC_DAC_C0_DWC_MUX_2_ACCESS "RW"
2690 +// -----------------------------------------------------------------------------
2691 +// Field : VEC_DAC_C0_DWC_MUX_1
2692 +// Description : Select DAC channel 1 output
2693 +#define VEC_DAC_C0_DWC_MUX_1_RESET 0x0
2694 +#define VEC_DAC_C0_DWC_MUX_1_BITS 0x00003000
2695 +#define VEC_DAC_C0_DWC_MUX_1_MSB 13
2696 +#define VEC_DAC_C0_DWC_MUX_1_LSB 12
2697 +#define VEC_DAC_C0_DWC_MUX_1_ACCESS "RW"
2698 +// -----------------------------------------------------------------------------
2699 +// Field : VEC_DAC_C0_DWC_MUX_0
2700 +// Description : Select DAC channel 0 output
2701 +#define VEC_DAC_C0_DWC_MUX_0_RESET 0x0
2702 +#define VEC_DAC_C0_DWC_MUX_0_BITS 0x00000c00
2703 +#define VEC_DAC_C0_DWC_MUX_0_MSB 11
2704 +#define VEC_DAC_C0_DWC_MUX_0_LSB 10
2705 +#define VEC_DAC_C0_DWC_MUX_0_ACCESS "RW"
2706 +// -----------------------------------------------------------------------------
2707 +// Field : VEC_DAC_C0_DWC_TEST
2708 +// Description : Fixed DAC command word
2709 +#define VEC_DAC_C0_DWC_TEST_RESET 0x000
2710 +#define VEC_DAC_C0_DWC_TEST_BITS 0x000003ff
2711 +#define VEC_DAC_C0_DWC_TEST_MSB 9
2712 +#define VEC_DAC_C0_DWC_TEST_LSB 0
2713 +#define VEC_DAC_C0_DWC_TEST_ACCESS "RW"
2714 +// =============================================================================
2715 +// Register : VEC_DAC_C4
2716 +// JTAG access : synchronous
2717 +// Description : Synopsis DAC control
2718 +#define VEC_DAC_C4_OFFSET 0x000000c4
2719 +#define VEC_DAC_C4_BITS 0x1fffffff
2720 +#define VEC_DAC_C4_RESET 0x00000000
2721 +// -----------------------------------------------------------------------------
2722 +// Field : VEC_DAC_C4_ENCTR
2723 +// Description : Always write3'b000
2724 +#define VEC_DAC_C4_ENCTR_RESET 0x0
2725 +#define VEC_DAC_C4_ENCTR_BITS 0x1c000000
2726 +#define VEC_DAC_C4_ENCTR_MSB 28
2727 +#define VEC_DAC_C4_ENCTR_LSB 26
2728 +#define VEC_DAC_C4_ENCTR_ACCESS "RW"
2729 +// -----------------------------------------------------------------------------
2730 +// Field : VEC_DAC_C4_ENSC
2731 +// Description : Enable cable detect - write 3'b000
2732 +#define VEC_DAC_C4_ENSC_RESET 0x0
2733 +#define VEC_DAC_C4_ENSC_BITS 0x03800000
2734 +#define VEC_DAC_C4_ENSC_MSB 25
2735 +#define VEC_DAC_C4_ENSC_LSB 23
2736 +#define VEC_DAC_C4_ENSC_ACCESS "RW"
2737 +// -----------------------------------------------------------------------------
2738 +// Field : VEC_DAC_C4_ENDAC
2739 +// Description : Enable DAC channel
2740 +#define VEC_DAC_C4_ENDAC_RESET 0x0
2741 +#define VEC_DAC_C4_ENDAC_BITS 0x00700000
2742 +#define VEC_DAC_C4_ENDAC_MSB 22
2743 +#define VEC_DAC_C4_ENDAC_LSB 20
2744 +#define VEC_DAC_C4_ENDAC_ACCESS "RW"
2745 +// -----------------------------------------------------------------------------
2746 +// Field : VEC_DAC_C4_ENVBG
2747 +// Description : Enable internal bandgap reference - write '1'
2748 +#define VEC_DAC_C4_ENVBG_RESET 0x0
2749 +#define VEC_DAC_C4_ENVBG_BITS 0x00080000
2750 +#define VEC_DAC_C4_ENVBG_MSB 19
2751 +#define VEC_DAC_C4_ENVBG_LSB 19
2752 +#define VEC_DAC_C4_ENVBG_ACCESS "RW"
2753 +// -----------------------------------------------------------------------------
2754 +// Field : VEC_DAC_C4_ENEXTREF
2755 +// Description : Enable external reference - write '0'
2756 +#define VEC_DAC_C4_ENEXTREF_RESET 0x0
2757 +#define VEC_DAC_C4_ENEXTREF_BITS 0x00040000
2758 +#define VEC_DAC_C4_ENEXTREF_MSB 18
2759 +#define VEC_DAC_C4_ENEXTREF_LSB 18
2760 +#define VEC_DAC_C4_ENEXTREF_ACCESS "RW"
2761 +// -----------------------------------------------------------------------------
2762 +// Field : VEC_DAC_C4_DAC2GC
2763 +// Description : DAC channel 2 gain control - write 6'd63
2764 +#define VEC_DAC_C4_DAC2GC_RESET 0x00
2765 +#define VEC_DAC_C4_DAC2GC_BITS 0x0003f000
2766 +#define VEC_DAC_C4_DAC2GC_MSB 17
2767 +#define VEC_DAC_C4_DAC2GC_LSB 12
2768 +#define VEC_DAC_C4_DAC2GC_ACCESS "RW"
2769 +// -----------------------------------------------------------------------------
2770 +// Field : VEC_DAC_C4_DAC1GC
2771 +// Description : DAC channel 1 gain control - write 6'd63
2772 +#define VEC_DAC_C4_DAC1GC_RESET 0x00
2773 +#define VEC_DAC_C4_DAC1GC_BITS 0x00000fc0
2774 +#define VEC_DAC_C4_DAC1GC_MSB 11
2775 +#define VEC_DAC_C4_DAC1GC_LSB 6
2776 +#define VEC_DAC_C4_DAC1GC_ACCESS "RW"
2777 +// -----------------------------------------------------------------------------
2778 +// Field : VEC_DAC_C4_DAC0GC
2779 +// Description : DAC channel 0 gain control - write 6'd63
2780 +#define VEC_DAC_C4_DAC0GC_RESET 0x00
2781 +#define VEC_DAC_C4_DAC0GC_BITS 0x0000003f
2782 +#define VEC_DAC_C4_DAC0GC_MSB 5
2783 +#define VEC_DAC_C4_DAC0GC_LSB 0
2784 +#define VEC_DAC_C4_DAC0GC_ACCESS "RW"
2785 +// =============================================================================
2786 +// Register : VEC_DAC_C8
2787 +// JTAG access : synchronous
2788 +// Description : None
2789 +#define VEC_DAC_C8_OFFSET 0x000000c8
2790 +#define VEC_DAC_C8_BITS 0xffffffff
2791 +#define VEC_DAC_C8_RESET 0x00000000
2792 +// -----------------------------------------------------------------------------
2793 +// Field : VEC_DAC_C8_U16_SCALE_SYNC
2794 +// Description : Scaling applied prior to final summation to form the DAC
2795 +// command word(s)
2796 +#define VEC_DAC_C8_U16_SCALE_SYNC_RESET 0x0000
2797 +#define VEC_DAC_C8_U16_SCALE_SYNC_BITS 0xffff0000
2798 +#define VEC_DAC_C8_U16_SCALE_SYNC_MSB 31
2799 +#define VEC_DAC_C8_U16_SCALE_SYNC_LSB 16
2800 +#define VEC_DAC_C8_U16_SCALE_SYNC_ACCESS "RW"
2801 +// -----------------------------------------------------------------------------
2802 +// Field : VEC_DAC_C8_U16_SCALE_LUMA
2803 +// Description : Scaling applied prior to final summation to form the DAC
2804 +// command word(s)
2805 +#define VEC_DAC_C8_U16_SCALE_LUMA_RESET 0x0000
2806 +#define VEC_DAC_C8_U16_SCALE_LUMA_BITS 0x0000ffff
2807 +#define VEC_DAC_C8_U16_SCALE_LUMA_MSB 15
2808 +#define VEC_DAC_C8_U16_SCALE_LUMA_LSB 0
2809 +#define VEC_DAC_C8_U16_SCALE_LUMA_ACCESS "RW"
2810 +// =============================================================================
2811 +// Register : VEC_DAC_CC
2812 +// JTAG access : synchronous
2813 +// Description : None
2814 +#define VEC_DAC_CC_OFFSET 0x000000cc
2815 +#define VEC_DAC_CC_BITS 0xffffffff
2816 +#define VEC_DAC_CC_RESET 0x00000000
2817 +// -----------------------------------------------------------------------------
2818 +// Field : VEC_DAC_CC_S16_SCALE_BURST
2819 +// Description : Scaling applied prior to final summation to form the DAC
2820 +// command word(s)
2821 +#define VEC_DAC_CC_S16_SCALE_BURST_RESET 0x0000
2822 +#define VEC_DAC_CC_S16_SCALE_BURST_BITS 0xffff0000
2823 +#define VEC_DAC_CC_S16_SCALE_BURST_MSB 31
2824 +#define VEC_DAC_CC_S16_SCALE_BURST_LSB 16
2825 +#define VEC_DAC_CC_S16_SCALE_BURST_ACCESS "RW"
2826 +// -----------------------------------------------------------------------------
2827 +// Field : VEC_DAC_CC_S16_SCALE_CHROMA
2828 +// Description : Scaling applied prior to final summation to form the DAC
2829 +// command word(s)
2830 +#define VEC_DAC_CC_S16_SCALE_CHROMA_RESET 0x0000
2831 +#define VEC_DAC_CC_S16_SCALE_CHROMA_BITS 0x0000ffff
2832 +#define VEC_DAC_CC_S16_SCALE_CHROMA_MSB 15
2833 +#define VEC_DAC_CC_S16_SCALE_CHROMA_LSB 0
2834 +#define VEC_DAC_CC_S16_SCALE_CHROMA_ACCESS "RW"
2835 +// =============================================================================
2836 +// Register : VEC_DAC_D0
2837 +// JTAG access : synchronous
2838 +// Description : None
2839 +#define VEC_DAC_D0_OFFSET 0x000000d0
2840 +#define VEC_DAC_D0_BITS 0xffffffff
2841 +#define VEC_DAC_D0_RESET 0x00000000
2842 +// -----------------------------------------------------------------------------
2843 +// Field : VEC_DAC_D0_S16_OFFSET_LUMA
2844 +// Description : These offsets are applied to the chroma and luma channels
2845 +// before the final MUX
2846 +#define VEC_DAC_D0_S16_OFFSET_LUMA_RESET 0x0000
2847 +#define VEC_DAC_D0_S16_OFFSET_LUMA_BITS 0xffff0000
2848 +#define VEC_DAC_D0_S16_OFFSET_LUMA_MSB 31
2849 +#define VEC_DAC_D0_S16_OFFSET_LUMA_LSB 16
2850 +#define VEC_DAC_D0_S16_OFFSET_LUMA_ACCESS "RW"
2851 +// -----------------------------------------------------------------------------
2852 +// Field : VEC_DAC_D0_S16_OFFSET_CHRO
2853 +// Description : These offsets are applied to the chroma and luma channels
2854 +// before the final MUX
2855 +#define VEC_DAC_D0_S16_OFFSET_CHRO_RESET 0x0000
2856 +#define VEC_DAC_D0_S16_OFFSET_CHRO_BITS 0x0000ffff
2857 +#define VEC_DAC_D0_S16_OFFSET_CHRO_MSB 15
2858 +#define VEC_DAC_D0_S16_OFFSET_CHRO_LSB 0
2859 +#define VEC_DAC_D0_S16_OFFSET_CHRO_ACCESS "RW"
2860 +// =============================================================================
2861 +// Register : VEC_DAC_D4
2862 +// JTAG access : synchronous
2863 +// Description : None
2864 +#define VEC_DAC_D4_OFFSET 0x000000d4
2865 +#define VEC_DAC_D4_BITS 0xffffffff
2866 +#define VEC_DAC_D4_RESET 0x00000000
2867 +// -----------------------------------------------------------------------------
2868 +// Field : VEC_DAC_D4_NCO_FREQ
2869 +// Description : This 64-bit frequency command is applied to the phase
2870 +// accumulator of the NCO (numerically controlled oscillator)
2871 +// which generates the colour sub-carrier. This value is computed
2872 +// as ratio of sub-carrier frequency to DAC clock multiplied by
2873 +// 2^64.
2874 +#define VEC_DAC_D4_NCO_FREQ_RESET 0x00000000
2875 +#define VEC_DAC_D4_NCO_FREQ_BITS 0xffffffff
2876 +#define VEC_DAC_D4_NCO_FREQ_MSB 31
2877 +#define VEC_DAC_D4_NCO_FREQ_LSB 0
2878 +#define VEC_DAC_D4_NCO_FREQ_ACCESS "RW"
2879 +// =============================================================================
2880 +// Register : VEC_DAC_D8
2881 +// JTAG access : synchronous
2882 +// Description : None
2883 +#define VEC_DAC_D8_OFFSET 0x000000d8
2884 +#define VEC_DAC_D8_BITS 0xffffffff
2885 +#define VEC_DAC_D8_RESET 0x00000000
2886 +// -----------------------------------------------------------------------------
2887 +// Field : VEC_DAC_D8_NCO_FREQ
2888 +// Description : This 64-bit frequency command is applied to the phase
2889 +// accumulator of the NCO (numerically controlled oscillator)
2890 +// which generates the colour sub-carrier. This value is computed
2891 +// as ratio of sub-carrier frequency to DAC clock multiplied by
2892 +// 2^64.
2893 +#define VEC_DAC_D8_NCO_FREQ_RESET 0x00000000
2894 +#define VEC_DAC_D8_NCO_FREQ_BITS 0xffffffff
2895 +#define VEC_DAC_D8_NCO_FREQ_MSB 31
2896 +#define VEC_DAC_D8_NCO_FREQ_LSB 0
2897 +#define VEC_DAC_D8_NCO_FREQ_ACCESS "RW"
2898 +// =============================================================================
2899 +// Register : VEC_DAC_DC
2900 +// JTAG access : synchronous
2901 +// Description : None
2902 +#define VEC_DAC_DC_OFFSET 0x000000dc
2903 +#define VEC_DAC_DC_BITS 0xffffffff
2904 +#define VEC_DAC_DC_RESET 0x00000000
2905 +// -----------------------------------------------------------------------------
2906 +// Field : VEC_DAC_DC_FIR_COEFF_CHROMA_0_6
2907 +// Description : FIR filter coefficients
2908 +#define VEC_DAC_DC_FIR_COEFF_CHROMA_0_6_RESET 0x0000
2909 +#define VEC_DAC_DC_FIR_COEFF_CHROMA_0_6_BITS 0xffff0000
2910 +#define VEC_DAC_DC_FIR_COEFF_CHROMA_0_6_MSB 31
2911 +#define VEC_DAC_DC_FIR_COEFF_CHROMA_0_6_LSB 16
2912 +#define VEC_DAC_DC_FIR_COEFF_CHROMA_0_6_ACCESS "RW"
2913 +// -----------------------------------------------------------------------------
2914 +// Field : VEC_DAC_DC_FIR_COEFF_LUMA_0_6
2915 +// Description : FIR filter coefficients
2916 +#define VEC_DAC_DC_FIR_COEFF_LUMA_0_6_RESET 0x0000
2917 +#define VEC_DAC_DC_FIR_COEFF_LUMA_0_6_BITS 0x0000ffff
2918 +#define VEC_DAC_DC_FIR_COEFF_LUMA_0_6_MSB 15
2919 +#define VEC_DAC_DC_FIR_COEFF_LUMA_0_6_LSB 0
2920 +#define VEC_DAC_DC_FIR_COEFF_LUMA_0_6_ACCESS "RW"
2921 +// =============================================================================
2922 +// Register : VEC_DAC_E0
2923 +// JTAG access : synchronous
2924 +// Description : None
2925 +#define VEC_DAC_E0_OFFSET 0x000000e0
2926 +#define VEC_DAC_E0_BITS 0xffffffff
2927 +#define VEC_DAC_E0_RESET 0x00000000
2928 +// -----------------------------------------------------------------------------
2929 +// Field : VEC_DAC_E0_FIR_COEFF_CHROMA_1_5
2930 +// Description : FIR filter coefficients
2931 +#define VEC_DAC_E0_FIR_COEFF_CHROMA_1_5_RESET 0x0000
2932 +#define VEC_DAC_E0_FIR_COEFF_CHROMA_1_5_BITS 0xffff0000
2933 +#define VEC_DAC_E0_FIR_COEFF_CHROMA_1_5_MSB 31
2934 +#define VEC_DAC_E0_FIR_COEFF_CHROMA_1_5_LSB 16
2935 +#define VEC_DAC_E0_FIR_COEFF_CHROMA_1_5_ACCESS "RW"
2936 +// -----------------------------------------------------------------------------
2937 +// Field : VEC_DAC_E0_FIR_COEFF_LUMA_1_5
2938 +// Description : FIR filter coefficients
2939 +#define VEC_DAC_E0_FIR_COEFF_LUMA_1_5_RESET 0x0000
2940 +#define VEC_DAC_E0_FIR_COEFF_LUMA_1_5_BITS 0x0000ffff
2941 +#define VEC_DAC_E0_FIR_COEFF_LUMA_1_5_MSB 15
2942 +#define VEC_DAC_E0_FIR_COEFF_LUMA_1_5_LSB 0
2943 +#define VEC_DAC_E0_FIR_COEFF_LUMA_1_5_ACCESS "RW"
2944 +// =============================================================================
2945 +// Register : VEC_DAC_E4
2946 +// JTAG access : synchronous
2947 +// Description : None
2948 +#define VEC_DAC_E4_OFFSET 0x000000e4
2949 +#define VEC_DAC_E4_BITS 0xffffffff
2950 +#define VEC_DAC_E4_RESET 0x00000000
2951 +// -----------------------------------------------------------------------------
2952 +// Field : VEC_DAC_E4_FIR_COEFF_CHROMA_2_4
2953 +// Description : FIR filter coefficients
2954 +#define VEC_DAC_E4_FIR_COEFF_CHROMA_2_4_RESET 0x0000
2955 +#define VEC_DAC_E4_FIR_COEFF_CHROMA_2_4_BITS 0xffff0000
2956 +#define VEC_DAC_E4_FIR_COEFF_CHROMA_2_4_MSB 31
2957 +#define VEC_DAC_E4_FIR_COEFF_CHROMA_2_4_LSB 16
2958 +#define VEC_DAC_E4_FIR_COEFF_CHROMA_2_4_ACCESS "RW"
2959 +// -----------------------------------------------------------------------------
2960 +// Field : VEC_DAC_E4_FIR_COEFF_LUMA_2_4
2961 +// Description : FIR filter coefficients
2962 +#define VEC_DAC_E4_FIR_COEFF_LUMA_2_4_RESET 0x0000
2963 +#define VEC_DAC_E4_FIR_COEFF_LUMA_2_4_BITS 0x0000ffff
2964 +#define VEC_DAC_E4_FIR_COEFF_LUMA_2_4_MSB 15
2965 +#define VEC_DAC_E4_FIR_COEFF_LUMA_2_4_LSB 0
2966 +#define VEC_DAC_E4_FIR_COEFF_LUMA_2_4_ACCESS "RW"
2967 +// =============================================================================
2968 +// Register : VEC_DAC_E8
2969 +// JTAG access : synchronous
2970 +// Description : None
2971 +#define VEC_DAC_E8_OFFSET 0x000000e8
2972 +#define VEC_DAC_E8_BITS 0xffffffff
2973 +#define VEC_DAC_E8_RESET 0x00000000
2974 +// -----------------------------------------------------------------------------
2975 +// Field : VEC_DAC_E8_FIR_COEFF_CHROMA_3
2976 +// Description : FIR filter coefficients
2977 +#define VEC_DAC_E8_FIR_COEFF_CHROMA_3_RESET 0x0000
2978 +#define VEC_DAC_E8_FIR_COEFF_CHROMA_3_BITS 0xffff0000
2979 +#define VEC_DAC_E8_FIR_COEFF_CHROMA_3_MSB 31
2980 +#define VEC_DAC_E8_FIR_COEFF_CHROMA_3_LSB 16
2981 +#define VEC_DAC_E8_FIR_COEFF_CHROMA_3_ACCESS "RW"
2982 +// -----------------------------------------------------------------------------
2983 +// Field : VEC_DAC_E8_FIR_COEFF_LUMA_3
2984 +// Description : FIR filter coefficients
2985 +#define VEC_DAC_E8_FIR_COEFF_LUMA_3_RESET 0x0000
2986 +#define VEC_DAC_E8_FIR_COEFF_LUMA_3_BITS 0x0000ffff
2987 +#define VEC_DAC_E8_FIR_COEFF_LUMA_3_MSB 15
2988 +#define VEC_DAC_E8_FIR_COEFF_LUMA_3_LSB 0
2989 +#define VEC_DAC_E8_FIR_COEFF_LUMA_3_ACCESS "RW"
2990 +// =============================================================================
2991 +// Register : VEC_DAC_EC
2992 +// JTAG access : synchronous
2993 +// Description : Misc. control
2994 +#define VEC_DAC_EC_OFFSET 0x000000ec
2995 +#define VEC_DAC_EC_BITS 0x001fffff
2996 +#define VEC_DAC_EC_RESET 0x00000000
2997 +// -----------------------------------------------------------------------------
2998 +// Field : VEC_DAC_EC_SLOW_CLOCK
2999 +// Description : Doubles the raised-cosine rate
3000 +#define VEC_DAC_EC_SLOW_CLOCK_RESET 0x0
3001 +#define VEC_DAC_EC_SLOW_CLOCK_BITS 0x00100000
3002 +#define VEC_DAC_EC_SLOW_CLOCK_MSB 20
3003 +#define VEC_DAC_EC_SLOW_CLOCK_LSB 20
3004 +#define VEC_DAC_EC_SLOW_CLOCK_ACCESS "RW"
3005 +// -----------------------------------------------------------------------------
3006 +// Field : VEC_DAC_EC_FIR_RMINUS1
3007 +// Description : Select 1, 3, 5 or 7 FIR taps
3008 +#define VEC_DAC_EC_FIR_RMINUS1_RESET 0x0
3009 +#define VEC_DAC_EC_FIR_RMINUS1_BITS 0x000c0000
3010 +#define VEC_DAC_EC_FIR_RMINUS1_MSB 19
3011 +#define VEC_DAC_EC_FIR_RMINUS1_LSB 18
3012 +#define VEC_DAC_EC_FIR_RMINUS1_ACCESS "RW"
3013 +// -----------------------------------------------------------------------------
3014 +// Field : VEC_DAC_EC_VERT_FULL_NOT_HALF
3015 +// Description : Disable half-line pulses during VBI
3016 +#define VEC_DAC_EC_VERT_FULL_NOT_HALF_RESET 0x0
3017 +#define VEC_DAC_EC_VERT_FULL_NOT_HALF_BITS 0x00020000
3018 +#define VEC_DAC_EC_VERT_FULL_NOT_HALF_MSB 17
3019 +#define VEC_DAC_EC_VERT_FULL_NOT_HALF_LSB 17
3020 +#define VEC_DAC_EC_VERT_FULL_NOT_HALF_ACCESS "RW"
3021 +// -----------------------------------------------------------------------------
3022 +// Field : VEC_DAC_EC_SEQ_EN
3023 +// Description : Enable NCO reset
3024 +#define VEC_DAC_EC_SEQ_EN_RESET 0x0
3025 +#define VEC_DAC_EC_SEQ_EN_BITS 0x00010000
3026 +#define VEC_DAC_EC_SEQ_EN_MSB 16
3027 +#define VEC_DAC_EC_SEQ_EN_LSB 16
3028 +#define VEC_DAC_EC_SEQ_EN_ACCESS "RW"
3029 +// -----------------------------------------------------------------------------
3030 +// Field : VEC_DAC_EC_U2_FLD_MASK
3031 +// Description : Field sequence
3032 +#define VEC_DAC_EC_U2_FLD_MASK_RESET 0x0
3033 +#define VEC_DAC_EC_U2_FLD_MASK_BITS 0x0000c000
3034 +#define VEC_DAC_EC_U2_FLD_MASK_MSB 15
3035 +#define VEC_DAC_EC_U2_FLD_MASK_LSB 14
3036 +#define VEC_DAC_EC_U2_FLD_MASK_ACCESS "RW"
3037 +// -----------------------------------------------------------------------------
3038 +// Field : VEC_DAC_EC_U4_SEQ_MASK
3039 +// Description : NCO reset sequence
3040 +#define VEC_DAC_EC_U4_SEQ_MASK_RESET 0x0
3041 +#define VEC_DAC_EC_U4_SEQ_MASK_BITS 0x00003c00
3042 +#define VEC_DAC_EC_U4_SEQ_MASK_MSB 13
3043 +#define VEC_DAC_EC_U4_SEQ_MASK_LSB 10
3044 +#define VEC_DAC_EC_U4_SEQ_MASK_ACCESS "RW"
3045 +// -----------------------------------------------------------------------------
3046 +// Field : VEC_DAC_EC_INTERP_RATE_MINUS1
3047 +// Description : Interpolation rate 2<=R<=16
3048 +#define VEC_DAC_EC_INTERP_RATE_MINUS1_RESET 0x0
3049 +#define VEC_DAC_EC_INTERP_RATE_MINUS1_BITS 0x000003c0
3050 +#define VEC_DAC_EC_INTERP_RATE_MINUS1_MSB 9
3051 +#define VEC_DAC_EC_INTERP_RATE_MINUS1_LSB 6
3052 +#define VEC_DAC_EC_INTERP_RATE_MINUS1_ACCESS "RW"
3053 +// -----------------------------------------------------------------------------
3054 +// Field : VEC_DAC_EC_INTERP_SHIFT_MINUS1
3055 +// Description : Power-of-2 scaling after interpolation
3056 +#define VEC_DAC_EC_INTERP_SHIFT_MINUS1_RESET 0x0
3057 +#define VEC_DAC_EC_INTERP_SHIFT_MINUS1_BITS 0x0000003c
3058 +#define VEC_DAC_EC_INTERP_SHIFT_MINUS1_MSB 5
3059 +#define VEC_DAC_EC_INTERP_SHIFT_MINUS1_LSB 2
3060 +#define VEC_DAC_EC_INTERP_SHIFT_MINUS1_ACCESS "RW"
3061 +// -----------------------------------------------------------------------------
3062 +// Field : VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1
3063 +// Description : Interlaced / progressive
3064 +#define VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1_RESET 0x0
3065 +#define VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1_BITS 0x00000002
3066 +#define VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1_MSB 1
3067 +#define VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1_LSB 1
3068 +#define VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1_ACCESS "RW"
3069 +// -----------------------------------------------------------------------------
3070 +// Field : VEC_DAC_EC_PAL_EN
3071 +// Description : Enable phase alternate line (PAL) mode
3072 +#define VEC_DAC_EC_PAL_EN_RESET 0x0
3073 +#define VEC_DAC_EC_PAL_EN_BITS 0x00000001
3074 +#define VEC_DAC_EC_PAL_EN_MSB 0
3075 +#define VEC_DAC_EC_PAL_EN_LSB 0
3076 +#define VEC_DAC_EC_PAL_EN_ACCESS "RW"
3077 +// =============================================================================
3078 +#endif // VEC_REGS_DEFINED
Staging tree of Daniel Golle