target/linux/bcm27xx/patches-6.1/950-0884-pwm-Add-support-for-RP1-PWM.patch

   1 From 824f18efc8ad59e2783570ae2df83e2cd16b9f04 Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.com>
   3 Date: Tue, 14 Feb 2023 14:03:54 +0000
   4 Subject: [PATCH] pwm: Add support for RP1 PWM
   5
   6 Add a driver for the RP1 PWM block.
   7
   8 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
   9 ---
  10  .../devicetree/bindings/pwm/pwm-rp1.yaml      |  38 ++++
  11  drivers/pwm/Kconfig                           |   9 +
  12  drivers/pwm/Makefile                          |   1 +
  13  drivers/pwm/pwm-rp1.c                         | 203 ++++++++++++++++++
  14  4 files changed, 251 insertions(+)
  15  create mode 100644 Documentation/devicetree/bindings/pwm/pwm-rp1.yaml
  16  create mode 100644 drivers/pwm/pwm-rp1.c
  17
  18 --- /dev/null
  19 +++ b/Documentation/devicetree/bindings/pwm/pwm-rp1.yaml
  20 @@ -0,0 +1,38 @@
  21 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  22 +%YAML 1.2
  23 +---
  24 +$id: http://devicetree.org/schemas/pwm/pwm-rp1.yaml#
  25 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  26 +
  27 +title: Raspberry Pi RP1 PWM controller
  28 +
  29 +maintainers:
  30 +  - Naushir Patuck <naush@raspberrypi.com>
  31 +
  32 +properties:
  33 +  compatible:
  34 +    enum:
  35 +      - raspberrypi,rp1-pwm
  36 +
  37 +  reg:
  38 +    maxItems: 1
  39 +
  40 +  "#pwm-cells":
  41 +    const: 3
  42 +
  43 +required:
  44 +  - compatible
  45 +  - reg
  46 +  - clocks
  47 +  - "#pwm-cells"
  48 +
  49 +additionalProperties: false
  50 +
  51 +examples:
  52 +  - |
  53 +    pwm0: pwm@98000 {
  54 +      compatible = "raspberrypi,rp1-pwm";
  55 +      reg = <0x0 0x98000  0x0 0x100>;
  56 +      clocks = <&rp1_sys>;
  57 +      #pwm-cells = <3>;
  58 +    };
  59 --- a/drivers/pwm/Kconfig
  60 +++ b/drivers/pwm/Kconfig
  61 @@ -451,6 +451,15 @@ config PWM_RASPBERRYPI_POE
  62           Enable Raspberry Pi firmware controller PWM bus used to control the
  63           official RPI PoE hat
  64
  65 +config PWM_RP1
  66 +       tristate "RP1 PWM support"
  67 +       depends on ARCH_BCM2835 || COMPILE_TEST
  68 +       help
  69 +         PWM framework driver for Raspberry Pi RP1 controller
  70 +
  71 +         To compile this driver as a module, choose M here: the module
  72 +         will be called pwm-rp1.
  73 +
  74  config PWM_RCAR
  75         tristate "Renesas R-Car PWM support"
  76         depends on ARCH_RENESAS || COMPILE_TEST
  77 --- a/drivers/pwm/Makefile
  78 +++ b/drivers/pwm/Makefile
  79 @@ -41,6 +41,7 @@ obj-$(CONFIG_PWM_OMAP_DMTIMER)        += pwm-om
  80  obj-$(CONFIG_PWM_PCA9685)      += pwm-pca9685.o
  81  obj-$(CONFIG_PWM_PXA)          += pwm-pxa.o
  82  obj-$(CONFIG_PWM_RASPBERRYPI_POE)      += pwm-raspberrypi-poe.o
  83 +obj-$(CONFIG_PWM_RP1)          += pwm-rp1.o
  84  obj-$(CONFIG_PWM_RCAR)         += pwm-rcar.o
  85  obj-$(CONFIG_PWM_RENESAS_TPU)  += pwm-renesas-tpu.o
  86  obj-$(CONFIG_PWM_ROCKCHIP)     += pwm-rockchip.o
  87 --- /dev/null
  88 +++ b/drivers/pwm/pwm-rp1.c
  89 @@ -0,0 +1,203 @@
  90 +// SPDX-License-Identifier: GPL-2.0
  91 +/*
  92 + * pwm-rp1.c
  93 + *
  94 + * Raspberry Pi RP1 PWM.
  95 + *
  96 + * Copyright © 2023 Raspberry Pi Ltd.
  97 + *
  98 + * Author: Naushir Patuck (naush@raspberrypi.com)
  99 + *
 100 + * Based on the pwm-bcm2835 driver by:
 101 + * Bart Tanghe <bart.tanghe@thomasmore.be>
 102 + */
 103 +
 104 +#include <linux/bitops.h>
 105 +#include <linux/clk.h>
 106 +#include <linux/err.h>
 107 +#include <linux/io.h>
 108 +#include <linux/module.h>
 109 +#include <linux/of.h>
 110 +#include <linux/platform_device.h>
 111 +#include <linux/pwm.h>
 112 +
 113 +#define PWM_GLOBAL_CTRL                0x000
 114 +#define PWM_CHANNEL_CTRL(x)    (0x014 + ((x) * 16))
 115 +#define PWM_RANGE(x)           (0x018 + ((x) * 16))
 116 +#define PWM_DUTY(x)            (0x020 + ((x) * 16))
 117 +
 118 +/* 8:FIFO_POP_MASK + 0:Trailing edge M/S modulation */
 119 +#define PWM_CHANNEL_DEFAULT    (BIT(8) + BIT(0))
 120 +#define PWM_CHANNEL_ENABLE(x)  BIT(x)
 121 +#define PWM_POLARITY           BIT(3)
 122 +#define SET_UPDATE             BIT(31)
 123 +#define PWM_MODE_MASK          GENMASK(1, 0)
 124 +
 125 +struct rp1_pwm {
 126 +       struct pwm_chip chip;
 127 +       struct device *dev;
 128 +       void __iomem *base;
 129 +       struct clk *clk;
 130 +};
 131 +
 132 +static inline struct rp1_pwm *to_rp1_pwm(struct pwm_chip *chip)
 133 +{
 134 +       return container_of(chip, struct rp1_pwm, chip);
 135 +}
 136 +
 137 +static void rp1_pwm_apply_config(struct pwm_chip *chip, struct pwm_device *pwm)
 138 +{
 139 +       struct rp1_pwm *pc = to_rp1_pwm(chip);
 140 +       u32 value;
 141 +
 142 +       value = readl(pc->base + PWM_GLOBAL_CTRL);
 143 +       value |= SET_UPDATE;
 144 +       writel(value, pc->base + PWM_GLOBAL_CTRL);
 145 +}
 146 +
 147 +static int rp1_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
 148 +{
 149 +       struct rp1_pwm *pc = to_rp1_pwm(chip);
 150 +
 151 +       writel(PWM_CHANNEL_DEFAULT, pc->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
 152 +       return 0;
 153 +}
 154 +
 155 +static void rp1_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 156 +{
 157 +       struct rp1_pwm *pc = to_rp1_pwm(chip);
 158 +       u32 value;
 159 +
 160 +       value = readl(pc->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
 161 +       value &= ~PWM_MODE_MASK;
 162 +       writel(value, pc->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
 163 +       rp1_pwm_apply_config(chip, pwm);
 164 +}
 165 +
 166 +static int rp1_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 167 +                        const struct pwm_state *state)
 168 +{
 169 +       struct rp1_pwm *pc = to_rp1_pwm(chip);
 170 +       unsigned long clk_rate = clk_get_rate(pc->clk);
 171 +       unsigned long clk_period;
 172 +       u32 value;
 173 +
 174 +       if (!clk_rate) {
 175 +               dev_err(pc->dev, "failed to get clock rate\n");
 176 +               return -EINVAL;
 177 +       }
 178 +
 179 +       /* set period */
 180 +       clk_period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, clk_rate);
 181 +
 182 +       writel(DIV_ROUND_CLOSEST(state->duty_cycle, clk_period),
 183 +              pc->base + PWM_DUTY(pwm->hwpwm));
 184 +
 185 +       /* set duty cycle */
 186 +       writel(DIV_ROUND_CLOSEST(state->period, clk_period),
 187 +              pc->base + PWM_RANGE(pwm->hwpwm));
 188 +
 189 +       /* set polarity */
 190 +       value = readl(pc->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
 191 +       if (state->polarity == PWM_POLARITY_NORMAL)
 192 +               value &= ~PWM_POLARITY;
 193 +       else
 194 +               value |= PWM_POLARITY;
 195 +       writel(value, pc->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
 196 +
 197 +       /* enable/disable */
 198 +       value = readl(pc->base + PWM_GLOBAL_CTRL);
 199 +       if (state->enabled)
 200 +               value |= PWM_CHANNEL_ENABLE(pwm->hwpwm);
 201 +       else
 202 +               value &= ~PWM_CHANNEL_ENABLE(pwm->hwpwm);
 203 +       writel(value, pc->base + PWM_GLOBAL_CTRL);
 204 +
 205 +       rp1_pwm_apply_config(chip, pwm);
 206 +
 207 +       return 0;
 208 +}
 209 +
 210 +static const struct pwm_ops rp1_pwm_ops = {
 211 +       .request = rp1_pwm_request,
 212 +       .free = rp1_pwm_free,
 213 +       .apply = rp1_pwm_apply,
 214 +       .owner = THIS_MODULE,
 215 +};
 216 +
 217 +static int rp1_pwm_probe(struct platform_device *pdev)
 218 +{
 219 +       struct rp1_pwm *pc;
 220 +       struct resource *res;
 221 +       int ret;
 222 +
 223 +       pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 224 +       if (!pc)
 225 +               return -ENOMEM;
 226 +
 227 +       pc->dev = &pdev->dev;
 228 +
 229 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 230 +       pc->base = devm_ioremap_resource(&pdev->dev, res);
 231 +       if (IS_ERR(pc->base))
 232 +               return PTR_ERR(pc->base);
 233 +
 234 +       pc->clk = devm_clk_get(&pdev->dev, NULL);
 235 +       if (IS_ERR(pc->clk))
 236 +               return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
 237 +                                    "clock not found\n");
 238 +
 239 +       ret = clk_prepare_enable(pc->clk);
 240 +       if (ret)
 241 +               return ret;
 242 +
 243 +       pc->chip.dev = &pdev->dev;
 244 +       pc->chip.ops = &rp1_pwm_ops;
 245 +       pc->chip.base = -1;
 246 +       pc->chip.npwm = 4;
 247 +       pc->chip.of_xlate = of_pwm_xlate_with_flags;
 248 +       pc->chip.of_pwm_n_cells = 3;
 249 +
 250 +       platform_set_drvdata(pdev, pc);
 251 +
 252 +       ret = pwmchip_add(&pc->chip);
 253 +       if (ret < 0)
 254 +               goto add_fail;
 255 +
 256 +       return 0;
 257 +
 258 +add_fail:
 259 +       clk_disable_unprepare(pc->clk);
 260 +       return ret;
 261 +}
 262 +
 263 +static int rp1_pwm_remove(struct platform_device *pdev)
 264 +{
 265 +       struct rp1_pwm *pc = platform_get_drvdata(pdev);
 266 +
 267 +       clk_disable_unprepare(pc->clk);
 268 +
 269 +       pwmchip_remove(&pc->chip);
 270 +
 271 +       return 0;
 272 +}
 273 +
 274 +static const struct of_device_id rp1_pwm_of_match[] = {
 275 +       { .compatible = "raspberrypi,rp1-pwm" },
 276 +       { /* sentinel */ }
 277 +};
 278 +MODULE_DEVICE_TABLE(of, rp1_pwm_of_match);
 279 +
 280 +static struct platform_driver rp1_pwm_driver = {
 281 +       .driver = {
 282 +               .name = "rpi-pwm",
 283 +               .of_match_table = rp1_pwm_of_match,
 284 +       },
 285 +       .probe = rp1_pwm_probe,
 286 +       .remove = rp1_pwm_remove,
 287 +};
 288 +module_platform_driver(rp1_pwm_driver);
 289 +
 290 +MODULE_AUTHOR("Naushir Patuck <naush@raspberrypi.com");
 291 +MODULE_DESCRIPTION("RP1 PWM driver");
 292 +MODULE_LICENSE("GPL");