target/linux/bcm27xx/patches-6.1/950-0880-clk-rp1-Add-sdio-clk-driver.patch

   1 From b427cc1a83404f48b12dec2efbef076b38df6218 Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.com>
   3 Date: Wed, 12 Oct 2022 14:20:07 +0100
   4 Subject: [PATCH] clk: rp1: Add sdio-clk driver
   5
   6 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
   7 ---
   8  drivers/clk/Kconfig        |   6 +
   9  drivers/clk/Makefile       |   1 +
  10  drivers/clk/clk-rp1-sdio.c | 600 +++++++++++++++++++++++++++++++++++++
  11  3 files changed, 607 insertions(+)
  12  create mode 100644 drivers/clk/clk-rp1-sdio.c
  13
  14 --- a/drivers/clk/Kconfig
  15 +++ b/drivers/clk/Kconfig
  16 @@ -96,6 +96,12 @@ config COMMON_CLK_RP1
  17         help
  18           Enable common clock framework support for Raspberry Pi RP1
  19
  20 +config COMMON_CLK_RP1_SDIO
  21 +       tristate "Clock driver for the RP1 SDIO interfaces"
  22 +       depends on MFD_RP1
  23 +       help
  24 +         SDIO clock driver for the RP1 support chip
  25 +
  26  config COMMON_CLK_HI655X
  27         tristate "Clock driver for Hi655x" if EXPERT
  28         depends on (MFD_HI655X_PMIC || COMPILE_TEST)
  29 --- a/drivers/clk/Makefile
  30 +++ b/drivers/clk/Makefile
  31 @@ -59,6 +59,7 @@ obj-$(CONFIG_COMMON_CLK_PWM)          += clk-pwm
  32  obj-$(CONFIG_CLK_QORIQ)                        += clk-qoriq.o
  33  obj-$(CONFIG_COMMON_CLK_RK808)         += clk-rk808.o
  34  obj-$(CONFIG_COMMON_CLK_RP1)           += clk-rp1.o
  35 +obj-$(CONFIG_COMMON_CLK_RP1_SDIO)      += clk-rp1-sdio.o
  36  obj-$(CONFIG_COMMON_CLK_HI655X)                += clk-hi655x.o
  37  obj-$(CONFIG_COMMON_CLK_S2MPS11)       += clk-s2mps11.o
  38  obj-$(CONFIG_COMMON_CLK_SCMI)           += clk-scmi.o
  39 --- /dev/null
  40 +++ b/drivers/clk/clk-rp1-sdio.c
  41 @@ -0,0 +1,600 @@
  42 +// SPDX-License-Identifier: GPL-2.0-or-later
  43 +/*
  44 + * SDIO clock driver for RP1
  45 + *
  46 + * Copyright (C) 2023 Raspberry Pi Ltd.
  47 + */
  48 +
  49 +#include <linux/io.h>
  50 +#include <linux/clk.h>
  51 +#include <linux/clk-provider.h>
  52 +#include <linux/module.h>
  53 +#include <linux/platform_device.h>
  54 +
  55 +// Register    : MODE
  56 +#define MODE        0x00000000
  57 +#define MODE_BITS   0x70030000
  58 +#define MODE_RESET  0x00000000
  59 +// Field       : MODE_STEPS_PER_CYCLE
  60 +#define MODE_STEPS_PER_CYCLE_RESET          0x0
  61 +#define MODE_STEPS_PER_CYCLE_BITS           0x70000000
  62 +#define MODE_STEPS_PER_CYCLE_MSB            30
  63 +#define MODE_STEPS_PER_CYCLE_LSB            28
  64 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_20 0x0
  65 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_10 0x1
  66 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_16 0x2
  67 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_8  0x3
  68 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_12 0x4
  69 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_6  0x5
  70 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_5  0x6
  71 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_4  0x7
  72 +// Field       : MODE_SRC_SEL
  73 +#define MODE_SRC_SEL_RESET                   0x0
  74 +#define MODE_SRC_SEL_BITS                    0x00030000
  75 +#define MODE_SRC_SEL_MSB                     17
  76 +#define MODE_SRC_SEL_LSB                     16
  77 +#define MODE_SRC_SEL_VALUE_STOP              0x0
  78 +#define MODE_SRC_SEL_VALUE_CLK_ALT_SRC       0x1
  79 +#define MODE_SRC_SEL_VALUE_PLL_SYS_VCO       0x2
  80 +#define MODE_SRC_SEL_VALUE_PLL_SYS_VCO_AGAIN 0x3
  81 +// Register    : FROMIP
  82 +#define FROMIP        0x00000004
  83 +#define FROMIP_BITS   0x0f9713ff
  84 +#define FROMIP_RESET  0x00000000
  85 +// Field       : FROMIP_TUNING_CCLK_SEL
  86 +#define FROMIP_TUNING_CCLK_SEL_RESET  0x0
  87 +#define FROMIP_TUNING_CCLK_SEL_BITS   0x0f000000
  88 +#define FROMIP_TUNING_CCLK_SEL_MSB    27
  89 +#define FROMIP_TUNING_CCLK_SEL_LSB    24
  90 +// Field       : FROMIP_TUNING_CCLK_UPDATE
  91 +#define FROMIP_TUNING_CCLK_UPDATE_RESET  0x0
  92 +#define FROMIP_TUNING_CCLK_UPDATE_BITS   0x00800000
  93 +#define FROMIP_TUNING_CCLK_UPDATE_MSB    23
  94 +#define FROMIP_TUNING_CCLK_UPDATE_LSB    23
  95 +// Field       : FROMIP_SAMPLE_CCLK_SEL
  96 +#define FROMIP_SAMPLE_CCLK_SEL_RESET  0x0
  97 +#define FROMIP_SAMPLE_CCLK_SEL_BITS   0x00100000
  98 +#define FROMIP_SAMPLE_CCLK_SEL_MSB    20
  99 +#define FROMIP_SAMPLE_CCLK_SEL_LSB    20
 100 +// Field       : FROMIP_CLK2CARD_ON
 101 +#define FROMIP_CLK2CARD_ON_RESET  0x0
 102 +#define FROMIP_CLK2CARD_ON_BITS   0x00040000
 103 +#define FROMIP_CLK2CARD_ON_MSB    18
 104 +#define FROMIP_CLK2CARD_ON_LSB    18
 105 +// Field       : FROMIP_CARD_CLK_STABLE
 106 +#define FROMIP_CARD_CLK_STABLE_RESET  0x0
 107 +#define FROMIP_CARD_CLK_STABLE_BITS   0x00020000
 108 +#define FROMIP_CARD_CLK_STABLE_MSB    17
 109 +#define FROMIP_CARD_CLK_STABLE_LSB    17
 110 +// Field       : FROMIP_CARD_CLK_EN
 111 +#define FROMIP_CARD_CLK_EN_RESET  0x0
 112 +#define FROMIP_CARD_CLK_EN_BITS   0x00010000
 113 +#define FROMIP_CARD_CLK_EN_MSB    16
 114 +#define FROMIP_CARD_CLK_EN_LSB    16
 115 +// Field       : FROMIP_CLK_GEN_SEL
 116 +#define FROMIP_CLK_GEN_SEL_RESET  0x0
 117 +#define FROMIP_CLK_GEN_SEL_BITS   0x00001000
 118 +#define FROMIP_CLK_GEN_SEL_MSB    12
 119 +#define FROMIP_CLK_GEN_SEL_LSB    12
 120 +// Field       : FROMIP_FREQ_SEL
 121 +#define FROMIP_FREQ_SEL_RESET  0x000
 122 +#define FROMIP_FREQ_SEL_BITS   0x000003ff
 123 +#define FROMIP_FREQ_SEL_MSB    9
 124 +#define FROMIP_FREQ_SEL_LSB    0
 125 +// Register    : LOCAL
 126 +#define LOCAL        0x00000008
 127 +#define LOCAL_BITS   0x1f9713ff
 128 +#define LOCAL_RESET  0x00000000
 129 +// Field       : LOCAL_TUNING_CCLK_SEL
 130 +#define LOCAL_TUNING_CCLK_SEL_RESET  0x00
 131 +#define LOCAL_TUNING_CCLK_SEL_BITS   0x1f000000
 132 +#define LOCAL_TUNING_CCLK_SEL_MSB    28
 133 +#define LOCAL_TUNING_CCLK_SEL_LSB    24
 134 +// Field       : LOCAL_TUNING_CCLK_UPDATE
 135 +#define LOCAL_TUNING_CCLK_UPDATE_RESET  0x0
 136 +#define LOCAL_TUNING_CCLK_UPDATE_BITS   0x00800000
 137 +#define LOCAL_TUNING_CCLK_UPDATE_MSB    23
 138 +#define LOCAL_TUNING_CCLK_UPDATE_LSB    23
 139 +// Field       : LOCAL_SAMPLE_CCLK_SEL
 140 +#define LOCAL_SAMPLE_CCLK_SEL_RESET  0x0
 141 +#define LOCAL_SAMPLE_CCLK_SEL_BITS   0x00100000
 142 +#define LOCAL_SAMPLE_CCLK_SEL_MSB    20
 143 +#define LOCAL_SAMPLE_CCLK_SEL_LSB    20
 144 +// Field       : LOCAL_CLK2CARD_ON
 145 +#define LOCAL_CLK2CARD_ON_RESET  0x0
 146 +#define LOCAL_CLK2CARD_ON_BITS   0x00040000
 147 +#define LOCAL_CLK2CARD_ON_MSB    18
 148 +#define LOCAL_CLK2CARD_ON_LSB    18
 149 +// Field       : LOCAL_CARD_CLK_STABLE
 150 +#define LOCAL_CARD_CLK_STABLE_RESET  0x0
 151 +#define LOCAL_CARD_CLK_STABLE_BITS   0x00020000
 152 +#define LOCAL_CARD_CLK_STABLE_MSB    17
 153 +#define LOCAL_CARD_CLK_STABLE_LSB    17
 154 +// Field       : LOCAL_CARD_CLK_EN
 155 +#define LOCAL_CARD_CLK_EN_RESET  0x0
 156 +#define LOCAL_CARD_CLK_EN_BITS   0x00010000
 157 +#define LOCAL_CARD_CLK_EN_MSB    16
 158 +#define LOCAL_CARD_CLK_EN_LSB    16
 159 +// Field       : LOCAL_CLK_GEN_SEL
 160 +#define LOCAL_CLK_GEN_SEL_RESET               0x0
 161 +#define LOCAL_CLK_GEN_SEL_BITS                0x00001000
 162 +#define LOCAL_CLK_GEN_SEL_MSB                 12
 163 +#define LOCAL_CLK_GEN_SEL_LSB                 12
 164 +#define LOCAL_CLK_GEN_SEL_VALUE_PROGCLOCKMODE 0x0
 165 +#define LOCAL_CLK_GEN_SEL_VALUE_DIVCLOCKMODE  0x1
 166 +// Field       : LOCAL_FREQ_SEL
 167 +#define LOCAL_FREQ_SEL_RESET  0x000
 168 +#define LOCAL_FREQ_SEL_BITS   0x000003ff
 169 +#define LOCAL_FREQ_SEL_MSB    9
 170 +#define LOCAL_FREQ_SEL_LSB    0
 171 +// Register    : USE_LOCAL
 172 +#define USE_LOCAL        0x0000000c
 173 +#define USE_LOCAL_BITS   0x01951001
 174 +#define USE_LOCAL_RESET  0x00000000
 175 +// Field       : USE_LOCAL_TUNING_CCLK_SEL
 176 +#define USE_LOCAL_TUNING_CCLK_SEL_RESET  0x0
 177 +#define USE_LOCAL_TUNING_CCLK_SEL_BITS   0x01000000
 178 +#define USE_LOCAL_TUNING_CCLK_SEL_MSB    24
 179 +#define USE_LOCAL_TUNING_CCLK_SEL_LSB    24
 180 +// Field       : USE_LOCAL_TUNING_CCLK_UPDATE
 181 +#define USE_LOCAL_TUNING_CCLK_UPDATE_RESET  0x0
 182 +#define USE_LOCAL_TUNING_CCLK_UPDATE_BITS   0x00800000
 183 +#define USE_LOCAL_TUNING_CCLK_UPDATE_MSB    23
 184 +#define USE_LOCAL_TUNING_CCLK_UPDATE_LSB    23
 185 +// Field       : USE_LOCAL_SAMPLE_CCLK_SEL
 186 +#define USE_LOCAL_SAMPLE_CCLK_SEL_RESET  0x0
 187 +#define USE_LOCAL_SAMPLE_CCLK_SEL_BITS   0x00100000
 188 +#define USE_LOCAL_SAMPLE_CCLK_SEL_MSB    20
 189 +#define USE_LOCAL_SAMPLE_CCLK_SEL_LSB    20
 190 +// Field       : USE_LOCAL_CLK2CARD_ON
 191 +#define USE_LOCAL_CLK2CARD_ON_RESET  0x0
 192 +#define USE_LOCAL_CLK2CARD_ON_BITS   0x00040000
 193 +#define USE_LOCAL_CLK2CARD_ON_MSB    18
 194 +#define USE_LOCAL_CLK2CARD_ON_LSB    18
 195 +// Field       : USE_LOCAL_CARD_CLK_EN
 196 +#define USE_LOCAL_CARD_CLK_EN_RESET  0x0
 197 +#define USE_LOCAL_CARD_CLK_EN_BITS   0x00010000
 198 +#define USE_LOCAL_CARD_CLK_EN_MSB    16
 199 +#define USE_LOCAL_CARD_CLK_EN_LSB    16
 200 +// Field       : USE_LOCAL_CLK_GEN_SEL
 201 +#define USE_LOCAL_CLK_GEN_SEL_RESET  0x0
 202 +#define USE_LOCAL_CLK_GEN_SEL_BITS   0x00001000
 203 +#define USE_LOCAL_CLK_GEN_SEL_MSB    12
 204 +#define USE_LOCAL_CLK_GEN_SEL_LSB    12
 205 +// Field       : USE_LOCAL_FREQ_SEL
 206 +#define USE_LOCAL_FREQ_SEL_RESET  0x0
 207 +#define USE_LOCAL_FREQ_SEL_BITS   0x00000001
 208 +#define USE_LOCAL_FREQ_SEL_MSB    0
 209 +#define USE_LOCAL_FREQ_SEL_LSB    0
 210 +// Register    : SD_DELAY
 211 +#define SD_DELAY        0x00000010
 212 +#define SD_DELAY_BITS   0x0000001f
 213 +#define SD_DELAY_RESET  0x00000000
 214 +// Field       : SD_DELAY_STEPS
 215 +#define SD_DELAY_STEPS_RESET  0x00
 216 +#define SD_DELAY_STEPS_BITS   0x0000001f
 217 +#define SD_DELAY_STEPS_MSB    4
 218 +#define SD_DELAY_STEPS_LSB    0
 219 +// Register    : RX_DELAY
 220 +#define RX_DELAY        0x00000014
 221 +#define RX_DELAY_BITS   0x19f3331f
 222 +#define RX_DELAY_RESET  0x00000000
 223 +// Field       : RX_DELAY_BYPASS
 224 +#define RX_DELAY_BYPASS_RESET  0x0
 225 +#define RX_DELAY_BYPASS_BITS   0x10000000
 226 +#define RX_DELAY_BYPASS_MSB    28
 227 +#define RX_DELAY_BYPASS_LSB    28
 228 +// Field       : RX_DELAY_FAIL_ACTUAL
 229 +#define RX_DELAY_FAIL_ACTUAL_RESET  0x0
 230 +#define RX_DELAY_FAIL_ACTUAL_BITS   0x08000000
 231 +#define RX_DELAY_FAIL_ACTUAL_MSB    27
 232 +#define RX_DELAY_FAIL_ACTUAL_LSB    27
 233 +// Field       : RX_DELAY_ACTUAL
 234 +#define RX_DELAY_ACTUAL_RESET  0x00
 235 +#define RX_DELAY_ACTUAL_BITS   0x01f00000
 236 +#define RX_DELAY_ACTUAL_MSB    24
 237 +#define RX_DELAY_ACTUAL_LSB    20
 238 +// Field       : RX_DELAY_OFFSET
 239 +#define RX_DELAY_OFFSET_RESET  0x0
 240 +#define RX_DELAY_OFFSET_BITS   0x00030000
 241 +#define RX_DELAY_OFFSET_MSB    17
 242 +#define RX_DELAY_OFFSET_LSB    16
 243 +// Field       : RX_DELAY_OVERFLOW
 244 +#define RX_DELAY_OVERFLOW_RESET       0x0
 245 +#define RX_DELAY_OVERFLOW_BITS        0x00003000
 246 +#define RX_DELAY_OVERFLOW_MSB         13
 247 +#define RX_DELAY_OVERFLOW_LSB         12
 248 +#define RX_DELAY_OVERFLOW_VALUE_ALLOW 0x0
 249 +#define RX_DELAY_OVERFLOW_VALUE_CLAMP 0x1
 250 +#define RX_DELAY_OVERFLOW_VALUE_FAIL  0x2
 251 +// Field       : RX_DELAY_MAP
 252 +#define RX_DELAY_MAP_RESET         0x0
 253 +#define RX_DELAY_MAP_BITS          0x00000300
 254 +#define RX_DELAY_MAP_MSB           9
 255 +#define RX_DELAY_MAP_LSB           8
 256 +#define RX_DELAY_MAP_VALUE_DIRECT  0x0
 257 +#define RX_DELAY_MAP_VALUE         0x1
 258 +#define RX_DELAY_MAP_VALUE_STRETCH 0x2
 259 +// Field       : RX_DELAY_FIXED
 260 +#define RX_DELAY_FIXED_RESET  0x00
 261 +#define RX_DELAY_FIXED_BITS   0x0000001f
 262 +#define RX_DELAY_FIXED_MSB    4
 263 +#define RX_DELAY_FIXED_LSB    0
 264 +// Register    : NDIV
 265 +#define NDIV        0x00000018
 266 +#define NDIV_BITS   0x1fff0000
 267 +#define NDIV_RESET  0x00110000
 268 +// Field       : NDIV_DIVB
 269 +#define NDIV_DIVB_RESET  0x001
 270 +#define NDIV_DIVB_BITS   0x1ff00000
 271 +#define NDIV_DIVB_MSB    28
 272 +#define NDIV_DIVB_LSB    20
 273 +// Field       : NDIV_DIVA
 274 +#define NDIV_DIVA_RESET  0x1
 275 +#define NDIV_DIVA_BITS   0x000f0000
 276 +#define NDIV_DIVA_MSB    19
 277 +#define NDIV_DIVA_LSB    16
 278 +// Register    : CS
 279 +#define CS        0x0000001c
 280 +#define CS_BITS   0x00111101
 281 +#define CS_RESET  0x00000001
 282 +// Field       : CS_RX_DEL_UPDATED
 283 +#define CS_RX_DEL_UPDATED_RESET  0x0
 284 +#define CS_RX_DEL_UPDATED_BITS   0x00100000
 285 +#define CS_RX_DEL_UPDATED_MSB    20
 286 +#define CS_RX_DEL_UPDATED_LSB    20
 287 +// Field       : CS_RX_CLK_RUNNING
 288 +#define CS_RX_CLK_RUNNING_RESET  0x0
 289 +#define CS_RX_CLK_RUNNING_BITS   0x00010000
 290 +#define CS_RX_CLK_RUNNING_MSB    16
 291 +#define CS_RX_CLK_RUNNING_LSB    16
 292 +// Field       : CS_SD_CLK_RUNNING
 293 +#define CS_SD_CLK_RUNNING_RESET  0x0
 294 +#define CS_SD_CLK_RUNNING_BITS   0x00001000
 295 +#define CS_SD_CLK_RUNNING_MSB    12
 296 +#define CS_SD_CLK_RUNNING_LSB    12
 297 +// Field       : CS_TX_CLK_RUNNING
 298 +#define CS_TX_CLK_RUNNING_RESET  0x0
 299 +#define CS_TX_CLK_RUNNING_BITS   0x00000100
 300 +#define CS_TX_CLK_RUNNING_MSB    8
 301 +#define CS_TX_CLK_RUNNING_LSB    8
 302 +// Field       : CS_RESET
 303 +#define CS_RESET_RESET  0x1
 304 +#define CS_RESET_BITS   0x00000001
 305 +#define CS_RESET_MSB    0
 306 +#define CS_RESET_LSB    0
 307 +
 308 +#define FPGA_SRC_RATE 400000000
 309 +
 310 +/* Base number of steps to delay in relation to tx clk.
 311 + * The relationship of the 3 clocks are as follows:
 312 + * tx_clk: This clock is provided to the controller. Data is sent out
 313 + * to the pads using this clock.
 314 + * sd_clk: This clock is sent out to the card.
 315 + * rx_clk: This clock is used to sample the data coming back from the card.
 316 + * This may need to be several steps ahead of the tx_clk. The default rx delay
 317 + * is used as a base delay, and can be further adjusted by the sd host
 318 + * controller during the tuning process if using a DDR50 or faster SD card
 319 + */
 320 +/*
 321 + * PRJY-1813 - the default SD clock delay needs to be set to ~60% of the total
 322 + * number of steps to meet tISU (>6ns) and tIH (>2ns) in high-speed mode.
 323 + * On FPGA this means delay SDCLK by 5, and sample RX with a delay of 6.
 324 + */
 325 +#define DEFAULT_RX_DELAY 6
 326 +#define DEFAULT_SD_DELAY 5
 327 +
 328 +struct rp1_sdio_clkgen {
 329 +       struct device *dev;
 330 +
 331 +       /* Source clock. Either PLL VCO or fixed freq on FPGA */
 332 +       struct clk *src_clk;
 333 +       /* Desired base frequency. Max freq card can go */
 334 +       struct clk *base_clk;
 335 +
 336 +       struct clk_hw hw;
 337 +       void __iomem *regs;
 338 +
 339 +       /* Starting value of local register before changing freq */
 340 +       u32 local_base;
 341 +};
 342 +
 343 +static inline void clkgen_write(struct rp1_sdio_clkgen *clkgen, u32 reg, u32 val)
 344 +{
 345 +       dev_dbg(clkgen->dev, "%s: write reg 0x%x: 0x%x\n", __func__, reg, val);
 346 +       writel(val, clkgen->regs + reg);
 347 +}
 348 +
 349 +static inline u32 clkgen_read(struct rp1_sdio_clkgen *clkgen, u32 reg)
 350 +{
 351 +       u32 val = readl(clkgen->regs + reg);
 352 +
 353 +       dev_dbg(clkgen->dev, "%s: read reg 0x%x: 0x%x\n", __func__, reg, val);
 354 +       return val;
 355 +}
 356 +
 357 +static int get_steps(unsigned int steps)
 358 +{
 359 +       int ret = -1;
 360 +
 361 +       if (steps == 4)
 362 +               ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_4;
 363 +       else if (steps == 5)
 364 +               ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_5;
 365 +       else if (steps == 6)
 366 +               ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_6;
 367 +       else if (steps == 8)
 368 +               ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_8;
 369 +       else if (steps == 10)
 370 +               ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_10;
 371 +       else if (steps == 12)
 372 +               ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_12;
 373 +       else if (steps == 16)
 374 +               ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_16;
 375 +       else if (steps == 20)
 376 +               ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_20;
 377 +       return ret;
 378 +}
 379 +
 380 +static int rp1_sdio_clk_init(struct rp1_sdio_clkgen *clkgen)
 381 +{
 382 +       unsigned long src_rate = clk_get_rate(clkgen->src_clk);
 383 +       unsigned long base_rate = clk_get_rate(clkgen->base_clk);
 384 +       unsigned int steps = src_rate / base_rate;
 385 +       u32 reg = 0;
 386 +       int steps_value = 0;
 387 +
 388 +       dev_dbg(clkgen->dev, "init: src_rate %lu, base_rate %lu, steps %d\n",
 389 +               src_rate, base_rate, steps);
 390 +
 391 +       /* Assert reset while we set up clkgen */
 392 +       clkgen_write(clkgen, CS, CS_RESET_BITS);
 393 +
 394 +       /* Pick clock source */
 395 +       if (src_rate == FPGA_SRC_RATE) {
 396 +               /* Using ALT SRC */
 397 +               reg |= MODE_SRC_SEL_VALUE_CLK_ALT_SRC << MODE_SRC_SEL_LSB;
 398 +       } else {
 399 +               /* Assume we are using PLL SYS VCO */
 400 +               reg |= MODE_SRC_SEL_VALUE_PLL_SYS_VCO << MODE_SRC_SEL_LSB;
 401 +       }
 402 +
 403 +       /* How many delay steps are available in one cycle for this source */
 404 +       steps_value = get_steps(steps);
 405 +       if (steps_value < 0) {
 406 +               dev_err(clkgen->dev, "Invalid step value: %d\n", steps);
 407 +               return -EINVAL;
 408 +       }
 409 +       reg |= steps_value << MODE_STEPS_PER_CYCLE_LSB;
 410 +
 411 +       /* Mode register is done now*/
 412 +       clkgen_write(clkgen, MODE, reg);
 413 +
 414 +       /* Now set delay mode */
 415 +       /* Clamp value if out of range rx delay is used */
 416 +       reg = RX_DELAY_OVERFLOW_VALUE_CLAMP << RX_DELAY_OVERFLOW_LSB;
 417 +       /* SD tuning bus goes from 0x0 to 0xf but we don't necessarily have that
 418 +        * many steps available depending on the source so map 0x0 -> 0xf to one
 419 +        * cycle of rx delay
 420 +        */
 421 +       reg |= RX_DELAY_MAP_VALUE_STRETCH << RX_DELAY_MAP_LSB;
 422 +
 423 +       /* Default RX delay */
 424 +       dev_dbg(clkgen->dev, "default rx delay %d\n", DEFAULT_RX_DELAY);
 425 +       reg |= (DEFAULT_RX_DELAY & RX_DELAY_FIXED_BITS) << RX_DELAY_FIXED_LSB;
 426 +       clkgen_write(clkgen, RX_DELAY, reg);
 427 +
 428 +       /* Default SD delay */
 429 +       dev_dbg(clkgen->dev, "default sd delay %d\n", DEFAULT_SD_DELAY);
 430 +       reg = (DEFAULT_SD_DELAY & SD_DELAY_STEPS_BITS) << SD_DELAY_STEPS_LSB;
 431 +       clkgen_write(clkgen, SD_DELAY, reg);
 432 +
 433 +       /* We select freq, we turn on tx clock, we turn on sd clk,
 434 +        * we pick clock generator mode
 435 +        */
 436 +       reg = USE_LOCAL_FREQ_SEL_BITS | USE_LOCAL_CARD_CLK_EN_BITS |
 437 +             USE_LOCAL_CLK2CARD_ON_BITS | USE_LOCAL_CLK_GEN_SEL_BITS;
 438 +       clkgen_write(clkgen, USE_LOCAL, reg);
 439 +
 440 +       /* Deassert reset. Reset bit is only writable bit of CS
 441 +        * reg so fine to write a 0.
 442 +        */
 443 +       clkgen_write(clkgen, CS, 0);
 444 +
 445 +       return 0;
 446 +}
 447 +
 448 +#define RUNNING        \
 449 +       (CS_TX_CLK_RUNNING_BITS | CS_RX_CLK_RUNNING_BITS | \
 450 +        CS_SD_CLK_RUNNING_BITS)
 451 +static int rp1_sdio_clk_is_prepared(struct clk_hw *hw)
 452 +{
 453 +       struct rp1_sdio_clkgen *clkgen =
 454 +               container_of(hw, struct rp1_sdio_clkgen, hw);
 455 +       u32 status;
 456 +
 457 +       dev_dbg(clkgen->dev, "is_prepared\n");
 458 +       status = clkgen_read(clkgen, CS);
 459 +       return ((status & RUNNING) == RUNNING);
 460 +}
 461 +
 462 +/* Can define an additional divider if an sd card isn't working at full speed */
 463 +/* #define SLOWDOWN 3 */
 464 +
 465 +static unsigned long rp1_sdio_clk_get_rate(struct clk_hw *hw,
 466 +                                          unsigned long parent_rate)
 467 +{
 468 +       /* Get the current rate */
 469 +       struct rp1_sdio_clkgen *clkgen =
 470 +               container_of(hw, struct rp1_sdio_clkgen, hw);
 471 +       unsigned long actual_rate = 0;
 472 +       u32 ndiv_diva;
 473 +       u32 ndiv_divb;
 474 +       u32 tmp;
 475 +       u32 div;
 476 +
 477 +       tmp = clkgen_read(clkgen, LOCAL);
 478 +       if ((tmp & LOCAL_CLK2CARD_ON_BITS) == 0) {
 479 +               dev_dbg(clkgen->dev, "get_rate 0\n");
 480 +               return 0;
 481 +       }
 482 +
 483 +       tmp = clkgen_read(clkgen, NDIV);
 484 +       ndiv_diva = (tmp & NDIV_DIVA_BITS) >> NDIV_DIVA_LSB;
 485 +       ndiv_divb = (tmp & NDIV_DIVB_BITS) >> NDIV_DIVB_LSB;
 486 +       div = ndiv_diva * ndiv_divb;
 487 +       actual_rate = (clk_get_rate(clkgen->base_clk) / div);
 488 +
 489 +#ifdef SLOWDOWN
 490 +       actual_rate *= SLOWDOWN;
 491 +#endif
 492 +
 493 +       dev_dbg(clkgen->dev, "get_rate. ndiv_diva %d, ndiv_divb %d = %lu\n",
 494 +               ndiv_diva, ndiv_divb, actual_rate);
 495 +
 496 +       return actual_rate;
 497 +}
 498 +
 499 +static int rp1_sdio_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 500 +                                unsigned long parent_rate)
 501 +{
 502 +       struct rp1_sdio_clkgen *clkgen =
 503 +               container_of(hw, struct rp1_sdio_clkgen, hw);
 504 +       u32 div;
 505 +       u32 reg;
 506 +
 507 +       dev_dbg(clkgen->dev, "set_rate %lu\n", rate);
 508 +
 509 +       if (rate == 0) {
 510 +               /* Keep tx clock running */
 511 +               clkgen_write(clkgen, LOCAL, LOCAL_CARD_CLK_EN_BITS);
 512 +               return 0;
 513 +       }
 514 +
 515 +#ifdef SLOWDOWN
 516 +       rate /= SLOWDOWN;
 517 +#endif
 518 +
 519 +       div = (clk_get_rate(clkgen->base_clk) / rate) - 1;
 520 +       reg = LOCAL_CLK_GEN_SEL_BITS | LOCAL_CARD_CLK_EN_BITS |
 521 +             LOCAL_CLK2CARD_ON_BITS | (div << LOCAL_FREQ_SEL_LSB);
 522 +       clkgen_write(clkgen, LOCAL, reg);
 523 +
 524 +       return 0;
 525 +}
 526 +
 527 +#define MAX_NDIV (256 * 8)
 528 +static int rp1_sdio_clk_determine_rate(struct clk_hw *hw,
 529 +                                      struct clk_rate_request *req)
 530 +{
 531 +       unsigned long rate;
 532 +       struct rp1_sdio_clkgen *clkgen =
 533 +               container_of(hw, struct rp1_sdio_clkgen, hw);
 534 +       unsigned long base_rate = clk_get_rate(clkgen->base_clk);
 535 +       u32 div;
 536 +
 537 +       /* What is the actual rate I can get if I request xyz */
 538 +       if (req->rate) {
 539 +               div = min((u32)(base_rate / req->rate), (u32)MAX_NDIV);
 540 +               rate = base_rate / div;
 541 +               req->rate = rate;
 542 +               dev_dbg(clkgen->dev, "determine_rate %lu: %lu / %d = %lu\n",
 543 +                       req->rate, base_rate, div, rate);
 544 +       } else {
 545 +               rate = 0;
 546 +               dev_dbg(clkgen->dev, "determine_rate %lu: %lu\n", req->rate,
 547 +                       rate);
 548 +       }
 549 +
 550 +       return 0;
 551 +}
 552 +
 553 +static const struct clk_ops rp1_sdio_clk_ops = {
 554 +       .is_prepared    = rp1_sdio_clk_is_prepared,
 555 +       .recalc_rate    = rp1_sdio_clk_get_rate,
 556 +       .set_rate       = rp1_sdio_clk_set_rate,
 557 +       .determine_rate = rp1_sdio_clk_determine_rate,
 558 +};
 559 +
 560 +static int rp1_sdio_clk_probe(struct platform_device *pdev)
 561 +{
 562 +       struct device_node *node = pdev->dev.of_node;
 563 +       struct rp1_sdio_clkgen *clkgen;
 564 +       void __iomem *regs;
 565 +       struct clk_init_data init = {};
 566 +       int ret;
 567 +
 568 +       clkgen = devm_kzalloc(&pdev->dev, sizeof(*clkgen), GFP_KERNEL);
 569 +       if (!clkgen)
 570 +               return -ENOMEM;
 571 +       platform_set_drvdata(pdev, clkgen);
 572 +
 573 +       clkgen->dev = &pdev->dev;
 574 +
 575 +       /* Source freq */
 576 +       clkgen->src_clk = devm_clk_get(&pdev->dev, "src");
 577 +       if (IS_ERR(clkgen->src_clk)) {
 578 +               int err = PTR_ERR(clkgen->src_clk);
 579 +
 580 +               dev_err(&pdev->dev, "failed to get src clk: %d\n", err);
 581 +               return err;
 582 +       }
 583 +
 584 +       /* Desired maximum output freq (i.e. base freq) */
 585 +       clkgen->base_clk = devm_clk_get(&pdev->dev, "base");
 586 +       if (IS_ERR(clkgen->base_clk)) {
 587 +               int err = PTR_ERR(clkgen->base_clk);
 588 +
 589 +               dev_err(&pdev->dev, "failed to get base clk: %d\n", err);
 590 +               return err;
 591 +       }
 592 +
 593 +       regs = devm_platform_ioremap_resource(pdev, 0);
 594 +       if (IS_ERR(regs))
 595 +               return PTR_ERR(regs);
 596 +
 597 +       init.name = node->name;
 598 +       init.ops = &rp1_sdio_clk_ops;
 599 +       init.flags = CLK_GET_RATE_NOCACHE;
 600 +
 601 +       clkgen->hw.init = &init;
 602 +       clkgen->regs = regs;
 603 +
 604 +       dev_info(&pdev->dev, "loaded %s\n", init.name);
 605 +
 606 +       ret = devm_clk_hw_register(&pdev->dev, &clkgen->hw);
 607 +       if (ret)
 608 +               return ret;
 609 +
 610 +       ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &clkgen->hw);
 611 +       if (ret)
 612 +               return ret;
 613 +
 614 +       ret = rp1_sdio_clk_init(clkgen);
 615 +       return ret;
 616 +}
 617 +
 618 +static int rp1_sdio_clk_remove(struct platform_device *pdev)
 619 +{
 620 +       return 0;
 621 +}
 622 +
 623 +static const struct of_device_id rp1_sdio_clk_dt_ids[] = {
 624 +       { .compatible = "raspberrypi,rp1-sdio-clk", },
 625 +       { /* sentinel */ }
 626 +};
 627 +MODULE_DEVICE_TABLE(of, rp1_sdio_clk_dt_ids);
 628 +
 629 +static struct platform_driver rp1_sdio_clk_driver = {
 630 +       .probe  = rp1_sdio_clk_probe,
 631 +       .remove = rp1_sdio_clk_remove,
 632 +       .driver = {
 633 +               .name           = "rp1-sdio-clk",
 634 +               .of_match_table = rp1_sdio_clk_dt_ids,
 635 +       },
 636 +};
 637 +module_platform_driver(rp1_sdio_clk_driver);
 638 +
 639 +MODULE_AUTHOR("Liam Fraser <liam@raspberrypi.com>");
 640 +MODULE_DESCRIPTION("RP1 SDIO clock driver");
 641 +MODULE_LICENSE("GPL");