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bcm27xx: update 6.1 patches to latest version
[openwrt/staging/dangole.git] / target / linux / bcm27xx / patches-6.1 / 950-0876-pinctrl-Add-rp1-driver.patch
1 From 4d4cc5be473a7767052122a87393a83d10f9ed41 Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.com>
3 Date: Mon, 10 Oct 2022 14:21:11 +0100
4 Subject: [PATCH] pinctrl: Add rp1 driver
5
6 RP1 exposes GPIOs. Add a pinctrl driver to allow control of those.
7
8 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
9 ---
10 drivers/pinctrl/Kconfig | 7 +
11 drivers/pinctrl/Makefile | 1 +
12 drivers/pinctrl/pinctrl-rp1.c | 1571 +++++++++++++++++++++++++++++
13 include/dt-bindings/pinctrl/rp1.h | 46 -
14 4 files changed, 1579 insertions(+), 46 deletions(-)
15 create mode 100644 drivers/pinctrl/pinctrl-rp1.c
16 delete mode 100644 include/dt-bindings/pinctrl/rp1.h
17
18 --- a/drivers/pinctrl/Kconfig
19 +++ b/drivers/pinctrl/Kconfig
20 @@ -512,6 +512,13 @@ config PINCTRL_ZYNQMP
21 This driver can also be built as a module. If so, the module
22 will be called pinctrl-zynqmp.
23
24 +config PINCTRL_RP1
25 + bool "Pinctrl driver for RP1"
26 + select PINMUX
27 + select PINCONF
28 + select GENERIC_PINCONF
29 + select GPIOLIB_IRQCHIP
30 +
31 source "drivers/pinctrl/actions/Kconfig"
32 source "drivers/pinctrl/aspeed/Kconfig"
33 source "drivers/pinctrl/bcm/Kconfig"
34 --- a/drivers/pinctrl/Makefile
35 +++ b/drivers/pinctrl/Makefile
36 @@ -42,6 +42,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-p
37 obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
38 obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
39 obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
40 +obj-$(CONFIG_PINCTRL_RP1) += pinctrl-rp1.o
41 obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
42 obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
43 obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
44 --- /dev/null
45 +++ b/drivers/pinctrl/pinctrl-rp1.c
46 @@ -0,0 +1,1571 @@
47 +// SPDX-License-Identifier: GPL-2.0
48 +/*
49 + * Driver for Raspberry Pi RP1 GPIO unit (pinctrl + GPIO)
50 + *
51 + * Copyright (C) 2023 Raspberry Pi Ltd.
52 + *
53 + * This driver is inspired by:
54 + * pinctrl-bcm2835.c, please see original file for copyright information
55 + */
56 +
57 +#include <linux/bitmap.h>
58 +#include <linux/bitops.h>
59 +#include <linux/bug.h>
60 +#include <linux/delay.h>
61 +#include <linux/device.h>
62 +#include <linux/err.h>
63 +#include <linux/gpio/driver.h>
64 +#include <linux/io.h>
65 +#include <linux/irq.h>
66 +#include <linux/irqdesc.h>
67 +#include <linux/init.h>
68 +#include <linux/of_address.h>
69 +#include <linux/of.h>
70 +#include <linux/of_irq.h>
71 +#include <linux/pinctrl/consumer.h>
72 +#include <linux/pinctrl/machine.h>
73 +#include <linux/pinctrl/pinconf.h>
74 +#include <linux/pinctrl/pinctrl.h>
75 +#include <linux/pinctrl/pinmux.h>
76 +#include <linux/pinctrl/pinconf-generic.h>
77 +#include <linux/platform_device.h>
78 +#include <linux/seq_file.h>
79 +#include <linux/spinlock.h>
80 +#include <linux/types.h>
81 +#include "core.h"
82 +#include "pinconf.h"
83 +#include "pinctrl-utils.h"
84 +
85 +#define MODULE_NAME "pinctrl-rp1"
86 +#define RP1_NUM_GPIOS 54
87 +#define RP1_NUM_BANKS 3
88 +
89 +#define RP1_RW_OFFSET 0x0000
90 +#define RP1_XOR_OFFSET 0x1000
91 +#define RP1_SET_OFFSET 0x2000
92 +#define RP1_CLR_OFFSET 0x3000
93 +
94 +#define RP1_GPIO_STATUS 0x0000
95 +#define RP1_GPIO_CTRL 0x0004
96 +
97 +#define RP1_GPIO_PCIE_INTE 0x011c
98 +#define RP1_GPIO_PCIE_INTS 0x0124
99 +
100 +#define RP1_GPIO_EVENTS_SHIFT_RAW 20
101 +#define RP1_GPIO_STATUS_FALLING BIT(20)
102 +#define RP1_GPIO_STATUS_RISING BIT(21)
103 +#define RP1_GPIO_STATUS_LOW BIT(22)
104 +#define RP1_GPIO_STATUS_HIGH BIT(23)
105 +
106 +#define RP1_GPIO_EVENTS_SHIFT_FILTERED 24
107 +#define RP1_GPIO_STATUS_F_FALLING BIT(24)
108 +#define RP1_GPIO_STATUS_F_RISING BIT(25)
109 +#define RP1_GPIO_STATUS_F_LOW BIT(26)
110 +#define RP1_GPIO_STATUS_F_HIGH BIT(27)
111 +
112 +#define RP1_GPIO_CTRL_FUNCSEL_LSB 0
113 +#define RP1_GPIO_CTRL_FUNCSEL_MASK 0x0000001f
114 +#define RP1_GPIO_CTRL_OUTOVER_LSB 12
115 +#define RP1_GPIO_CTRL_OUTOVER_MASK 0x00003000
116 +#define RP1_GPIO_CTRL_OEOVER_LSB 14
117 +#define RP1_GPIO_CTRL_OEOVER_MASK 0x0000c000
118 +#define RP1_GPIO_CTRL_INOVER_LSB 16
119 +#define RP1_GPIO_CTRL_INOVER_MASK 0x00030000
120 +#define RP1_GPIO_CTRL_IRQEN_FALLING BIT(20)
121 +#define RP1_GPIO_CTRL_IRQEN_RISING BIT(21)
122 +#define RP1_GPIO_CTRL_IRQEN_LOW BIT(22)
123 +#define RP1_GPIO_CTRL_IRQEN_HIGH BIT(23)
124 +#define RP1_GPIO_CTRL_IRQEN_F_FALLING BIT(24)
125 +#define RP1_GPIO_CTRL_IRQEN_F_RISING BIT(25)
126 +#define RP1_GPIO_CTRL_IRQEN_F_LOW BIT(26)
127 +#define RP1_GPIO_CTRL_IRQEN_F_HIGH BIT(27)
128 +#define RP1_GPIO_CTRL_IRQRESET BIT(28)
129 +#define RP1_GPIO_CTRL_IRQOVER_LSB 30
130 +#define RP1_GPIO_CTRL_IRQOVER_MASK 0xc0000000
131 +
132 +#define RP1_INT_EDGE_FALLING BIT(0)
133 +#define RP1_INT_EDGE_RISING BIT(1)
134 +#define RP1_INT_LEVEL_LOW BIT(2)
135 +#define RP1_INT_LEVEL_HIGH BIT(3)
136 +#define RP1_INT_MASK 0xf
137 +
138 +#define RP1_INT_EDGE_BOTH (RP1_INT_EDGE_FALLING | \
139 + RP1_INT_EDGE_RISING)
140 +#define RP1_PUD_OFF 0
141 +#define RP1_PUD_DOWN 1
142 +#define RP1_PUD_UP 2
143 +
144 +#define RP1_FSEL_COUNT 9
145 +
146 +#define RP1_FSEL_ALT0 0x00
147 +#define RP1_FSEL_GPIO 0x05
148 +#define RP1_FSEL_NONE 0x09
149 +#define RP1_FSEL_NONE_HW 0x1f
150 +
151 +#define RP1_DIR_OUTPUT 0
152 +#define RP1_DIR_INPUT 1
153 +
154 +#define RP1_OUTOVER_PERI 0
155 +#define RP1_OUTOVER_INVPERI 1
156 +#define RP1_OUTOVER_LOW 2
157 +#define RP1_OUTOVER_HIGH 3
158 +
159 +#define RP1_OEOVER_PERI 0
160 +#define RP1_OEOVER_INVPERI 1
161 +#define RP1_OEOVER_DISABLE 2
162 +#define RP1_OEOVER_ENABLE 3
163 +
164 +#define RP1_INOVER_PERI 0
165 +#define RP1_INOVER_INVPERI 1
166 +#define RP1_INOVER_LOW 2
167 +#define RP1_INOVER_HIGH 3
168 +
169 +#define RP1_RIO_OUT 0x00
170 +#define RP1_RIO_OE 0x04
171 +#define RP1_RIO_IN 0x08
172 +
173 +#define RP1_PAD_SLEWFAST_MASK 0x00000001
174 +#define RP1_PAD_SLEWFAST_LSB 0
175 +#define RP1_PAD_SCHMITT_MASK 0x00000002
176 +#define RP1_PAD_SCHMITT_LSB 1
177 +#define RP1_PAD_PULL_MASK 0x0000000c
178 +#define RP1_PAD_PULL_LSB 2
179 +#define RP1_PAD_DRIVE_MASK 0x00000030
180 +#define RP1_PAD_DRIVE_LSB 4
181 +#define RP1_PAD_IN_ENABLE_MASK 0x00000040
182 +#define RP1_PAD_IN_ENABLE_LSB 6
183 +#define RP1_PAD_OUT_DISABLE_MASK 0x00000080
184 +#define RP1_PAD_OUT_DISABLE_LSB 7
185 +
186 +#define RP1_PAD_DRIVE_2MA 0x00000000
187 +#define RP1_PAD_DRIVE_4MA 0x00000010
188 +#define RP1_PAD_DRIVE_8MA 0x00000020
189 +#define RP1_PAD_DRIVE_12MA 0x00000030
190 +
191 +#define FLD_GET(r, f) (((r) & (f ## _MASK)) >> (f ## _LSB))
192 +#define FLD_SET(r, f, v) r = (((r) & ~(f ## _MASK)) | ((v) << (f ## _LSB)))
193 +
194 +#define FUNC(f) \
195 + [func_##f] = #f
196 +#define RP1_MAX_FSEL 8
197 +#define PIN(i, f0, f1, f2, f3, f4, f5, f6, f7, f8) \
198 + [i] = { \
199 + .funcs = { \
200 + func_##f0, \
201 + func_##f1, \
202 + func_##f2, \
203 + func_##f3, \
204 + func_##f4, \
205 + func_##f5, \
206 + func_##f6, \
207 + func_##f7, \
208 + func_##f8, \
209 + }, \
210 + }
211 +
212 +#define LEGACY_MAP(n, f0, f1, f2, f3, f4, f5) \
213 + [n] = { \
214 + func_gpio, \
215 + func_gpio, \
216 + func_##f5, \
217 + func_##f4, \
218 + func_##f0, \
219 + func_##f1, \
220 + func_##f2, \
221 + func_##f3, \
222 + }
223 +
224 +struct rp1_iobank_desc {
225 + int min_gpio;
226 + int num_gpios;
227 + int gpio_offset;
228 + int inte_offset;
229 + int ints_offset;
230 + int rio_offset;
231 + int pads_offset;
232 +};
233 +
234 +struct rp1_pin_info {
235 + u8 num;
236 + u8 bank;
237 + u8 offset;
238 + u8 fsel;
239 + u8 irq_type;
240 +
241 + void __iomem *gpio;
242 + void __iomem *rio;
243 + void __iomem *inte;
244 + void __iomem *ints;
245 + void __iomem *pad;
246 +};
247 +
248 +enum funcs {
249 + func_alt0,
250 + func_alt1,
251 + func_alt2,
252 + func_alt3,
253 + func_alt4,
254 + func_gpio,
255 + func_alt6,
256 + func_alt7,
257 + func_alt8,
258 + func_none,
259 + func_aaud,
260 + func_dcd0,
261 + func_dpi,
262 + func_dsi0_te_ext,
263 + func_dsi1_te_ext,
264 + func_dsr0,
265 + func_dtr0,
266 + func_gpclk0,
267 + func_gpclk1,
268 + func_gpclk2,
269 + func_gpclk3,
270 + func_gpclk4,
271 + func_gpclk5,
272 + func_i2c0,
273 + func_i2c1,
274 + func_i2c2,
275 + func_i2c3,
276 + func_i2c4,
277 + func_i2c5,
278 + func_i2c6,
279 + func_i2s0,
280 + func_i2s1,
281 + func_i2s2,
282 + func_ir,
283 + func_mic,
284 + func_pcie_clkreq_n,
285 + func_pio,
286 + func_proc_rio,
287 + func_pwm0,
288 + func_pwm1,
289 + func_ri0,
290 + func_sd0,
291 + func_sd1,
292 + func_spi0,
293 + func_spi1,
294 + func_spi2,
295 + func_spi3,
296 + func_spi4,
297 + func_spi5,
298 + func_spi6,
299 + func_spi7,
300 + func_spi8,
301 + func_uart0,
302 + func_uart1,
303 + func_uart2,
304 + func_uart3,
305 + func_uart4,
306 + func_uart5,
307 + func_vbus0,
308 + func_vbus1,
309 + func_vbus2,
310 + func_vbus3,
311 + func__,
312 + func_count = func__,
313 + func_invalid = func__,
314 +};
315 +
316 +struct rp1_pin_funcs {
317 + u8 funcs[RP1_FSEL_COUNT];
318 +};
319 +
320 +struct rp1_pinctrl {
321 + struct device *dev;
322 + void __iomem *gpio_base;
323 + void __iomem *rio_base;
324 + void __iomem *pads_base;
325 + int irq[RP1_NUM_BANKS];
326 + struct rp1_pin_info pins[RP1_NUM_GPIOS];
327 +
328 + struct pinctrl_dev *pctl_dev;
329 + struct gpio_chip gpio_chip;
330 + struct pinctrl_gpio_range gpio_range;
331 +
332 + raw_spinlock_t irq_lock[RP1_NUM_BANKS];
333 +};
334 +
335 +const struct rp1_iobank_desc rp1_iobanks[RP1_NUM_BANKS] = {
336 + /* gpio inte ints rio pads */
337 + { 0, 28, 0x0000, 0x011c, 0x0124, 0x0000, 0x0004 },
338 + { 28, 6, 0x4000, 0x411c, 0x4124, 0x4000, 0x4004 },
339 + { 34, 20, 0x8000, 0x811c, 0x8124, 0x8000, 0x8004 },
340 +};
341 +
342 +/* pins are just named GPIO0..GPIO53 */
343 +#define RP1_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
344 +static struct pinctrl_pin_desc rp1_gpio_pins[] = {
345 + RP1_GPIO_PIN(0),
346 + RP1_GPIO_PIN(1),
347 + RP1_GPIO_PIN(2),
348 + RP1_GPIO_PIN(3),
349 + RP1_GPIO_PIN(4),
350 + RP1_GPIO_PIN(5),
351 + RP1_GPIO_PIN(6),
352 + RP1_GPIO_PIN(7),
353 + RP1_GPIO_PIN(8),
354 + RP1_GPIO_PIN(9),
355 + RP1_GPIO_PIN(10),
356 + RP1_GPIO_PIN(11),
357 + RP1_GPIO_PIN(12),
358 + RP1_GPIO_PIN(13),
359 + RP1_GPIO_PIN(14),
360 + RP1_GPIO_PIN(15),
361 + RP1_GPIO_PIN(16),
362 + RP1_GPIO_PIN(17),
363 + RP1_GPIO_PIN(18),
364 + RP1_GPIO_PIN(19),
365 + RP1_GPIO_PIN(20),
366 + RP1_GPIO_PIN(21),
367 + RP1_GPIO_PIN(22),
368 + RP1_GPIO_PIN(23),
369 + RP1_GPIO_PIN(24),
370 + RP1_GPIO_PIN(25),
371 + RP1_GPIO_PIN(26),
372 + RP1_GPIO_PIN(27),
373 + RP1_GPIO_PIN(28),
374 + RP1_GPIO_PIN(29),
375 + RP1_GPIO_PIN(30),
376 + RP1_GPIO_PIN(31),
377 + RP1_GPIO_PIN(32),
378 + RP1_GPIO_PIN(33),
379 + RP1_GPIO_PIN(34),
380 + RP1_GPIO_PIN(35),
381 + RP1_GPIO_PIN(36),
382 + RP1_GPIO_PIN(37),
383 + RP1_GPIO_PIN(38),
384 + RP1_GPIO_PIN(39),
385 + RP1_GPIO_PIN(40),
386 + RP1_GPIO_PIN(41),
387 + RP1_GPIO_PIN(42),
388 + RP1_GPIO_PIN(43),
389 + RP1_GPIO_PIN(44),
390 + RP1_GPIO_PIN(45),
391 + RP1_GPIO_PIN(46),
392 + RP1_GPIO_PIN(47),
393 + RP1_GPIO_PIN(48),
394 + RP1_GPIO_PIN(49),
395 + RP1_GPIO_PIN(50),
396 + RP1_GPIO_PIN(51),
397 + RP1_GPIO_PIN(52),
398 + RP1_GPIO_PIN(53),
399 +};
400 +
401 +/* one pin per group */
402 +static const char * const rp1_gpio_groups[] = {
403 + "gpio0",
404 + "gpio1",
405 + "gpio2",
406 + "gpio3",
407 + "gpio4",
408 + "gpio5",
409 + "gpio6",
410 + "gpio7",
411 + "gpio8",
412 + "gpio9",
413 + "gpio10",
414 + "gpio11",
415 + "gpio12",
416 + "gpio13",
417 + "gpio14",
418 + "gpio15",
419 + "gpio16",
420 + "gpio17",
421 + "gpio18",
422 + "gpio19",
423 + "gpio20",
424 + "gpio21",
425 + "gpio22",
426 + "gpio23",
427 + "gpio24",
428 + "gpio25",
429 + "gpio26",
430 + "gpio27",
431 + "gpio28",
432 + "gpio29",
433 + "gpio30",
434 + "gpio31",
435 + "gpio32",
436 + "gpio33",
437 + "gpio34",
438 + "gpio35",
439 + "gpio36",
440 + "gpio37",
441 + "gpio38",
442 + "gpio39",
443 + "gpio40",
444 + "gpio41",
445 + "gpio42",
446 + "gpio43",
447 + "gpio44",
448 + "gpio45",
449 + "gpio46",
450 + "gpio47",
451 + "gpio48",
452 + "gpio49",
453 + "gpio50",
454 + "gpio51",
455 + "gpio52",
456 + "gpio53",
457 +};
458 +
459 +static const char * const rp1_func_names[] = {
460 + FUNC(alt0),
461 + FUNC(alt1),
462 + FUNC(alt2),
463 + FUNC(alt3),
464 + FUNC(alt4),
465 + FUNC(gpio),
466 + FUNC(alt6),
467 + FUNC(alt7),
468 + FUNC(alt8),
469 + FUNC(none),
470 + FUNC(aaud),
471 + FUNC(dcd0),
472 + FUNC(dpi),
473 + FUNC(dsi0_te_ext),
474 + FUNC(dsi1_te_ext),
475 + FUNC(dsr0),
476 + FUNC(dtr0),
477 + FUNC(gpclk0),
478 + FUNC(gpclk1),
479 + FUNC(gpclk2),
480 + FUNC(gpclk3),
481 + FUNC(gpclk4),
482 + FUNC(gpclk5),
483 + FUNC(i2c0),
484 + FUNC(i2c1),
485 + FUNC(i2c2),
486 + FUNC(i2c3),
487 + FUNC(i2c4),
488 + FUNC(i2c5),
489 + FUNC(i2c6),
490 + FUNC(i2s0),
491 + FUNC(i2s1),
492 + FUNC(i2s2),
493 + FUNC(ir),
494 + FUNC(mic),
495 + FUNC(pcie_clkreq_n),
496 + FUNC(pio),
497 + FUNC(proc_rio),
498 + FUNC(pwm0),
499 + FUNC(pwm1),
500 + FUNC(ri0),
501 + FUNC(sd0),
502 + FUNC(sd1),
503 + FUNC(spi0),
504 + FUNC(spi1),
505 + FUNC(spi2),
506 + FUNC(spi3),
507 + FUNC(spi4),
508 + FUNC(spi5),
509 + FUNC(spi6),
510 + FUNC(spi7),
511 + FUNC(spi8),
512 + FUNC(uart0),
513 + FUNC(uart1),
514 + FUNC(uart2),
515 + FUNC(uart3),
516 + FUNC(uart4),
517 + FUNC(uart5),
518 + FUNC(vbus0),
519 + FUNC(vbus1),
520 + FUNC(vbus2),
521 + FUNC(vbus3),
522 + [func_invalid] = "?"
523 +};
524 +
525 +static const struct rp1_pin_funcs rp1_gpio_pin_funcs[] = {
526 + PIN(0, spi0, dpi, uart1, i2c0, _, gpio, proc_rio, pio, spi2),
527 + PIN(1, spi0, dpi, uart1, i2c0, _, gpio, proc_rio, pio, spi2),
528 + PIN(2, spi0, dpi, uart1, i2c1, ir, gpio, proc_rio, pio, spi2),
529 + PIN(3, spi0, dpi, uart1, i2c1, ir, gpio, proc_rio, pio, spi2),
530 + PIN(4, gpclk0, dpi, uart2, i2c2, ri0, gpio, proc_rio, pio, spi3),
531 + PIN(5, gpclk1, dpi, uart2, i2c2, dtr0, gpio, proc_rio, pio, spi3),
532 + PIN(6, gpclk2, dpi, uart2, i2c3, dcd0, gpio, proc_rio, pio, spi3),
533 + PIN(7, spi0, dpi, uart2, i2c3, dsr0, gpio, proc_rio, pio, spi3),
534 + PIN(8, spi0, dpi, uart3, i2c0, _, gpio, proc_rio, pio, spi4),
535 + PIN(9, spi0, dpi, uart3, i2c0, _, gpio, proc_rio, pio, spi4),
536 + PIN(10, spi0, dpi, uart3, i2c1, _, gpio, proc_rio, pio, spi4),
537 + PIN(11, spi0, dpi, uart3, i2c1, _, gpio, proc_rio, pio, spi4),
538 + PIN(12, pwm0, dpi, uart4, i2c2, aaud, gpio, proc_rio, pio, spi5),
539 + PIN(13, pwm0, dpi, uart4, i2c2, aaud, gpio, proc_rio, pio, spi5),
540 + PIN(14, pwm0, dpi, uart4, i2c3, uart0, gpio, proc_rio, pio, spi5),
541 + PIN(15, pwm0, dpi, uart4, i2c3, uart0, gpio, proc_rio, pio, spi5),
542 + PIN(16, spi1, dpi, dsi0_te_ext, _, uart0, gpio, proc_rio, pio, _),
543 + PIN(17, spi1, dpi, dsi1_te_ext, _, uart0, gpio, proc_rio, pio, _),
544 + PIN(18, spi1, dpi, i2s0, pwm0, i2s1, gpio, proc_rio, pio, gpclk1),
545 + PIN(19, spi1, dpi, i2s0, pwm0, i2s1, gpio, proc_rio, pio, _),
546 + PIN(20, spi1, dpi, i2s0, gpclk0, i2s1, gpio, proc_rio, pio, _),
547 + PIN(21, spi1, dpi, i2s0, gpclk1, i2s1, gpio, proc_rio, pio, _),
548 + PIN(22, sd0, dpi, i2s0, i2c3, i2s1, gpio, proc_rio, pio, _),
549 + PIN(23, sd0, dpi, i2s0, i2c3, i2s1, gpio, proc_rio, pio, _),
550 + PIN(24, sd0, dpi, i2s0, _, i2s1, gpio, proc_rio, pio, spi2),
551 + PIN(25, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi3),
552 + PIN(26, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi5),
553 + PIN(27, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi1),
554 + PIN(28, sd1, i2c4, i2s2, spi6, vbus0, gpio, proc_rio, _, _),
555 + PIN(29, sd1, i2c4, i2s2, spi6, vbus0, gpio, proc_rio, _, _),
556 + PIN(30, sd1, i2c5, i2s2, spi6, uart5, gpio, proc_rio, _, _),
557 + PIN(31, sd1, i2c5, i2s2, spi6, uart5, gpio, proc_rio, _, _),
558 + PIN(32, sd1, gpclk3, i2s2, spi6, uart5, gpio, proc_rio, _, _),
559 + PIN(33, sd1, gpclk4, i2s2, spi6, uart5, gpio, proc_rio, _, _),
560 + PIN(34, pwm1, gpclk3, vbus0, i2c4, mic, gpio, proc_rio, _, _),
561 + PIN(35, spi8, pwm1, vbus0, i2c4, mic, gpio, proc_rio, _, _),
562 + PIN(36, spi8, uart5, pcie_clkreq_n, i2c5, mic, gpio, proc_rio, _, _),
563 + PIN(37, spi8, uart5, mic, i2c5, pcie_clkreq_n, gpio, proc_rio, _, _),
564 + PIN(38, spi8, uart5, mic, i2c6, aaud, gpio, proc_rio, dsi0_te_ext, _),
565 + PIN(39, spi8, uart5, mic, i2c6, aaud, gpio, proc_rio, dsi1_te_ext, _),
566 + PIN(40, pwm1, uart5, i2c4, spi6, aaud, gpio, proc_rio, _, _),
567 + PIN(41, pwm1, uart5, i2c4, spi6, aaud, gpio, proc_rio, _, _),
568 + PIN(42, gpclk5, uart5, vbus1, spi6, i2s2, gpio, proc_rio, _, _),
569 + PIN(43, gpclk4, uart5, vbus1, spi6, i2s2, gpio, proc_rio, _, _),
570 + PIN(44, gpclk5, i2c5, pwm1, spi6, i2s2, gpio, proc_rio, _, _),
571 + PIN(45, pwm1, i2c5, spi7, spi6, i2s2, gpio, proc_rio, _, _),
572 + PIN(46, gpclk3, i2c4, spi7, mic, i2s2, gpio, proc_rio, dsi0_te_ext, _),
573 + PIN(47, gpclk5, i2c4, spi7, mic, i2s2, gpio, proc_rio, dsi1_te_ext, _),
574 + PIN(48, pwm1, pcie_clkreq_n, spi7, mic, uart5, gpio, proc_rio, _, _),
575 + PIN(49, spi8, spi7, i2c5, aaud, uart5, gpio, proc_rio, _, _),
576 + PIN(50, spi8, spi7, i2c5, aaud, vbus2, gpio, proc_rio, _, _),
577 + PIN(51, spi8, spi7, i2c6, aaud, vbus2, gpio, proc_rio, _, _),
578 + PIN(52, spi8, _, i2c6, aaud, vbus3, gpio, proc_rio, _, _),
579 + PIN(53, spi8, spi7, _, pcie_clkreq_n, vbus3, gpio, proc_rio, _, _),
580 +};
581 +
582 +static const u8 legacy_fsel_map[][8] = {
583 + LEGACY_MAP(0, i2c0, _, dpi, spi2, uart1, _),
584 + LEGACY_MAP(1, i2c0, _, dpi, spi2, uart1, _),
585 + LEGACY_MAP(2, i2c1, _, dpi, spi2, uart1, _),
586 + LEGACY_MAP(3, i2c1, _, dpi, spi2, uart1, _),
587 + LEGACY_MAP(4, gpclk0, _, dpi, spi3, uart2, i2c2),
588 + LEGACY_MAP(5, gpclk1, _, dpi, spi3, uart2, i2c2),
589 + LEGACY_MAP(6, gpclk2, _, dpi, spi3, uart2, i2c3),
590 + LEGACY_MAP(7, spi0, _, dpi, spi3, uart2, i2c3),
591 + LEGACY_MAP(8, spi0, _, dpi, _, uart3, i2c0),
592 + LEGACY_MAP(9, spi0, _, dpi, _, uart3, i2c0),
593 + LEGACY_MAP(10, spi0, _, dpi, _, uart3, i2c1),
594 + LEGACY_MAP(11, spi0, _, dpi, _, uart3, i2c1),
595 + LEGACY_MAP(12, pwm0, _, dpi, spi5, uart4, i2c2),
596 + LEGACY_MAP(13, pwm0, _, dpi, spi5, uart4, i2c2),
597 + LEGACY_MAP(14, uart0, _, dpi, spi5, uart4, _),
598 + LEGACY_MAP(15, uart0, _, dpi, spi5, uart4, _),
599 + LEGACY_MAP(16, _, _, dpi, uart0, spi1, _),
600 + LEGACY_MAP(17, _, _, dpi, uart0, spi1, _),
601 + LEGACY_MAP(18, i2s0, _, dpi, _, spi1, pwm0),
602 + LEGACY_MAP(19, i2s0, _, dpi, _, spi1, pwm0),
603 + LEGACY_MAP(20, i2s0, _, dpi, _, spi1, gpclk0),
604 + LEGACY_MAP(21, i2s0, _, dpi, _, spi1, gpclk1),
605 + LEGACY_MAP(22, sd0, _, dpi, _, _, i2c3),
606 + LEGACY_MAP(23, sd0, _, dpi, _, _, i2c3),
607 + LEGACY_MAP(24, sd0, _, dpi, _, _, spi2),
608 + LEGACY_MAP(25, sd0, _, dpi, _, _, spi3),
609 + LEGACY_MAP(26, sd0, _, dpi, _, _, spi5),
610 + LEGACY_MAP(27, sd0, _, dpi, _, _, _),
611 +};
612 +
613 +static const char * const irq_type_names[] = {
614 + [IRQ_TYPE_NONE] = "none",
615 + [IRQ_TYPE_EDGE_RISING] = "edge-rising",
616 + [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
617 + [IRQ_TYPE_EDGE_BOTH] = "edge-both",
618 + [IRQ_TYPE_LEVEL_HIGH] = "level-high",
619 + [IRQ_TYPE_LEVEL_LOW] = "level-low",
620 +};
621 +
622 +static int rp1_pinconf_set(struct pinctrl_dev *pctldev,
623 + unsigned int offset, unsigned long *configs,
624 + unsigned int num_configs);
625 +
626 +static struct rp1_pin_info *rp1_get_pin(struct gpio_chip *chip,
627 + unsigned int offset)
628 +{
629 + struct rp1_pinctrl *pc = gpiochip_get_data(chip);
630 +
631 + if (pc && offset < RP1_NUM_GPIOS)
632 + return &pc->pins[offset];
633 + return NULL;
634 +}
635 +
636 +static struct rp1_pin_info *rp1_get_pin_pctl(struct pinctrl_dev *pctldev,
637 + unsigned int offset)
638 +{
639 + struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
640 +
641 + if (pc && offset < RP1_NUM_GPIOS)
642 + return &pc->pins[offset];
643 + return NULL;
644 +}
645 +
646 +static void rp1_pad_update(struct rp1_pin_info *pin, u32 clr, u32 set)
647 +{
648 + u32 padctrl = readl(pin->pad);
649 +
650 + padctrl &= ~clr;
651 + padctrl |= set;
652 +
653 + writel(padctrl, pin->pad);
654 +}
655 +
656 +static void rp1_input_enable(struct rp1_pin_info *pin, int value)
657 +{
658 + rp1_pad_update(pin, RP1_PAD_IN_ENABLE_MASK,
659 + value ? RP1_PAD_IN_ENABLE_MASK : 0);
660 +}
661 +
662 +static void rp1_output_enable(struct rp1_pin_info *pin, int value)
663 +{
664 + rp1_pad_update(pin, RP1_PAD_OUT_DISABLE_MASK,
665 + value ? 0 : RP1_PAD_OUT_DISABLE_MASK);
666 +}
667 +
668 +static u32 rp1_get_fsel(struct rp1_pin_info *pin)
669 +{
670 + u32 ctrl = readl(pin->gpio + RP1_GPIO_CTRL);
671 + u32 oeover = FLD_GET(ctrl, RP1_GPIO_CTRL_OEOVER);
672 + u32 fsel = FLD_GET(ctrl, RP1_GPIO_CTRL_FUNCSEL);
673 +
674 + if (oeover != RP1_OEOVER_PERI || fsel >= RP1_FSEL_COUNT)
675 + fsel = RP1_FSEL_NONE;
676 +
677 + return fsel;
678 +}
679 +
680 +static void rp1_set_fsel(struct rp1_pin_info *pin, u32 fsel)
681 +{
682 + u32 ctrl = readl(pin->gpio + RP1_GPIO_CTRL);
683 +
684 + if (fsel >= RP1_FSEL_COUNT)
685 + fsel = RP1_FSEL_NONE_HW;
686 +
687 + rp1_input_enable(pin, 1);
688 + rp1_output_enable(pin, 1);
689 +
690 + if (fsel == RP1_FSEL_NONE) {
691 + FLD_SET(ctrl, RP1_GPIO_CTRL_OEOVER, RP1_OEOVER_DISABLE);
692 + } else {
693 + FLD_SET(ctrl, RP1_GPIO_CTRL_OUTOVER, RP1_OUTOVER_PERI);
694 + FLD_SET(ctrl, RP1_GPIO_CTRL_OEOVER, RP1_OEOVER_PERI);
695 + }
696 + FLD_SET(ctrl, RP1_GPIO_CTRL_FUNCSEL, fsel);
697 + writel(ctrl, pin->gpio + RP1_GPIO_CTRL);
698 +}
699 +
700 +static int rp1_get_dir(struct rp1_pin_info *pin)
701 +{
702 + return !(readl(pin->rio + RP1_RIO_OE) & (1 << pin->offset)) ?
703 + RP1_DIR_INPUT : RP1_DIR_OUTPUT;
704 +}
705 +
706 +static void rp1_set_dir(struct rp1_pin_info *pin, bool is_input)
707 +{
708 + int offset = is_input ? RP1_CLR_OFFSET : RP1_SET_OFFSET;
709 +
710 + writel(1 << pin->offset, pin->rio + RP1_RIO_OE + offset);
711 +}
712 +
713 +static int rp1_get_value(struct rp1_pin_info *pin)
714 +{
715 + return !!(readl(pin->rio + RP1_RIO_IN) & (1 << pin->offset));
716 +}
717 +
718 +static void rp1_set_value(struct rp1_pin_info *pin, int value)
719 +{
720 + /* Assume the pin is already an output */
721 + writel(1 << pin->offset,
722 + pin->rio + RP1_RIO_OUT + (value ? RP1_SET_OFFSET : RP1_CLR_OFFSET));
723 +}
724 +
725 +static int rp1_gpio_get(struct gpio_chip *chip, unsigned offset)
726 +{
727 + struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
728 + int ret;
729 +
730 + if (!pin)
731 + return -EINVAL;
732 + ret = rp1_get_value(pin);
733 + return ret;
734 +}
735 +
736 +static void rp1_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
737 +{
738 + struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
739 +
740 + if (pin)
741 + rp1_set_value(pin, value);
742 +}
743 +
744 +static int rp1_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
745 +{
746 + struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
747 + u32 fsel;
748 +
749 + if (!pin)
750 + return -EINVAL;
751 + fsel = rp1_get_fsel(pin);
752 + if (fsel != RP1_FSEL_GPIO)
753 + return -EINVAL;
754 + return (rp1_get_dir(pin) == RP1_DIR_OUTPUT) ?
755 + GPIO_LINE_DIRECTION_OUT :
756 + GPIO_LINE_DIRECTION_IN;
757 +}
758 +
759 +static int rp1_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
760 +{
761 + struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
762 +
763 + if (!pin)
764 + return -EINVAL;
765 + rp1_set_dir(pin, RP1_DIR_INPUT);
766 + rp1_set_fsel(pin, RP1_FSEL_GPIO);
767 + return 0;
768 +}
769 +
770 +static int rp1_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
771 + int value)
772 +{
773 + struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
774 +
775 + if (!pin)
776 + return -EINVAL;
777 + rp1_set_value(pin, value);
778 + rp1_set_dir(pin, RP1_DIR_OUTPUT);
779 + rp1_set_fsel(pin, RP1_FSEL_GPIO);
780 + return 0;
781 +}
782 +
783 +static int rp1_gpio_set_config(struct gpio_chip *gc, unsigned offset,
784 + unsigned long config)
785 +{
786 + struct rp1_pinctrl *pc = gpiochip_get_data(gc);
787 + unsigned long configs[] = { config };
788 +
789 + return rp1_pinconf_set(pc->pctl_dev, offset, configs,
790 + ARRAY_SIZE(configs));
791 +}
792 +
793 +static const struct gpio_chip rp1_gpio_chip = {
794 + .label = MODULE_NAME,
795 + .owner = THIS_MODULE,
796 + .request = gpiochip_generic_request,
797 + .free = gpiochip_generic_free,
798 + .direction_input = rp1_gpio_direction_input,
799 + .direction_output = rp1_gpio_direction_output,
800 + .get_direction = rp1_gpio_get_direction,
801 + .get = rp1_gpio_get,
802 + .set = rp1_gpio_set,
803 + .base = -1,
804 + .set_config = rp1_gpio_set_config,
805 + .ngpio = RP1_NUM_GPIOS,
806 + .can_sleep = false,
807 +};
808 +
809 +static void rp1_gpio_irq_handler(struct irq_desc *desc)
810 +{
811 + struct gpio_chip *chip = irq_desc_get_handler_data(desc);
812 + struct rp1_pinctrl *pc = gpiochip_get_data(chip);
813 + struct irq_chip *host_chip = irq_desc_get_chip(desc);
814 + const struct rp1_iobank_desc *bank;
815 + int irq = irq_desc_get_irq(desc);
816 + unsigned long ints;
817 + int b;
818 +
819 + if (pc->irq[0] == irq)
820 + bank = &rp1_iobanks[0];
821 + else if (pc->irq[1] == irq)
822 + bank = &rp1_iobanks[1];
823 + else
824 + bank = &rp1_iobanks[2];
825 +
826 + chained_irq_enter(host_chip, desc);
827 +
828 + ints = readl(pc->gpio_base + bank->ints_offset);
829 + for_each_set_bit(b, &ints, 32) {
830 + struct rp1_pin_info *pin = rp1_get_pin(chip, b);
831 +
832 + writel(RP1_GPIO_CTRL_IRQRESET,
833 + pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
834 + generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
835 + bank->gpio_offset + b));
836 + }
837 +
838 + chained_irq_exit(host_chip, desc);
839 +}
840 +
841 +static void rp1_gpio_irq_config(struct rp1_pin_info *pin, bool enable)
842 +{
843 + writel(1 << pin->offset,
844 + pin->inte + (enable ? RP1_SET_OFFSET : RP1_CLR_OFFSET));
845 + if (!enable)
846 + /* Clear any latched events */
847 + writel(RP1_GPIO_CTRL_IRQRESET,
848 + pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
849 +}
850 +
851 +static void rp1_gpio_irq_enable(struct irq_data *data)
852 +{
853 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
854 + unsigned gpio = irqd_to_hwirq(data);
855 + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
856 +
857 + rp1_gpio_irq_config(pin, true);
858 +}
859 +
860 +static void rp1_gpio_irq_disable(struct irq_data *data)
861 +{
862 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
863 + unsigned gpio = irqd_to_hwirq(data);
864 + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
865 +
866 + rp1_gpio_irq_config(pin, false);
867 +}
868 +
869 +static int rp1_irq_set_type(struct rp1_pin_info *pin, unsigned int type)
870 +{
871 + u32 irq_flags;
872 +
873 + switch (type) {
874 + case IRQ_TYPE_NONE:
875 + irq_flags = 0;
876 + break;
877 + case IRQ_TYPE_EDGE_RISING:
878 + irq_flags = RP1_INT_EDGE_RISING;
879 + break;
880 + case IRQ_TYPE_EDGE_FALLING:
881 + irq_flags = RP1_INT_EDGE_FALLING;
882 + break;
883 + case IRQ_TYPE_EDGE_BOTH:
884 + irq_flags = RP1_INT_EDGE_RISING | RP1_INT_EDGE_FALLING;
885 + break;
886 + case IRQ_TYPE_LEVEL_HIGH:
887 + irq_flags = RP1_INT_LEVEL_HIGH;
888 + break;
889 + case IRQ_TYPE_LEVEL_LOW:
890 + irq_flags = RP1_INT_LEVEL_LOW;
891 + break;
892 +
893 + default:
894 + return -EINVAL;
895 + }
896 +
897 + /* Clear them all */
898 + writel(RP1_INT_MASK << RP1_GPIO_EVENTS_SHIFT_RAW,
899 + pin->gpio + RP1_CLR_OFFSET + RP1_GPIO_CTRL);
900 + /* Set those that are needed */
901 + writel(irq_flags << RP1_GPIO_EVENTS_SHIFT_RAW,
902 + pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
903 + pin->irq_type = type;
904 +
905 + return 0;
906 +}
907 +
908 +static int rp1_gpio_irq_set_type(struct irq_data *data, unsigned int type)
909 +{
910 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
911 + struct rp1_pinctrl *pc = gpiochip_get_data(chip);
912 + unsigned gpio = irqd_to_hwirq(data);
913 + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
914 + int bank = pin->bank;
915 + unsigned long flags;
916 + int ret;
917 +
918 + raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
919 +
920 + ret = rp1_irq_set_type(pin, type);
921 + if (!ret) {
922 + if (type & IRQ_TYPE_EDGE_BOTH)
923 + irq_set_handler_locked(data, handle_edge_irq);
924 + else
925 + irq_set_handler_locked(data, handle_level_irq);
926 + }
927 +
928 + raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
929 +
930 + return ret;
931 +}
932 +
933 +static void rp1_gpio_irq_ack(struct irq_data *data)
934 +{
935 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
936 + unsigned gpio = irqd_to_hwirq(data);
937 + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
938 +
939 + /* Clear any latched events */
940 + writel(RP1_GPIO_CTRL_IRQRESET, pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
941 +}
942 +
943 +static struct irq_chip rp1_gpio_irq_chip = {
944 + .name = MODULE_NAME,
945 + .irq_enable = rp1_gpio_irq_enable,
946 + .irq_disable = rp1_gpio_irq_disable,
947 + .irq_set_type = rp1_gpio_irq_set_type,
948 + .irq_ack = rp1_gpio_irq_ack,
949 + .irq_mask = rp1_gpio_irq_disable,
950 + .irq_unmask = rp1_gpio_irq_enable,
951 + .flags = IRQCHIP_IMMUTABLE,
952 +};
953 +
954 +static int rp1_pctl_get_groups_count(struct pinctrl_dev *pctldev)
955 +{
956 + return ARRAY_SIZE(rp1_gpio_groups);
957 +}
958 +
959 +static const char *rp1_pctl_get_group_name(struct pinctrl_dev *pctldev,
960 + unsigned selector)
961 +{
962 + return rp1_gpio_groups[selector];
963 +}
964 +
965 +static enum funcs rp1_get_fsel_func(unsigned pin, unsigned fsel)
966 +{
967 + if (pin < RP1_NUM_GPIOS) {
968 + if (fsel < RP1_FSEL_COUNT)
969 + return rp1_gpio_pin_funcs[pin].funcs[fsel];
970 + else if (fsel == RP1_FSEL_NONE)
971 + return func_none;
972 + }
973 + return func_invalid;
974 +}
975 +
976 +static int rp1_pctl_get_group_pins(struct pinctrl_dev *pctldev,
977 + unsigned selector,
978 + const unsigned **pins,
979 + unsigned *num_pins)
980 +{
981 + *pins = &rp1_gpio_pins[selector].number;
982 + *num_pins = 1;
983 +
984 + return 0;
985 +}
986 +
987 +static void rp1_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
988 + struct seq_file *s,
989 + unsigned offset)
990 +{
991 + struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
992 + struct gpio_chip *chip = &pc->gpio_chip;
993 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
994 + u32 fsel = rp1_get_fsel(pin);
995 + enum funcs func = rp1_get_fsel_func(offset, fsel);
996 + int value = rp1_get_value(pin);
997 + int irq = irq_find_mapping(chip->irq.domain, offset);
998 +
999 + seq_printf(s, "function %s (%s) in %s; irq %d (%s)",
1000 + rp1_func_names[fsel], rp1_func_names[func],
1001 + value ? "hi" : "lo",
1002 + irq, irq_type_names[pin->irq_type]);
1003 +}
1004 +
1005 +static void rp1_pctl_dt_free_map(struct pinctrl_dev *pctldev,
1006 + struct pinctrl_map *maps, unsigned num_maps)
1007 +{
1008 + int i;
1009 +
1010 + for (i = 0; i < num_maps; i++)
1011 + if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1012 + kfree(maps[i].data.configs.configs);
1013 +
1014 + kfree(maps);
1015 +}
1016 +
1017 +static int rp1_pctl_legacy_map_func(struct rp1_pinctrl *pc,
1018 + struct device_node *np, u32 pin, u32 fnum,
1019 + struct pinctrl_map *maps,
1020 + unsigned int *num_maps)
1021 +{
1022 + struct pinctrl_map *map = &maps[*num_maps];
1023 + enum funcs func;
1024 +
1025 + if (fnum >= ARRAY_SIZE(legacy_fsel_map[0])) {
1026 + dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
1027 + return -EINVAL;
1028 + }
1029 +
1030 + func = legacy_fsel_map[pin][fnum];
1031 + if (func == func_invalid) {
1032 + dev_err(pc->dev, "%pOF: brcm,function %d not supported on pin %d\n",
1033 + np, fnum, pin);
1034 + }
1035 +
1036 + map->type = PIN_MAP_TYPE_MUX_GROUP;
1037 + map->data.mux.group = rp1_gpio_groups[pin];
1038 + map->data.mux.function = rp1_func_names[func];
1039 + (*num_maps)++;
1040 +
1041 + return 0;
1042 +}
1043 +
1044 +static int rp1_pctl_legacy_map_pull(struct rp1_pinctrl *pc,
1045 + struct device_node *np, u32 pin, u32 pull,
1046 + struct pinctrl_map *maps,
1047 + unsigned int *num_maps)
1048 +{
1049 + struct pinctrl_map *map = &maps[*num_maps];
1050 + enum pin_config_param param;
1051 + unsigned long *configs;
1052 +
1053 + switch (pull) {
1054 + case RP1_PUD_OFF:
1055 + param = PIN_CONFIG_BIAS_DISABLE;
1056 + break;
1057 + case RP1_PUD_DOWN:
1058 + param = PIN_CONFIG_BIAS_PULL_DOWN;
1059 + break;
1060 + case RP1_PUD_UP:
1061 + param = PIN_CONFIG_BIAS_PULL_UP;
1062 + break;
1063 + default:
1064 + dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
1065 + return -EINVAL;
1066 + }
1067 +
1068 + configs = kzalloc(sizeof(*configs), GFP_KERNEL);
1069 + if (!configs)
1070 + return -ENOMEM;
1071 +
1072 + configs[0] = pinconf_to_config_packed(param, 0);
1073 + map->type = PIN_MAP_TYPE_CONFIGS_PIN;
1074 + map->data.configs.group_or_pin = rp1_gpio_pins[pin].name;
1075 + map->data.configs.configs = configs;
1076 + map->data.configs.num_configs = 1;
1077 + (*num_maps)++;
1078 +
1079 + return 0;
1080 +}
1081 +
1082 +static int rp1_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
1083 + struct device_node *np,
1084 + struct pinctrl_map **map,
1085 + unsigned int *num_maps)
1086 +{
1087 + struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1088 + struct property *pins, *funcs, *pulls;
1089 + int num_pins, num_funcs, num_pulls, maps_per_pin;
1090 + struct pinctrl_map *maps;
1091 + unsigned long *configs = NULL;
1092 + const char *function = NULL;
1093 + unsigned int reserved_maps;
1094 + int num_configs = 0;
1095 + int i, err;
1096 + u32 pin, func, pull;
1097 +
1098 + /* Check for legacy pin declaration */
1099 + pins = of_find_property(np, "brcm,pins", NULL);
1100 +
1101 + if (!pins) /* Assume generic bindings in this node */
1102 + return pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
1103 +
1104 + funcs = of_find_property(np, "brcm,function", NULL);
1105 + if (!funcs)
1106 + of_property_read_string(np, "function", &function);
1107 +
1108 + pulls = of_find_property(np, "brcm,pull", NULL);
1109 + if (!pulls)
1110 + pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
1111 +
1112 + if (!function && !funcs && !num_configs && !pulls) {
1113 + dev_err(pc->dev,
1114 + "%pOF: no function, brcm,function, brcm,pull, etc.\n",
1115 + np);
1116 + return -EINVAL;
1117 + }
1118 +
1119 + num_pins = pins->length / 4;
1120 + num_funcs = funcs ? (funcs->length / 4) : 0;
1121 + num_pulls = pulls ? (pulls->length / 4) : 0;
1122 +
1123 + if (num_funcs > 1 && num_funcs != num_pins) {
1124 + dev_err(pc->dev,
1125 + "%pOF: brcm,function must have 1 or %d entries\n",
1126 + np, num_pins);
1127 + return -EINVAL;
1128 + }
1129 +
1130 + if (num_pulls > 1 && num_pulls != num_pins) {
1131 + dev_err(pc->dev,
1132 + "%pOF: brcm,pull must have 1 or %d entries\n",
1133 + np, num_pins);
1134 + return -EINVAL;
1135 + }
1136 +
1137 + maps_per_pin = 0;
1138 + if (function || num_funcs)
1139 + maps_per_pin++;
1140 + if (num_configs || num_pulls)
1141 + maps_per_pin++;
1142 + reserved_maps = num_pins * maps_per_pin;
1143 + maps = kcalloc(reserved_maps, sizeof(*maps), GFP_KERNEL);
1144 + if (!maps)
1145 + return -ENOMEM;
1146 +
1147 + *num_maps = 0;
1148 +
1149 + for (i = 0; i < num_pins; i++) {
1150 + err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
1151 + if (err)
1152 + goto out;
1153 + if (pin >= ARRAY_SIZE(legacy_fsel_map)) {
1154 + dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
1155 + np, pin);
1156 + err = -EINVAL;
1157 + goto out;
1158 + }
1159 +
1160 + if (num_funcs) {
1161 + err = of_property_read_u32_index(np, "brcm,function",
1162 + (num_funcs > 1) ? i : 0,
1163 + &func);
1164 + if (err)
1165 + goto out;
1166 + err = rp1_pctl_legacy_map_func(pc, np, pin, func,
1167 + maps, num_maps);
1168 + } else if (function) {
1169 + err = pinctrl_utils_add_map_mux(pctldev, &maps,
1170 + &reserved_maps, num_maps,
1171 + rp1_gpio_groups[pin],
1172 + function);
1173 + }
1174 +
1175 + if (err)
1176 + goto out;
1177 +
1178 + if (num_pulls) {
1179 + err = of_property_read_u32_index(np, "brcm,pull",
1180 + (num_pulls > 1) ? i : 0,
1181 + &pull);
1182 + if (err)
1183 + goto out;
1184 + err = rp1_pctl_legacy_map_pull(pc, np, pin, pull,
1185 + maps, num_maps);
1186 + } else if (num_configs) {
1187 + err = pinctrl_utils_add_map_configs(pctldev, &maps,
1188 + &reserved_maps, num_maps,
1189 + rp1_gpio_groups[pin],
1190 + configs, num_configs,
1191 + PIN_MAP_TYPE_CONFIGS_PIN);
1192 + }
1193 +
1194 + if (err)
1195 + goto out;
1196 + }
1197 +
1198 + *map = maps;
1199 +
1200 + return 0;
1201 +
1202 +out:
1203 + rp1_pctl_dt_free_map(pctldev, maps, reserved_maps);
1204 + return err;
1205 +}
1206 +
1207 +static const struct pinctrl_ops rp1_pctl_ops = {
1208 + .get_groups_count = rp1_pctl_get_groups_count,
1209 + .get_group_name = rp1_pctl_get_group_name,
1210 + .get_group_pins = rp1_pctl_get_group_pins,
1211 + .pin_dbg_show = rp1_pctl_pin_dbg_show,
1212 + .dt_node_to_map = rp1_pctl_dt_node_to_map,
1213 + .dt_free_map = rp1_pctl_dt_free_map,
1214 +};
1215 +
1216 +static int rp1_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
1217 +{
1218 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1219 + u32 fsel = rp1_get_fsel(pin);
1220 +
1221 + /* Return non-GPIOs to GPIO_IN */
1222 + if (fsel != RP1_FSEL_GPIO) {
1223 + rp1_set_dir(pin, RP1_DIR_INPUT);
1224 + rp1_set_fsel(pin, RP1_FSEL_GPIO);
1225 + }
1226 +
1227 + return 0;
1228 +}
1229 +
1230 +static int rp1_pmx_get_functions_count(struct pinctrl_dev *pctldev)
1231 +{
1232 + return func_count;
1233 +}
1234 +
1235 +static const char *rp1_pmx_get_function_name(struct pinctrl_dev *pctldev,
1236 + unsigned selector)
1237 +{
1238 + return (selector < func_count) ? rp1_func_names[selector] : NULL;
1239 +}
1240 +
1241 +static int rp1_pmx_get_function_groups(struct pinctrl_dev *pctldev,
1242 + unsigned selector,
1243 + const char * const **groups,
1244 + unsigned * const num_groups)
1245 +{
1246 + /* every pin can do every function */
1247 + *groups = rp1_gpio_groups;
1248 + *num_groups = ARRAY_SIZE(rp1_gpio_groups);
1249 +
1250 + return 0;
1251 +}
1252 +
1253 +static int rp1_pmx_set(struct pinctrl_dev *pctldev, unsigned func_selector,
1254 + unsigned group_selector)
1255 +{
1256 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, group_selector);
1257 + const u8 *pin_funcs;
1258 + int fsel;
1259 +
1260 + /* func_selector is an enum funcs, so needs translation */
1261 +
1262 + if (func_selector >= RP1_FSEL_COUNT) {
1263 + /* Convert to an fsel number */
1264 + pin_funcs = rp1_gpio_pin_funcs[pin->num].funcs;
1265 + for (fsel = 0; fsel < RP1_FSEL_COUNT; fsel++) {
1266 + if (pin_funcs[fsel] == func_selector)
1267 + break;
1268 + }
1269 + } else {
1270 + fsel = (int)func_selector;
1271 + }
1272 +
1273 + if (fsel >= RP1_FSEL_COUNT && fsel != RP1_FSEL_NONE)
1274 + return -EINVAL;
1275 +
1276 + rp1_set_fsel(pin, fsel);
1277 +
1278 + return 0;
1279 +}
1280 +
1281 +static void rp1_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
1282 + struct pinctrl_gpio_range *range,
1283 + unsigned offset)
1284 +{
1285 + (void)rp1_pmx_free(pctldev, offset);
1286 +}
1287 +
1288 +static int rp1_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1289 + struct pinctrl_gpio_range *range,
1290 + unsigned offset,
1291 + bool input)
1292 +{
1293 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1294 +
1295 + rp1_set_dir(pin, input);
1296 + rp1_set_fsel(pin, RP1_FSEL_GPIO);
1297 +
1298 + return 0;
1299 +}
1300 +
1301 +static const struct pinmux_ops rp1_pmx_ops = {
1302 + .free = rp1_pmx_free,
1303 + .get_functions_count = rp1_pmx_get_functions_count,
1304 + .get_function_name = rp1_pmx_get_function_name,
1305 + .get_function_groups = rp1_pmx_get_function_groups,
1306 + .set_mux = rp1_pmx_set,
1307 + .gpio_disable_free = rp1_pmx_gpio_disable_free,
1308 + .gpio_set_direction = rp1_pmx_gpio_set_direction,
1309 +};
1310 +
1311 +static void rp1_pull_config_set(struct rp1_pin_info *pin, unsigned int arg)
1312 +{
1313 + u32 padctrl = readl(pin->pad);
1314 +
1315 + FLD_SET(padctrl, RP1_PAD_PULL, arg & 0x3);
1316 +
1317 + writel(padctrl, pin->pad);
1318 +}
1319 +
1320 +/* Generic pinconf methods */
1321 +
1322 +static int rp1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int offset,
1323 + unsigned long *configs, unsigned int num_configs)
1324 +{
1325 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1326 + u32 param, arg;
1327 + int i;
1328 +
1329 + if (!pin)
1330 + return -EINVAL;
1331 +
1332 + for (i = 0; i < num_configs; i++) {
1333 + param = pinconf_to_config_param(configs[i]);
1334 + arg = pinconf_to_config_argument(configs[i]);
1335 +
1336 + switch (param) {
1337 + case PIN_CONFIG_BIAS_DISABLE:
1338 + rp1_pull_config_set(pin, RP1_PUD_OFF);
1339 + break;
1340 +
1341 + case PIN_CONFIG_BIAS_PULL_DOWN:
1342 + rp1_pull_config_set(pin, RP1_PUD_DOWN);
1343 + break;
1344 +
1345 + case PIN_CONFIG_BIAS_PULL_UP:
1346 + rp1_pull_config_set(pin, RP1_PUD_UP);
1347 + break;
1348 +
1349 + case PIN_CONFIG_INPUT_ENABLE:
1350 + rp1_input_enable(pin, arg);
1351 + break;
1352 +
1353 + case PIN_CONFIG_OUTPUT_ENABLE:
1354 + rp1_output_enable(pin, arg);
1355 + break;
1356 +
1357 + case PIN_CONFIG_OUTPUT:
1358 + rp1_set_value(pin, arg);
1359 + rp1_set_dir(pin, RP1_DIR_OUTPUT);
1360 + rp1_set_fsel(pin, RP1_FSEL_GPIO);
1361 + break;
1362 +
1363 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1364 + rp1_pad_update(pin, RP1_PAD_SCHMITT_MASK,
1365 + arg ? RP1_PAD_SCHMITT_MASK : 0);
1366 + break;
1367 +
1368 + case PIN_CONFIG_SLEW_RATE:
1369 + rp1_pad_update(pin, RP1_PAD_SLEWFAST_MASK,
1370 + arg ? RP1_PAD_SLEWFAST_MASK : 0);
1371 + break;
1372 +
1373 + case PIN_CONFIG_DRIVE_STRENGTH:
1374 + switch (arg) {
1375 + case 2:
1376 + arg = RP1_PAD_DRIVE_2MA;
1377 + break;
1378 + case 4:
1379 + arg = RP1_PAD_DRIVE_4MA;
1380 + break;
1381 + case 8:
1382 + arg = RP1_PAD_DRIVE_8MA;
1383 + break;
1384 + case 12:
1385 + arg = RP1_PAD_DRIVE_12MA;
1386 + break;
1387 + default:
1388 + return -ENOTSUPP;
1389 + }
1390 + rp1_pad_update(pin, RP1_PAD_DRIVE_MASK, arg);
1391 + break;
1392 +
1393 + default:
1394 + return -ENOTSUPP;
1395 +
1396 + } /* switch param type */
1397 + } /* for each config */
1398 +
1399 + return 0;
1400 +}
1401 +
1402 +static int rp1_pinconf_get(struct pinctrl_dev *pctldev, unsigned offset,
1403 + unsigned long *config)
1404 +{
1405 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1406 + enum pin_config_param param = pinconf_to_config_param(*config);
1407 + u32 padctrl;
1408 + u32 arg;
1409 +
1410 + if (!pin)
1411 + return -EINVAL;
1412 +
1413 + padctrl = readl(pin->pad);
1414 +
1415 + switch (param) {
1416 + case PIN_CONFIG_INPUT_ENABLE:
1417 + arg = !!(padctrl & RP1_PAD_IN_ENABLE_MASK);
1418 + break;
1419 + case PIN_CONFIG_OUTPUT_ENABLE:
1420 + arg = !(padctrl & RP1_PAD_OUT_DISABLE_MASK);
1421 + break;
1422 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1423 + arg = !!(padctrl & RP1_PAD_SCHMITT_MASK);
1424 + break;
1425 + case PIN_CONFIG_SLEW_RATE:
1426 + arg = !!(padctrl & RP1_PAD_SLEWFAST_MASK);
1427 + break;
1428 + case PIN_CONFIG_DRIVE_STRENGTH:
1429 + switch (padctrl & RP1_PAD_DRIVE_MASK) {
1430 + case RP1_PAD_DRIVE_2MA:
1431 + arg = 2;
1432 + break;
1433 + case RP1_PAD_DRIVE_4MA:
1434 + arg = 4;
1435 + break;
1436 + case RP1_PAD_DRIVE_8MA:
1437 + arg = 8;
1438 + break;
1439 + case RP1_PAD_DRIVE_12MA:
1440 + arg = 12;
1441 + break;
1442 + }
1443 + break;
1444 + case PIN_CONFIG_BIAS_DISABLE:
1445 + arg = ((padctrl & RP1_PAD_PULL_MASK) == (RP1_PUD_OFF << RP1_PAD_PULL_LSB));
1446 + break;
1447 + case PIN_CONFIG_BIAS_PULL_DOWN:
1448 + arg = ((padctrl & RP1_PAD_PULL_MASK) == (RP1_PUD_DOWN << RP1_PAD_PULL_LSB));
1449 + break;
1450 +
1451 + case PIN_CONFIG_BIAS_PULL_UP:
1452 + arg = ((padctrl & RP1_PAD_PULL_MASK) == (RP1_PUD_UP << RP1_PAD_PULL_LSB));
1453 + break;
1454 + default:
1455 + return -ENOTSUPP;
1456 + }
1457 +
1458 + *config = pinconf_to_config_packed(param, arg);
1459 +
1460 + return 0;
1461 +}
1462 +
1463 +static const struct pinconf_ops rp1_pinconf_ops = {
1464 + .is_generic = true,
1465 + .pin_config_get = rp1_pinconf_get,
1466 + .pin_config_set = rp1_pinconf_set,
1467 +};
1468 +
1469 +static struct pinctrl_desc rp1_pinctrl_desc = {
1470 + .name = MODULE_NAME,
1471 + .pins = rp1_gpio_pins,
1472 + .npins = ARRAY_SIZE(rp1_gpio_pins),
1473 + .pctlops = &rp1_pctl_ops,
1474 + .pmxops = &rp1_pmx_ops,
1475 + .confops = &rp1_pinconf_ops,
1476 + .owner = THIS_MODULE,
1477 +};
1478 +
1479 +static struct pinctrl_gpio_range rp1_pinctrl_gpio_range = {
1480 + .name = MODULE_NAME,
1481 + .npins = RP1_NUM_GPIOS,
1482 +};
1483 +
1484 +static const struct of_device_id rp1_pinctrl_match[] = {
1485 + {
1486 + .compatible = "raspberrypi,rp1-gpio",
1487 + .data = &rp1_pinconf_ops,
1488 + },
1489 + {}
1490 +};
1491 +
1492 +static inline void __iomem *devm_auto_iomap(struct platform_device *pdev,
1493 + unsigned int index)
1494 +{
1495 + struct device *dev = &pdev->dev;
1496 + struct device_node *np = dev->of_node;
1497 +
1498 + if (np)
1499 + return devm_of_iomap(dev, np, (int)index, NULL);
1500 + else
1501 + return devm_platform_ioremap_resource(pdev, index);
1502 +}
1503 +
1504 +static int rp1_pinctrl_probe(struct platform_device *pdev)
1505 +{
1506 + struct device *dev = &pdev->dev;
1507 + struct device_node *np = dev->of_node;
1508 + struct rp1_pinctrl *pc;
1509 + struct gpio_irq_chip *girq;
1510 + int err, i;
1511 +
1512 + BUILD_BUG_ON(ARRAY_SIZE(rp1_gpio_pins) != RP1_NUM_GPIOS);
1513 + BUILD_BUG_ON(ARRAY_SIZE(rp1_gpio_groups) != RP1_NUM_GPIOS);
1514 +
1515 + pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1516 + if (!pc)
1517 + return -ENOMEM;
1518 +
1519 + platform_set_drvdata(pdev, pc);
1520 + pc->dev = dev;
1521 +
1522 + pc->gpio_base = devm_auto_iomap(pdev, 0);
1523 + if (IS_ERR(pc->gpio_base)) {
1524 + dev_err(dev, "could not get GPIO IO memory\n");
1525 + return PTR_ERR(pc->gpio_base);
1526 + }
1527 +
1528 + pc->rio_base = devm_auto_iomap(pdev, 1);
1529 + if (IS_ERR(pc->rio_base)) {
1530 + dev_err(dev, "could not get RIO IO memory\n");
1531 + return PTR_ERR(pc->rio_base);
1532 + }
1533 +
1534 + pc->pads_base = devm_auto_iomap(pdev, 2);
1535 + if (IS_ERR(pc->pads_base)) {
1536 + dev_err(dev, "could not get PADS IO memory\n");
1537 + return PTR_ERR(pc->pads_base);
1538 + }
1539 +
1540 + pc->gpio_chip = rp1_gpio_chip;
1541 + pc->gpio_chip.parent = dev;
1542 +
1543 + for (i = 0; i < RP1_NUM_BANKS; i++) {
1544 + const struct rp1_iobank_desc *bank = &rp1_iobanks[i];
1545 + int j;
1546 +
1547 + for (j = 0; j < bank->num_gpios; j++) {
1548 + struct rp1_pin_info *pin =
1549 + &pc->pins[bank->min_gpio + j];
1550 +
1551 + pin->num = bank->min_gpio + j;
1552 + pin->bank = i;
1553 + pin->offset = j;
1554 +
1555 + pin->gpio = pc->gpio_base + bank->gpio_offset +
1556 + j * sizeof(u32) * 2;
1557 + pin->inte = pc->gpio_base + bank->inte_offset;
1558 + pin->ints = pc->gpio_base + bank->ints_offset;
1559 + pin->rio = pc->rio_base + bank->rio_offset;
1560 + pin->pad = pc->pads_base + bank->pads_offset +
1561 + j * sizeof(u32);
1562 + }
1563 +
1564 + raw_spin_lock_init(&pc->irq_lock[i]);
1565 + }
1566 +
1567 + pc->pctl_dev = devm_pinctrl_register(dev, &rp1_pinctrl_desc, pc);
1568 + if (IS_ERR(pc->pctl_dev))
1569 + return PTR_ERR(pc->pctl_dev);
1570 +
1571 + girq = &pc->gpio_chip.irq;
1572 + girq->chip = &rp1_gpio_irq_chip;
1573 + girq->parent_handler = rp1_gpio_irq_handler;
1574 + girq->num_parents = RP1_NUM_BANKS;
1575 + girq->parents = pc->irq;
1576 +
1577 + /*
1578 + * Use the same handler for all groups: this is necessary
1579 + * since we use one gpiochip to cover all lines - the
1580 + * irq handler then needs to figure out which group and
1581 + * bank that was firing the IRQ and look up the per-group
1582 + * and bank data.
1583 + */
1584 + for (i = 0; i < RP1_NUM_BANKS; i++) {
1585 + pc->irq[i] = irq_of_parse_and_map(np, i);
1586 + if (!pc->irq[i]) {
1587 + girq->num_parents = i;
1588 + break;
1589 + }
1590 + }
1591 +
1592 + girq->default_type = IRQ_TYPE_NONE;
1593 + girq->handler = handle_level_irq;
1594 +
1595 + err = devm_gpiochip_add_data(dev, &pc->gpio_chip, pc);
1596 + if (err) {
1597 + dev_err(dev, "could not add GPIO chip\n");
1598 + return err;
1599 + }
1600 +
1601 + pc->gpio_range = rp1_pinctrl_gpio_range;
1602 + pc->gpio_range.base = pc->gpio_chip.base;
1603 + pc->gpio_range.gc = &pc->gpio_chip;
1604 + pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1605 +
1606 + return 0;
1607 +}
1608 +
1609 +static struct platform_driver rp1_pinctrl_driver = {
1610 + .probe = rp1_pinctrl_probe,
1611 + .driver = {
1612 + .name = MODULE_NAME,
1613 + .of_match_table = rp1_pinctrl_match,
1614 + .suppress_bind_attrs = true,
1615 + },
1616 +};
1617 +builtin_platform_driver(rp1_pinctrl_driver);
1618 --- a/include/dt-bindings/pinctrl/rp1.h
1619 +++ /dev/null
1620 @@ -1,46 +0,0 @@
1621 -/* SPDX-License-Identifier: GPL-2.0 */
1622 -/*
1623 - * Header providing constants for RP1 pinctrl bindings.
1624 - *
1625 - * Copyright (C) 2019-2022 Raspberry Pi Ltd.
1626 - */
1627 -
1628 -#ifndef __DT_BINDINGS_PINCTRL_RP1_H__
1629 -#define __DT_BINDINGS_PINCTRL_RP1_H__
1630 -
1631 -/* brcm,function property */
1632 -#define RP1_FSEL_GPIO_IN 0
1633 -#define RP1_FSEL_GPIO_OUT 1
1634 -#define RP1_FSEL_ALT0_LEGACY 4
1635 -#define RP1_FSEL_ALT1_LEGACY 5
1636 -#define RP1_FSEL_ALT2_LEGACY 6
1637 -#define RP1_FSEL_ALT3_LEGACY 7
1638 -#define RP1_FSEL_ALT4_LEGACY 3
1639 -#define RP1_FSEL_ALT5_LEGACY 2
1640 -#define RP1_FSEL_ALT0 0x08
1641 -#define RP1_FSEL_ALT0INV 0x09
1642 -#define RP1_FSEL_ALT1 0x0a
1643 -#define RP1_FSEL_ALT1INV 0x0b
1644 -#define RP1_FSEL_ALT2 0x0c
1645 -#define RP1_FSEL_ALT2INV 0x0d
1646 -#define RP1_FSEL_ALT3 0x0e
1647 -#define RP1_FSEL_ALT3INV 0x0f
1648 -#define RP1_FSEL_ALT4 0x10
1649 -#define RP1_FSEL_ALT4INV 0x11
1650 -#define RP1_FSEL_ALT5 0x12
1651 -#define RP1_FSEL_ALT5INV 0x13
1652 -#define RP1_FSEL_ALT6 0x14
1653 -#define RP1_FSEL_ALT6INV 0x15
1654 -#define RP1_FSEL_ALT7 0x16
1655 -#define RP1_FSEL_ALT7INV 0x17
1656 -#define RP1_FSEL_ALT8 0x18
1657 -#define RP1_FSEL_ALT8INV 0x19
1658 -#define RP1_FSEL_NONE 0x1a
1659 -
1660 -/* brcm,pull property */
1661 -#define RP1_PUD_OFF 0
1662 -#define RP1_PUD_DOWN 1
1663 -#define RP1_PUD_UP 2
1664 -#define RP1_PUD_KEEP 3
1665 -
1666 -#endif /* __DT_BINDINGS_PINCTRL_RP1_H__ */
Staging tree of Daniel Golle