target/linux/bcm27xx/patches-6.1/950-0871-dt-binding-mfd-Add-binding-for-Raspberry-Pi-RP1.patch

   1 From c93f469dabdbed822e5abeb5283d79fc9faa858c Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.com>
   3 Date: Fri, 28 Oct 2022 14:10:34 +0100
   4 Subject: [PATCH] dt-binding: mfd: Add binding for Raspberry Pi RP1
   5
   6 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
   7 ---
   8  include/dt-bindings/mfd/rp1.h | 235 ++++++++++++++++++++++++++++++++++
   9  1 file changed, 235 insertions(+)
  10  create mode 100644 include/dt-bindings/mfd/rp1.h
  11
  12 --- /dev/null
  13 +++ b/include/dt-bindings/mfd/rp1.h
  14 @@ -0,0 +1,235 @@
  15 +/* SPDX-License-Identifier: GPL-2.0 */
  16 +/*
  17 + * This header provides constants for the PY MFD.
  18 + */
  19 +
  20 +#ifndef _RP1_H
  21 +#define _RP1_H
  22 +
  23 +/* Address map */
  24 +#define RP1_SYSINFO_BASE 0x000000
  25 +#define RP1_TBMAN_BASE 0x004000
  26 +#define RP1_SYSCFG_BASE 0x008000
  27 +#define RP1_OTP_BASE 0x00c000
  28 +#define RP1_POWER_BASE 0x010000
  29 +#define RP1_RESETS_BASE 0x014000
  30 +#define RP1_CLOCKS_BANK_DEFAULT_BASE 0x018000
  31 +#define RP1_CLOCKS_BANK_VIDEO_BASE 0x01c000
  32 +#define RP1_PLL_SYS_BASE 0x020000
  33 +#define RP1_PLL_AUDIO_BASE 0x024000
  34 +#define RP1_PLL_VIDEO_BASE 0x028000
  35 +#define RP1_UART0_BASE 0x030000
  36 +#define RP1_UART1_BASE 0x034000
  37 +#define RP1_UART2_BASE 0x038000
  38 +#define RP1_UART3_BASE 0x03c000
  39 +#define RP1_UART4_BASE 0x040000
  40 +#define RP1_UART5_BASE 0x044000
  41 +#define RP1_SPI8_BASE 0x04c000
  42 +#define RP1_SPI0_BASE 0x050000
  43 +#define RP1_SPI1_BASE 0x054000
  44 +#define RP1_SPI2_BASE 0x058000
  45 +#define RP1_SPI3_BASE 0x05c000
  46 +#define RP1_SPI4_BASE 0x060000
  47 +#define RP1_SPI5_BASE 0x064000
  48 +#define RP1_SPI6_BASE 0x068000
  49 +#define RP1_SPI7_BASE 0x06c000
  50 +#define RP1_I2C0_BASE 0x070000
  51 +#define RP1_I2C1_BASE 0x074000
  52 +#define RP1_I2C2_BASE 0x078000
  53 +#define RP1_I2C3_BASE 0x07c000
  54 +#define RP1_I2C4_BASE 0x080000
  55 +#define RP1_I2C5_BASE 0x084000
  56 +#define RP1_I2C6_BASE 0x088000
  57 +#define RP1_AUDIO_IN_BASE 0x090000
  58 +#define RP1_AUDIO_OUT_BASE 0x094000
  59 +#define RP1_PWM0_BASE 0x098000
  60 +#define RP1_PWM1_BASE 0x09c000
  61 +#define RP1_I2S0_BASE 0x0a0000
  62 +#define RP1_I2S1_BASE 0x0a4000
  63 +#define RP1_I2S2_BASE 0x0a8000
  64 +#define RP1_TIMER_BASE 0x0ac000
  65 +#define RP1_SDIO0_APBS_BASE 0x0b0000
  66 +#define RP1_SDIO1_APBS_BASE 0x0b4000
  67 +#define RP1_BUSFABRIC_MONITOR_BASE 0x0c0000
  68 +#define RP1_BUSFABRIC_AXISHIM_BASE 0x0c4000
  69 +#define RP1_ADC_BASE 0x0c8000
  70 +#define RP1_IO_BANK0_BASE 0x0d0000
  71 +#define RP1_IO_BANK1_BASE 0x0d4000
  72 +#define RP1_IO_BANK2_BASE 0x0d8000
  73 +#define RP1_SYS_RIO0_BASE 0x0e0000
  74 +#define RP1_SYS_RIO1_BASE 0x0e4000
  75 +#define RP1_SYS_RIO2_BASE 0x0e8000
  76 +#define RP1_PADS_BANK0_BASE 0x0f0000
  77 +#define RP1_PADS_BANK1_BASE 0x0f4000
  78 +#define RP1_PADS_BANK2_BASE 0x0f8000
  79 +#define RP1_PADS_ETH_BASE 0x0fc000
  80 +#define RP1_ETH_IP_BASE 0x100000
  81 +#define RP1_ETH_CFG_BASE 0x104000
  82 +#define RP1_PCIE_APBS_BASE 0x108000
  83 +#define RP1_MIPI0_CSIDMA_BASE 0x110000
  84 +#define RP1_MIPI0_CSIHOST_BASE 0x114000
  85 +#define RP1_MIPI0_DSIDMA_BASE 0x118000
  86 +#define RP1_MIPI0_DSIHOST_BASE 0x11c000
  87 +#define RP1_MIPI0_MIPICFG_BASE 0x120000
  88 +#define RP1_MIPI0_ISP_BASE 0x124000
  89 +#define RP1_MIPI1_CSIDMA_BASE 0x128000
  90 +#define RP1_MIPI1_CSIHOST_BASE 0x12c000
  91 +#define RP1_MIPI1_DSIDMA_BASE 0x130000
  92 +#define RP1_MIPI1_DSIHOST_BASE 0x134000
  93 +#define RP1_MIPI1_MIPICFG_BASE 0x138000
  94 +#define RP1_MIPI1_ISP_BASE 0x13c000
  95 +#define RP1_VIDEO_OUT_CFG_BASE 0x140000
  96 +#define RP1_VIDEO_OUT_VEC_BASE 0x144000
  97 +#define RP1_VIDEO_OUT_DPI_BASE 0x148000
  98 +#define RP1_XOSC_BASE 0x150000
  99 +#define RP1_WATCHDOG_BASE 0x154000
 100 +#define RP1_DMA_TICK_BASE 0x158000
 101 +#define RP1_SDIO_CLOCKS_BASE 0x15c000
 102 +#define RP1_USBHOST0_APBS_BASE 0x160000
 103 +#define RP1_USBHOST1_APBS_BASE 0x164000
 104 +#define RP1_ROSC0_BASE 0x168000
 105 +#define RP1_ROSC1_BASE 0x16c000
 106 +#define RP1_VBUSCTRL_BASE 0x170000
 107 +#define RP1_TICKS_BASE 0x174000
 108 +#define RP1_PIO_APBS_BASE 0x178000
 109 +#define RP1_SDIO0_AHBLS_BASE 0x180000
 110 +#define RP1_SDIO1_AHBLS_BASE 0x184000
 111 +#define RP1_DMA_BASE 0x188000
 112 +#define RP1_RAM_BASE 0x1c0000
 113 +#define RP1_RAM_SIZE 0x020000
 114 +#define RP1_USBHOST0_AXIS_BASE 0x200000
 115 +#define RP1_USBHOST1_AXIS_BASE 0x300000
 116 +#define RP1_EXAC_BASE 0x400000
 117 +
 118 +/* Interrupts */
 119 +
 120 +#define RP1_INT_IO_BANK0 0
 121 +#define RP1_INT_IO_BANK1 1
 122 +#define RP1_INT_IO_BANK2 2
 123 +#define RP1_INT_AUDIO_IN 3
 124 +#define RP1_INT_AUDIO_OUT 4
 125 +#define RP1_INT_PWM0 5
 126 +#define RP1_INT_ETH 6
 127 +#define RP1_INT_I2C0 7
 128 +#define RP1_INT_I2C1 8
 129 +#define RP1_INT_I2C2 9
 130 +#define RP1_INT_I2C3 10
 131 +#define RP1_INT_I2C4 11
 132 +#define RP1_INT_I2C5 12
 133 +#define RP1_INT_I2C6 13
 134 +#define RP1_INT_I2S0 14
 135 +#define RP1_INT_I2S1 15
 136 +#define RP1_INT_I2S2 16
 137 +#define RP1_INT_SDIO0 17
 138 +#define RP1_INT_SDIO1 18
 139 +#define RP1_INT_SPI0 19
 140 +#define RP1_INT_SPI1 20
 141 +#define RP1_INT_SPI2 21
 142 +#define RP1_INT_SPI3 22
 143 +#define RP1_INT_SPI4 23
 144 +#define RP1_INT_SPI5 24
 145 +#define RP1_INT_UART0 25
 146 +#define RP1_INT_TIMER_0 26
 147 +#define RP1_INT_TIMER_1 27
 148 +#define RP1_INT_TIMER_2 28
 149 +#define RP1_INT_TIMER_3 29
 150 +#define RP1_INT_USBHOST0 30
 151 +#define RP1_INT_USBHOST0_0 31
 152 +#define RP1_INT_USBHOST0_1 32
 153 +#define RP1_INT_USBHOST0_2 33
 154 +#define RP1_INT_USBHOST0_3 34
 155 +#define RP1_INT_USBHOST1 35
 156 +#define RP1_INT_USBHOST1_0 36
 157 +#define RP1_INT_USBHOST1_1 37
 158 +#define RP1_INT_USBHOST1_2 38
 159 +#define RP1_INT_USBHOST1_3 39
 160 +#define RP1_INT_DMA 40
 161 +#define RP1_INT_PWM1 41
 162 +#define RP1_INT_UART1 42
 163 +#define RP1_INT_UART2 43
 164 +#define RP1_INT_UART3 44
 165 +#define RP1_INT_UART4 45
 166 +#define RP1_INT_UART5 46
 167 +#define RP1_INT_MIPI0 47
 168 +#define RP1_INT_MIPI1 48
 169 +#define RP1_INT_VIDEO_OUT 49
 170 +#define RP1_INT_PIO_0 50
 171 +#define RP1_INT_PIO_1 51
 172 +#define RP1_INT_ADC_FIFO 52
 173 +#define RP1_INT_PCIE_OUT 53
 174 +#define RP1_INT_SPI6 54
 175 +#define RP1_INT_SPI7 55
 176 +#define RP1_INT_SPI8 56
 177 +#define RP1_INT_SYSCFG 58
 178 +#define RP1_INT_CLOCKS_DEFAULT 59
 179 +#define RP1_INT_VBUSCTRL 60
 180 +#define RP1_INT_PROC_MISC 57
 181 +#define RP1_INT_END 61
 182 +
 183 +/* DMA peripherals (for pacing) */
 184 +#define RP1_DMA_I2C0_RX 0x0
 185 +#define RP1_DMA_I2C0_TX 0x1
 186 +#define RP1_DMA_I2C1_RX 0x2
 187 +#define RP1_DMA_I2C1_TX 0x3
 188 +#define RP1_DMA_I2C2_RX 0x4
 189 +#define RP1_DMA_I2C2_TX 0x5
 190 +#define RP1_DMA_I2C3_RX 0x6
 191 +#define RP1_DMA_I2C3_TX 0x7
 192 +#define RP1_DMA_I2C4_RX 0x8
 193 +#define RP1_DMA_I2C4_TX 0x9
 194 +#define RP1_DMA_I2C5_RX 0xa
 195 +#define RP1_DMA_I2C5_TX 0xb
 196 +#define RP1_DMA_SPI0_RX 0xc
 197 +#define RP1_DMA_SPI0_TX 0xd
 198 +#define RP1_DMA_SPI1_RX 0xe
 199 +#define RP1_DMA_SPI1_TX 0xf
 200 +#define RP1_DMA_SPI2_RX 0x10
 201 +#define RP1_DMA_SPI2_TX 0x11
 202 +#define RP1_DMA_SPI3_RX 0x12
 203 +#define RP1_DMA_SPI3_TX 0x13
 204 +#define RP1_DMA_SPI4_RX 0x14
 205 +#define RP1_DMA_SPI4_TX 0x15
 206 +#define RP1_DMA_SPI5_RX 0x16
 207 +#define RP1_DMA_SPI5_TX 0x17
 208 +#define RP1_DMA_PWM0 0x18
 209 +#define RP1_DMA_UART0_RX 0x19
 210 +#define RP1_DMA_UART0_TX 0x1a
 211 +#define RP1_DMA_AUDIO_IN_CH0 0x1b
 212 +#define RP1_DMA_AUDIO_IN_CH1 0x1c
 213 +#define RP1_DMA_AUDIO_OUT 0x1d
 214 +#define RP1_DMA_PWM1 0x1e
 215 +#define RP1_DMA_I2S0_RX 0x1f
 216 +#define RP1_DMA_I2S0_TX 0x20
 217 +#define RP1_DMA_I2S1_RX 0x21
 218 +#define RP1_DMA_I2S1_TX 0x22
 219 +#define RP1_DMA_I2S2_RX 0x23
 220 +#define RP1_DMA_I2S2_TX 0x24
 221 +#define RP1_DMA_UART1_RX 0x25
 222 +#define RP1_DMA_UART1_TX 0x26
 223 +#define RP1_DMA_UART2_RX 0x27
 224 +#define RP1_DMA_UART2_TX 0x28
 225 +#define RP1_DMA_UART3_RX 0x29
 226 +#define RP1_DMA_UART3_TX 0x2a
 227 +#define RP1_DMA_UART4_RX 0x2b
 228 +#define RP1_DMA_UART4_TX 0x2c
 229 +#define RP1_DMA_UART5_RX 0x2d
 230 +#define RP1_DMA_UART5_TX 0x2e
 231 +#define RP1_DMA_ADC 0x2f
 232 +#define RP1_DMA_DMA_TICK_TICK0 0x30
 233 +#define RP1_DMA_DMA_TICK_TICK1 0x31
 234 +#define RP1_DMA_SPI6_RX 0x32
 235 +#define RP1_DMA_SPI6_TX 0x33
 236 +#define RP1_DMA_SPI7_RX 0x34
 237 +#define RP1_DMA_SPI7_TX 0x35
 238 +#define RP1_DMA_SPI8_RX 0x36
 239 +#define RP1_DMA_SPI8_TX 0x37
 240 +#define RP1_DMA_PIO_CH0_TX 0x38
 241 +#define RP1_DMA_PIO_CH0_RX 0x39
 242 +#define RP1_DMA_PIO_CH1_TX 0x3a
 243 +#define RP1_DMA_PIO_CH1_RX 0x3b
 244 +#define RP1_DMA_PIO_CH2_TX 0x3c
 245 +#define RP1_DMA_PIO_CH2_RX 0x3d
 246 +#define RP1_DMA_PIO_CH3_TX 0x3e
 247 +#define RP1_DMA_PIO_CH3_RX 0x3f
 248 +
 249 +#endif