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bcm27xx: update 6.1 patches to latest version
[openwrt/staging/dangole.git] / target / linux / bcm27xx / patches-6.1 / 950-0867-PCI-brcmstb-Add-BCM2712-support.patch
1 From 29702857d1ab71243ea6c247dfe9b5bc43dd422f Mon Sep 17 00:00:00 2001
2 From: Jim Quinlan <james.quinlan@broadcom.com>
3 Date: Fri, 23 Jun 2023 10:40:57 -0400
4 Subject: [PATCH] PCI: brcmstb: Add BCM2712 support
5
6 PCI: brcmstb: differing register offsets on 2712
7
8 pcie-brcmstb: Add 2712 bridge reset support
9
10 pcie: 2712 PORT_MASK and rescal support
11
12 pcie-brcmstb: don't alter the L1SS debug register
13
14 For reasons unknown, this disables the reference clock
15
16 pcie-brcmstb: fix BAR2 enable and window decode
17
18 Set UBUS ACCESS_EN to let inbound DMA work. Also BCM2712 has grown
19 an index in the inbound window size decode register.
20
21 PCIe: brcmstb: Enable support for 64 MSI-Xs
22
23 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
24
25 pcie-brcmstb: Suppress read error responses
26
27 If the link is down or the EP fails to return a read completion, the
28 RC's default behaviour is to return an AXI error. This causes fatal
29 exceptions on A76, so it's better to respond with all 1s instead.
30
31 pcie-brcmstb: increase UBUS timeout to cater for link retrain events
32
33 pcie-brcmstb: Handle additional inbound regions
34
35 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
36
37 pcie-brcmstb: Add support for external MSI controller
38
39 pcie-brcmstb: add a reasonable default traffic class to priority map
40
41 BCM2712 supports multiple traffic classes (TCs) with independent
42 maximally sized transfer queues for each TC. Traffic classes have no
43 transaction ordering requirements between them, which facilitates
44 out-of-order completions and arbitration between posted writes for
45 data streams that have no dependence on each other.
46
47 In addition to the above benefits of splitting endpoint traffic into
48 individual queues, priorities can be assigned to traffic classes by
49 a heuristic or deterministic mechanism. The heuristic elevates AXI
50 QOS priority in accordance with the number of pending transfers in
51 each TC's queue, but for true priority signalling a forwarding
52 mechanism using vendor-defined messages is implemented.
53
54 Receipt of a 3 DWORD VDM assigns a priority tag to a TC on-the-fly,
55 and this tag corresponds to a configurable AXI QOS value.
56
57 As a simple baseline, assign a linear map of AXI QOS to each tag.
58
59 pcie: brcmstb: set up the VDM forwarding interface when setting up QoS
60
61 pcie-brcmstb: add DT bindings for MPS-size Read Completion Mode
62
63 This controller has an optional feature that allows read completion
64 TLPs to be sized up to the Maximum Packet Size of a configured link.
65
66 This can exceed the Read Completion Boundary of 128B specified in
67 the PCIe specification, but depending on endpoint support may increase
68 link read bandwidth significantly.
69
70 pcie-brcmstb: clean up debug messages
71
72 pcie-brcmstb: fix BCM2712A0 PHY PM errata
73
74 The power management clock is 54MHz not 50MHz, so adjust the PM clock period
75 to suit. Powering off the PHY PLL in L1.2 is unsafe, so force it on.
76
77 pcie-brcmstb: set CLKREQ functionality according to link partner support
78
79 The RC supports either L1 with clock PM or L1 sub-state control, not both
80 at the same time. Examine the link partner's capabilities to determine
81 which is the most suitable scheme to use.
82
83 pcie: brcmstb: don't reset block bridges in suspend or removal cases
84
85 BCM2712 has a single rescal block for all three root complexes, and
86 holding PCIE1's bridge in reset will hang the chip if a different
87 RC wants to access any of the rescal registers.
88
89 pcie: brcmstb: guard 2712-specific setup with a RC type check
90
91 BCM2711 doesn't implement the UBUS control registers.
92
93 pcie: brcmstb: On 2712 keeping the PLL powered in L1.x is not required
94
95 A separate misconfiguration when enabling SSC (the MDIO registers no
96 longer do the same thing on BCM2712) had the side-effect of breaking
97 PLL powerdown and resume sequencing.
98
99 Allow entry into a true L1.2 state where analogue is depowered.
100
101 pcie: brcmstb: Fix reset warning on probe failure
102
103 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
104
105 bcm2712: pcie: adjust PHY PLL setup to use a 54MHz input refclk
106
107 Use canned MDIO writes from Broadcom that switch the ref_clk output
108 pair to run from the internal fractional PLL, and set the internal PLL
109 to expect a 54MHz input reference clock.
110
111 Gen3 operation is not guaranteed to be stable in this setup, so default
112 to gen2.
113
114 This only works if the LCPLL is bypassed (requires latest bootloader).
115
116 pcie: brcmstb: add missing register writes
117
118 drivers: pcie: brcmstb: cater for BCM2712C0 bug dropping QoS on the floor
119
120 The AXI QoS value extracted from the request fifo ends up as zero forever.
121 Disabling this means that "panic" signalling doesn't do anything useful,
122 but static priorites do work.
123
124 Also align the selected TC:QoS map with RP1's expectations of service.
125
126 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
127
128 drivers: pcie: brcmstb: shuffle TC priorities up to 8
129
130 Use the range 8-11 which puts the highest below HVS but leaves space
131 below for other 2712 masters.
132
133 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
134
135 drivers: pcie: brcmstb: optionally enable QoS features by DT for BCM2712
136
137 It's a bad idea to universally enable "realtime" priorities for TCs
138 across all the RC instances on the chip. Endpoints other than RP1 may
139 make use of these, so you don't want e.g. NVMe descriptor fetches getting
140 higher priority than your remote display.
141
142 Add two optional DT properties controlling the behaviour - FIFO-based
143 backpressure QoS or "message-based". Message-based signalling is
144 fundamentally broken due to a chip bug, so it collapses into a set of
145 static assignments that RP1 needs.
146
147 The default if neither property is specified is to assign everything a
148 QoS of 0.
149
150 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
151
152 drivers: pcie: brcmstb: adjust completion timeouts for bcm2712
153
154 Setting the RC config retry timeout makes CRS auto-polling work, but
155 the UBUS timeout will override the config retry. Both need to be large.
156
157 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
158 ---
159 drivers/pci/controller/pcie-brcmstb.c | 507 +++++++++++++++++++++++---
160 1 file changed, 458 insertions(+), 49 deletions(-)
161
162 --- a/drivers/pci/controller/pcie-brcmstb.c
163 +++ b/drivers/pci/controller/pcie-brcmstb.c
164 @@ -13,6 +13,7 @@
165 #include <linux/irqchip/chained_irq.h>
166 #include <linux/irqdomain.h>
167 #include <linux/kernel.h>
168 +#include <linux/kthread.h>
169 #include <linux/list.h>
170 #include <linux/log2.h>
171 #include <linux/module.h>
172 @@ -47,11 +48,25 @@
173 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
174 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
175
176 +#define PCIE_RC_TL_VDM_CTL0 0x0a20
177 +#define PCIE_RC_TL_VDM_CTL0_VDM_ENABLED_MASK 0x10000
178 +#define PCIE_RC_TL_VDM_CTL0_VDM_IGNORETAG_MASK 0x20000
179 +#define PCIE_RC_TL_VDM_CTL0_VDM_IGNOREVNDRID_MASK 0x40000
180 +
181 +#define PCIE_RC_TL_VDM_CTL1 0x0a0c
182 +#define PCIE_RC_TL_VDM_CTL1_VDM_VNDRID0_MASK 0x0000ffff
183 +#define PCIE_RC_TL_VDM_CTL1_VDM_VNDRID1_MASK 0xffff0000
184 +
185 #define PCIE_RC_DL_MDIO_ADDR 0x1100
186 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
187 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
188
189 +#define PCIE_RC_PL_PHY_CTL_15 0x184c
190 +#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000
191 +#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff
192 +
193 #define PCIE_MISC_MISC_CTRL 0x4008
194 +#define PCIE_MISC_MISC_CTRL_RCB_MPS_MODE_MASK 0x400
195 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
196 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
197 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
198 @@ -71,6 +86,7 @@
199
200 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
201 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
202 +#define PCIE_MISC_RC_BAR1_CONFIG_HI 0x4030
203
204 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
205 #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
206 @@ -78,6 +94,7 @@
207
208 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
209 #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
210 +#define PCIE_MISC_RC_BAR3_CONFIG_HI 0x4040
211
212 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
213 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
214 @@ -86,12 +103,15 @@
215 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
216 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
217
218 +#define PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT 0x405c
219 +
220 #define PCIE_MISC_PCIE_CTRL 0x4064
221 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
222 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
223
224 #define PCIE_MISC_PCIE_STATUS 0x4068
225 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
226 +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK_2712 0x40
227 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
228 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
229 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
230 @@ -116,14 +136,73 @@
231 #define PCIE_MEM_WIN0_LIMIT_HI(win) \
232 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
233
234 -#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
235 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG pcie->reg_offsets[PCIE_HARD_DEBUG]
236 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
237 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
238 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
239 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK 0x00200000
240
241 +#define PCIE_MISC_CTRL_1 0x40A0
242 +#define PCIE_MISC_CTRL_1_OUTBOUND_TC_MASK 0xf
243 +#define PCIE_MISC_CTRL_1_OUTBOUND_NO_SNOOP_MASK BIT(3)
244 +#define PCIE_MISC_CTRL_1_OUTBOUND_RO_MASK BIT(4)
245 +#define PCIE_MISC_CTRL_1_EN_VDM_QOS_CONTROL_MASK BIT(5)
246 +
247 +#define PCIE_MISC_UBUS_CTRL 0x40a4
248 +#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK BIT(13)
249 +#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK BIT(19)
250 +
251 +#define PCIE_MISC_UBUS_TIMEOUT 0x40A8
252 +
253 +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac
254 +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_ENABLE_MASK BIT(0)
255 +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_HI 0x40b0
256 +
257 +#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP 0x40b4
258 +#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK BIT(0)
259 +
260 +/* Additional RC BARs */
261 +#define PCIE_MISC_RC_BAR_CONFIG_LO_SIZE_MASK 0x1f
262 +#define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4
263 +#define PCIE_MISC_RC_BAR4_CONFIG_HI 0x40d8
264 +/* ... */
265 +#define PCIE_MISC_RC_BAR10_CONFIG_LO 0x4104
266 +#define PCIE_MISC_RC_BAR10_CONFIG_HI 0x4108
267 +
268 +#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE 0x1
269 +#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK 0xfffff000
270 +#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK 0xff
271 +#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO 0x410c
272 +#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI 0x4110
273 +/* ... */
274 +#define PCIE_MISC_UBUS_BAR10_CONFIG_REMAP_LO 0x413c
275 +#define PCIE_MISC_UBUS_BAR10_CONFIG_REMAP_HI 0x4140
276 +
277 +/* AXI priority forwarding - automatic level-based */
278 +#define PCIE_MISC_TC_QUEUE_TO_QOS_MAP(x) (0x4160 - (x) * 4)
279 +/* Defined in quarter-fullness */
280 +#define QUEUE_THRESHOLD_34_TO_QOS_MAP_SHIFT 12
281 +#define QUEUE_THRESHOLD_23_TO_QOS_MAP_SHIFT 8
282 +#define QUEUE_THRESHOLD_12_TO_QOS_MAP_SHIFT 4
283 +#define QUEUE_THRESHOLD_01_TO_QOS_MAP_SHIFT 0
284 +#define QUEUE_THRESHOLD_MASK 0xf
285 +
286 +/* VDM messages indexing TCs to AXI priorities */
287 +/* Indexes 8-15 */
288 +#define PCIE_MISC_VDM_PRIORITY_TO_QOS_MAP_HI 0x4164
289 +/* Indexes 0-7 */
290 +#define PCIE_MISC_VDM_PRIORITY_TO_QOS_MAP_LO 0x4168
291 +#define VDM_PRIORITY_TO_QOS_MAP_SHIFT(x) (4 * (x))
292 +#define VDM_PRIORITY_TO_QOS_MAP_MASK 0xf
293 +
294 +#define PCIE_MISC_AXI_INTF_CTRL 0x416C
295 +#define AXI_REQFIFO_EN_QOS_PROPAGATION BIT(7)
296 +#define AXI_BRIDGE_LOW_LATENCY_MODE BIT(6)
297 +#define AXI_MASTER_MAX_OUTSTANDING_REQUESTS_MASK 0x3f
298
299 -#define PCIE_INTR2_CPU_BASE 0x4300
300 +#define PCIE_MISC_AXI_READ_ERROR_DATA 0x4170
301 +
302 +#define PCIE_INTR2_CPU_BASE (pcie->reg_offsets[INTR2_CPU])
303 #define PCIE_MSI_INTR2_BASE 0x4500
304 /* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
305 #define MSI_INT_STATUS 0x0
306 @@ -197,6 +276,8 @@ enum {
307 RGR1_SW_INIT_1,
308 EXT_CFG_INDEX,
309 EXT_CFG_DATA,
310 + PCIE_HARD_DEBUG,
311 + INTR2_CPU,
312 };
313
314 enum {
315 @@ -211,6 +292,7 @@ enum pcie_type {
316 BCM4908,
317 BCM7278,
318 BCM2711,
319 + BCM2712,
320 };
321
322 struct pcie_cfg_data {
323 @@ -218,6 +300,7 @@ struct pcie_cfg_data {
324 const enum pcie_type type;
325 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
326 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
327 + bool (*rc_mode)(struct brcm_pcie *pcie);
328 };
329
330 struct subdev_regulators {
331 @@ -234,7 +317,7 @@ struct brcm_msi {
332 struct mutex lock; /* guards the alloc/free operations */
333 u64 target_addr;
334 int irq;
335 - DECLARE_BITMAP(used, BRCM_INT_PCI_MSI_NR);
336 + DECLARE_BITMAP(used, 64);
337 bool legacy;
338 /* Some chips have MSIs in bits [31..24] of a shared register. */
339 int legacy_shift;
340 @@ -251,6 +334,7 @@ struct brcm_pcie {
341 struct device_node *np;
342 bool ssc;
343 bool l1ss;
344 + bool rcb_mps_mode;
345 int gen;
346 u64 msi_target_addr;
347 struct brcm_msi *msi;
348 @@ -258,11 +342,14 @@ struct brcm_pcie {
349 enum pcie_type type;
350 struct reset_control *rescal;
351 struct reset_control *perst_reset;
352 + struct reset_control *bridge_reset;
353 int num_memc;
354 u64 memc_size[PCIE_BRCM_MAX_MEMC];
355 u32 hw_rev;
356 + u32 qos_map;
357 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
358 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
359 + bool (*rc_mode)(struct brcm_pcie *pcie);
360 struct subdev_regulators *sr;
361 bool ep_wakeup_capable;
362 };
363 @@ -283,8 +370,8 @@ static int brcm_pcie_encode_ibar_size(u6
364 if (log2_in >= 12 && log2_in <= 15)
365 /* Covers 4KB to 32KB (inclusive) */
366 return (log2_in - 12) + 0x1c;
367 - else if (log2_in >= 16 && log2_in <= 35)
368 - /* Covers 64KB to 32GB, (inclusive) */
369 + else if (log2_in >= 16 && log2_in <= 36)
370 + /* Covers 64KB to 64GB, (inclusive) */
371 return log2_in - 15;
372 /* Something is awry so disable */
373 return 0;
374 @@ -381,6 +468,35 @@ static int brcm_pcie_set_ssc(struct brcm
375 return ssc && pll ? 0 : -EIO;
376 }
377
378 +static void brcm_pcie_munge_pll(struct brcm_pcie *pcie)
379 +{
380 + //print "MDIO block 0x1600 written per Dannys instruction"
381 + //tmp = pcie_mdio_write(phyad, &h16&, &h50b9&)
382 + //tmp = pcie_mdio_write(phyad, &h17&, &hbd1a&)
383 + //tmp = pcie_mdio_write(phyad, &h1b&, &h5030&)
384 + //tmp = pcie_mdio_write(phyad, &h1e&, &h0007&)
385 +
386 + u32 tmp;
387 + int ret, i;
388 + u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e };
389 + u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 };
390 +
391 + ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
392 + 0x1600);
393 + for (i = 0; i < ARRAY_SIZE(regs); i++) {
394 + brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp);
395 + dev_dbg(pcie->dev, "PCIE MDIO pre_refclk 0x%02x = 0x%04x\n",
396 + regs[i], tmp);
397 + }
398 + for (i = 0; i < ARRAY_SIZE(regs); i++) {
399 + brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]);
400 + brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp);
401 + dev_dbg(pcie->dev, "PCIE MDIO post_refclk 0x%02x = 0x%04x\n",
402 + regs[i], tmp);
403 + }
404 + usleep_range(100, 200);
405 +}
406 +
407 /* Limits operation to a specific generation (1, 2, or 3) */
408 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
409 {
410 @@ -438,6 +554,97 @@ static void brcm_pcie_set_outbound_win(s
411 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
412 }
413
414 +static void brcm_pcie_set_tc_qos(struct brcm_pcie *pcie)
415 +{
416 + int i;
417 + u32 reg;
418 +
419 + if (pcie->type != BCM2712)
420 + return;
421 +
422 + /* XXX: BCM2712C0 is broken, disable the forwarding search */
423 + reg = readl(pcie->base + PCIE_MISC_AXI_INTF_CTRL);
424 + reg &= ~AXI_REQFIFO_EN_QOS_PROPAGATION;
425 + writel(reg, pcie->base + PCIE_MISC_AXI_INTF_CTRL);
426 +
427 + /* Disable VDM reception by default - QoS map defaults to 0 */
428 + reg = readl(pcie->base + PCIE_MISC_CTRL_1);
429 + reg &= ~PCIE_MISC_CTRL_1_EN_VDM_QOS_CONTROL_MASK;
430 + writel(reg, pcie->base + PCIE_MISC_CTRL_1);
431 +
432 + if (!of_property_read_u32(pcie->np, "brcm,fifo-qos-map", &pcie->qos_map)) {
433 + /*
434 + * Backpressure mode - bottom 4 nibbles are QoS for each
435 + * quartile of FIFO level. Each TC gets the same map, because
436 + * this mode is intended for nonrealtime EPs.
437 + */
438 +
439 + pcie->qos_map &= 0x0000ffff;
440 + for (i = 0; i < 8; i++)
441 + writel(pcie->qos_map, pcie->base + PCIE_MISC_TC_QUEUE_TO_QOS_MAP(i));
442 +
443 + return;
444 + }
445 +
446 + if (!of_property_read_u32(pcie->np, "brcm,vdm-qos-map", &pcie->qos_map)) {
447 +
448 + reg = readl(pcie->base + PCIE_MISC_CTRL_1);
449 + reg |= PCIE_MISC_CTRL_1_EN_VDM_QOS_CONTROL_MASK;
450 + writel(reg, pcie->base + PCIE_MISC_CTRL_1);
451 +
452 + /* No forwarding means no point separating panic priorities from normal */
453 + writel(pcie->qos_map, pcie->base + PCIE_MISC_VDM_PRIORITY_TO_QOS_MAP_LO);
454 + writel(pcie->qos_map, pcie->base + PCIE_MISC_VDM_PRIORITY_TO_QOS_MAP_HI);
455 +
456 + /* Match Vendor ID of 0 */
457 + writel(0, pcie->base + PCIE_RC_TL_VDM_CTL1);
458 + /* Forward VDMs to priority interface - at least the rx counters work */
459 + reg = readl(pcie->base + PCIE_RC_TL_VDM_CTL0);
460 + reg |= PCIE_RC_TL_VDM_CTL0_VDM_ENABLED_MASK |
461 + PCIE_RC_TL_VDM_CTL0_VDM_IGNORETAG_MASK |
462 + PCIE_RC_TL_VDM_CTL0_VDM_IGNOREVNDRID_MASK;
463 + writel(reg, pcie->base + PCIE_RC_TL_VDM_CTL0);
464 + }
465 +}
466 +
467 +static void brcm_pcie_config_clkreq(struct brcm_pcie *pcie)
468 +{
469 + void __iomem *base = pcie->base;
470 + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
471 + int domain = pci_domain_nr(bridge->bus);
472 + const struct pci_bus *bus = pci_find_bus(domain, 1);
473 + struct pci_dev *pdev = (struct pci_dev *)bus->devices.next;
474 + u32 tmp, link_cap = 0;
475 + u16 link_ctl = 0;
476 + int clkpm = 0;
477 + int substates = 0;
478 +
479 + pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
480 + if ((link_cap & PCI_EXP_LNKCAP_CLKPM))
481 + clkpm = 1;
482 +
483 + pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctl);
484 + if (!(link_ctl & PCI_EXP_LNKCTL_CLKREQ_EN))
485 + clkpm = 0;
486 +
487 + if (pcie->l1ss && pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS))
488 + substates = 1;
489 +
490 + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
491 + tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
492 + tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
493 +
494 + if (substates)
495 + tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
496 + else if (clkpm)
497 + tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
498 +
499 + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
500 +
501 + if (substates || clkpm)
502 + dev_info(pcie->dev, "clkreq control enabled\n");
503 +}
504 +
505 static struct irq_chip brcm_msi_irq_chip = {
506 .name = "BRCM STB PCIe MSI",
507 .irq_ack = irq_chip_ack_parent,
508 @@ -455,7 +662,7 @@ static struct msi_domain_info brcm_msi_d
509 static void brcm_pcie_msi_isr(struct irq_desc *desc)
510 {
511 struct irq_chip *chip = irq_desc_get_chip(desc);
512 - unsigned long status;
513 + unsigned long status, virq;
514 struct brcm_msi *msi;
515 struct device *dev;
516 u32 bit;
517 @@ -467,10 +674,22 @@ static void brcm_pcie_msi_isr(struct irq
518 status = readl(msi->intr_base + MSI_INT_STATUS);
519 status >>= msi->legacy_shift;
520
521 - for_each_set_bit(bit, &status, msi->nr) {
522 - int ret;
523 - ret = generic_handle_domain_irq(msi->inner_domain, bit);
524 - if (ret)
525 + for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR/*msi->nr*/) {
526 + bool found = false;
527 +
528 + virq = irq_find_mapping(msi->inner_domain, bit);
529 + if (virq) {
530 + found = true;
531 + dev_dbg(dev, "MSI -> %ld\n", virq);
532 + generic_handle_irq(virq);
533 + }
534 + virq = irq_find_mapping(msi->inner_domain, bit + 32);
535 + if (virq) {
536 + found = true;
537 + dev_dbg(dev, "MSI -> %ld\n", virq);
538 + generic_handle_irq(virq);
539 + }
540 + if (!found)
541 dev_dbg(dev, "unexpected MSI\n");
542 }
543
544 @@ -483,7 +702,7 @@ static void brcm_msi_compose_msi_msg(str
545
546 msg->address_lo = lower_32_bits(msi->target_addr);
547 msg->address_hi = upper_32_bits(msi->target_addr);
548 - msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq;
549 + msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | (data->hwirq & 0x1f);
550 }
551
552 static int brcm_msi_set_affinity(struct irq_data *irq_data,
553 @@ -495,7 +714,7 @@ static int brcm_msi_set_affinity(struct
554 static void brcm_msi_ack_irq(struct irq_data *data)
555 {
556 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
557 - const int shift_amt = data->hwirq + msi->legacy_shift;
558 + const int shift_amt = (data->hwirq & 0x1f) + msi->legacy_shift;
559
560 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR);
561 }
562 @@ -653,7 +872,7 @@ static int brcm_pcie_enable_msi(struct b
563 msi->legacy_shift = 24;
564 } else {
565 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
566 - msi->nr = BRCM_INT_PCI_MSI_NR;
567 + msi->nr = 64; //BRCM_INT_PCI_MSI_NR;
568 msi->legacy_shift = 0;
569 }
570
571 @@ -670,7 +889,7 @@ static int brcm_pcie_enable_msi(struct b
572 }
573
574 /* The controller is capable of serving in both RC and EP roles */
575 -static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
576 +static bool brcm_pcie_rc_mode_generic(struct brcm_pcie *pcie)
577 {
578 void __iomem *base = pcie->base;
579 u32 val = readl(base + PCIE_MISC_PCIE_STATUS);
580 @@ -678,6 +897,14 @@ static bool brcm_pcie_rc_mode(struct brc
581 return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val);
582 }
583
584 +static bool brcm_pcie_rc_mode_2712(struct brcm_pcie *pcie)
585 +{
586 + void __iomem *base = pcie->base;
587 + u32 val = readl(base + PCIE_MISC_PCIE_STATUS);
588 +
589 + return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK_2712, val) | 1; //XXX
590 +}
591 +
592 static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
593 {
594 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
595 @@ -749,6 +976,18 @@ static inline void brcm_pcie_bridge_sw_i
596 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
597 }
598
599 +static inline void brcm_pcie_bridge_sw_init_set_2712(struct brcm_pcie *pcie, u32 val)
600 +{
601 + if (WARN_ONCE(!pcie->bridge_reset,
602 + "missing bridge reset controller\n"))
603 + return;
604 +
605 + if (val)
606 + reset_control_assert(pcie->bridge_reset);
607 + else
608 + reset_control_deassert(pcie->bridge_reset);
609 +}
610 +
611 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
612 {
613 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
614 @@ -770,6 +1009,16 @@ static inline void brcm_pcie_perst_set_7
615 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
616 }
617
618 +static inline void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val)
619 +{
620 + u32 tmp;
621 +
622 + /* Perst bit has moved and assert value is 0 */
623 + tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
624 + u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK);
625 + writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
626 +}
627 +
628 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
629 {
630 u32 tmp;
631 @@ -796,6 +1045,8 @@ static inline int brcm_pcie_get_rc_bar2_
632 size += entry->res->end - entry->res->start + 1;
633 if (pcie_beg < lowest_pcie_addr)
634 lowest_pcie_addr = pcie_beg;
635 + if (pcie->type == BCM2711 || pcie->type == BCM2712)
636 + break; // Only consider the first entry
637 }
638
639 if (lowest_pcie_addr == ~(u64)0) {
640 @@ -866,6 +1117,30 @@ static inline int brcm_pcie_get_rc_bar2_
641 return 0;
642 }
643
644 +static int brcm_pcie_get_rc_bar_n(struct brcm_pcie *pcie,
645 + int idx,
646 + u64 *rc_bar_cpu,
647 + u64 *rc_bar_size,
648 + u64 *rc_bar_pci)
649 +{
650 + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
651 + struct resource_entry *entry;
652 + int i = 0;
653 +
654 + resource_list_for_each_entry(entry, &bridge->dma_ranges) {
655 + if (i == idx) {
656 + *rc_bar_cpu = entry->res->start;
657 + *rc_bar_size = entry->res->end - entry->res->start + 1;
658 + *rc_bar_pci = entry->res->start - entry->offset;
659 + return 0;
660 + }
661 +
662 + i++;
663 + }
664 +
665 + return -EINVAL;
666 +}
667 +
668 static int brcm_pcie_setup(struct brcm_pcie *pcie)
669 {
670 u64 rc_bar2_offset, rc_bar2_size;
671 @@ -874,11 +1149,14 @@ static int brcm_pcie_setup(struct brcm_p
672 struct resource_entry *entry;
673 u32 tmp, burst, aspm_support;
674 int num_out_wins = 0;
675 - int ret, memc;
676 + int ret, memc, count, i;
677
678 /* Reset the bridge */
679 pcie->bridge_sw_init_set(pcie, 1);
680 - pcie->perst_set(pcie, 1);
681 +
682 + /* Ensure that PERST# is asserted; some bootloaders may deassert it. */
683 + if (pcie->type == BCM2711)
684 + pcie->perst_set(pcie, 1);
685
686 usleep_range(100, 200);
687
688 @@ -894,6 +1172,17 @@ static int brcm_pcie_setup(struct brcm_p
689 /* Wait for SerDes to be stable */
690 usleep_range(100, 200);
691
692 + if (pcie->type == BCM2712) {
693 + /* Allow a 54MHz (xosc) refclk source */
694 + brcm_pcie_munge_pll(pcie);
695 + /* Fix for L1SS errata */
696 + tmp = readl(base + PCIE_RC_PL_PHY_CTL_15);
697 + tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK;
698 + /* PM clock period is 18.52ns (round down) */
699 + tmp |= 0x12;
700 + writel(tmp, base + PCIE_RC_PL_PHY_CTL_15);
701 + }
702 +
703 /*
704 * SCB_MAX_BURST_SIZE is a two bit field. For GENERIC chips it
705 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it
706 @@ -903,18 +1192,25 @@ static int brcm_pcie_setup(struct brcm_p
707 burst = 0x1; /* 256 bytes */
708 else if (pcie->type == BCM2711)
709 burst = 0x0; /* 128 bytes */
710 + else if (pcie->type == BCM2712)
711 + burst = 0x1; /* 128 bytes */
712 else if (pcie->type == BCM7278)
713 burst = 0x3; /* 512 bytes */
714 else
715 burst = 0x2; /* 512 bytes */
716
717 - /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
718 + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN, RCB_MPS_MODE */
719 tmp = readl(base + PCIE_MISC_MISC_CTRL);
720 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
721 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
722 u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
723 + if (pcie->rcb_mps_mode)
724 + u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_RCB_MPS_MODE_MASK);
725 + dev_info(pcie->dev, "setting SCB_ACCESS_EN, READ_UR_MODE, MAX_BURST_SIZE\n");
726 writel(tmp, base + PCIE_MISC_MISC_CTRL);
727
728 + brcm_pcie_set_tc_qos(pcie);
729 +
730 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
731 &rc_bar2_offset);
732 if (ret)
733 @@ -927,7 +1223,11 @@ static int brcm_pcie_setup(struct brcm_p
734 writel(upper_32_bits(rc_bar2_offset),
735 base + PCIE_MISC_RC_BAR2_CONFIG_HI);
736
737 + tmp = readl(base + PCIE_MISC_UBUS_BAR2_CONFIG_REMAP);
738 + u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK);
739 + writel(tmp, base + PCIE_MISC_UBUS_BAR2_CONFIG_REMAP);
740 tmp = readl(base + PCIE_MISC_MISC_CTRL);
741 +
742 for (memc = 0; memc < pcie->num_memc; memc++) {
743 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15;
744
745 @@ -938,8 +1238,32 @@ static int brcm_pcie_setup(struct brcm_p
746 else if (memc == 2)
747 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2));
748 }
749 +
750 writel(tmp, base + PCIE_MISC_MISC_CTRL);
751
752 + if (pcie->type == BCM2712) {
753 + /* Suppress AXI error responses and return 1s for read failures */
754 + tmp = readl(base + PCIE_MISC_UBUS_CTRL);
755 + u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK);
756 + u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK);
757 + writel(tmp, base + PCIE_MISC_UBUS_CTRL);
758 + writel(0xffffffff, base + PCIE_MISC_AXI_READ_ERROR_DATA);
759 +
760 + /*
761 + * Adjust timeouts. The UBUS timeout also affects CRS
762 + * completion retries, as the request will get terminated if
763 + * either timeout expires, so both have to be a large value
764 + * (in clocks of 750MHz).
765 + * Set UBUS timeout to 250ms, then set RC config retry timeout
766 + * to be ~240ms.
767 + *
768 + * Setting CRSVis=1 will stop the core from blocking on a CRS
769 + * response, but does require the device to be well-behaved...
770 + */
771 + writel(0xB2D0000, base + PCIE_MISC_UBUS_TIMEOUT);
772 + writel(0xABA0000, base + PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT);
773 + }
774 +
775 /*
776 * We ideally want the MSI target address to be located in the 32bit
777 * addressable memory area. Some devices might depend on it. This is
778 @@ -952,7 +1276,7 @@ static int brcm_pcie_setup(struct brcm_p
779 else
780 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
781
782 - if (!brcm_pcie_rc_mode(pcie)) {
783 + if (!pcie->rc_mode(pcie)) {
784 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n");
785 return -EINVAL;
786 }
787 @@ -976,6 +1300,38 @@ static int brcm_pcie_setup(struct brcm_p
788 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
789 writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
790
791 + /* program additional inbound windows (RC_BAR4..RC_BAR10) */
792 + count = (pcie->type == BCM2712) ? 7 : 0;
793 + for (i = 0; i < count; i++) {
794 + u64 bar_cpu, bar_size, bar_pci;
795 +
796 + ret = brcm_pcie_get_rc_bar_n(pcie, 1 + i, &bar_cpu, &bar_size,
797 + &bar_pci);
798 + if (ret)
799 + break;
800 +
801 + tmp = lower_32_bits(bar_pci);
802 + u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size),
803 + PCIE_MISC_RC_BAR_CONFIG_LO_SIZE_MASK);
804 + writel(tmp, base + PCIE_MISC_RC_BAR4_CONFIG_LO + i * 8);
805 + writel(upper_32_bits(bar_pci),
806 + base + PCIE_MISC_RC_BAR4_CONFIG_HI + i * 8);
807 +
808 + tmp = upper_32_bits(bar_cpu) &
809 + PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK;
810 + writel(tmp,
811 + base + PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI + i * 8);
812 + tmp = lower_32_bits(bar_cpu) &
813 + PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK;
814 + writel(tmp | PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE,
815 + base + PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + i * 8);
816 + }
817 +
818 + if (pcie->gen) {
819 + dev_info(pcie->dev, "Forcing gen %d\n", pcie->gen);
820 + brcm_pcie_set_gen(pcie, pcie->gen);
821 + }
822 +
823 /*
824 * For config space accesses on the RC, show the right class for
825 * a PCIe-PCIe bridge (the default setting is to be EP mode).
826 @@ -1031,7 +1387,6 @@ static int brcm_pcie_start_link(struct b
827 void __iomem *base = pcie->base;
828 u16 nlw, cls, lnksta;
829 bool ssc_good = false;
830 - u32 tmp;
831 int ret, i;
832
833 /* Unassert the fundamental reset */
834 @@ -1067,6 +1422,7 @@ static int brcm_pcie_start_link(struct b
835 dev_err(dev, "failed attempt to enter ssc mode\n");
836 }
837
838 +
839 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
840 cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
841 nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
842 @@ -1074,27 +1430,6 @@ static int brcm_pcie_start_link(struct b
843 pci_speed_string(pcie_link_speed[cls]), nlw,
844 ssc_good ? "(SSC)" : "(!SSC)");
845
846 - tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
847 - if (pcie->l1ss) {
848 - /*
849 - * Enable CLKREQ# signalling include L1 Substate control of
850 - * the CLKREQ# signal and the external reference clock buffer.
851 - * meet requirement for Endpoints that require CLKREQ#
852 - * assertion to clock active within 400ns.
853 - */
854 - tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
855 - tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
856 - } else {
857 - /*
858 - * Refclk from RC should be gated with CLKREQ# input when
859 - * ASPM L0s,L1 is enabled => setting the CLKREQ_DEBUG_ENABLE
860 - * field to 1.
861 - */
862 - tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
863 - tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
864 - }
865 - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
866 -
867 return 0;
868 }
869
870 @@ -1202,6 +1537,7 @@ static void brcm_pcie_enter_l23(struct b
871
872 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
873 {
874 +#if 0
875 static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
876 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT,
877 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT,
878 @@ -1234,6 +1570,9 @@ static int brcm_phy_cntl(struct brcm_pci
879 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop"));
880
881 return ret;
882 +#else
883 + return 0;
884 +#endif
885 }
886
887 static inline int brcm_phy_start(struct brcm_pcie *pcie)
888 @@ -1266,6 +1605,12 @@ static void brcm_pcie_turn_off(struct br
889 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
890 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
891
892 + /*
893 + * Shutting down this bridge on pcie1 means accesses to rescal block
894 + * will hang the chip if another RC wants to assert/deassert rescal.
895 + */
896 + if (pcie->type == BCM2712)
897 + return;
898 /* Shutdown PCIe bridge */
899 pcie->bridge_sw_init_set(pcie, 1);
900 }
901 @@ -1296,9 +1641,9 @@ static int brcm_pcie_suspend_noirq(struc
902 if (brcm_phy_stop(pcie))
903 dev_err(dev, "Could not stop phy for suspend\n");
904
905 - ret = reset_control_rearm(pcie->rescal);
906 + ret = reset_control_assert(pcie->rescal);
907 if (ret) {
908 - dev_err(dev, "Could not rearm rescal reset\n");
909 + dev_err(dev, "Could not assert rescal reset\n");
910 return ret;
911 }
912
913 @@ -1393,7 +1738,7 @@ err_regulator:
914 if (pcie->sr)
915 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
916 err_reset:
917 - reset_control_rearm(pcie->rescal);
918 + reset_control_assert(pcie->rescal);
919 err_disable_clk:
920 clk_disable_unprepare(pcie->clk);
921 return ret;
922 @@ -1405,8 +1750,8 @@ static void __brcm_pcie_remove(struct br
923 brcm_pcie_turn_off(pcie);
924 if (brcm_phy_stop(pcie))
925 dev_err(pcie->dev, "Could not stop phy\n");
926 - if (reset_control_rearm(pcie->rescal))
927 - dev_err(pcie->dev, "Could not rearm rescal reset\n");
928 + if (reset_control_assert(pcie->rescal))
929 + dev_err(pcie->dev, "Could not assert rescal reset\n");
930 clk_disable_unprepare(pcie->clk);
931 }
932
933 @@ -1426,12 +1771,16 @@ static const int pcie_offsets[] = {
934 [RGR1_SW_INIT_1] = 0x9210,
935 [EXT_CFG_INDEX] = 0x9000,
936 [EXT_CFG_DATA] = 0x9004,
937 + [PCIE_HARD_DEBUG] = 0x4204,
938 + [INTR2_CPU] = 0x4300,
939 };
940
941 static const int pcie_offsets_bmips_7425[] = {
942 [RGR1_SW_INIT_1] = 0x8010,
943 [EXT_CFG_INDEX] = 0x8300,
944 [EXT_CFG_DATA] = 0x8304,
945 + [PCIE_HARD_DEBUG] = 0x4204,
946 + [INTR2_CPU] = 0x4300,
947 };
948
949 static const struct pcie_cfg_data generic_cfg = {
950 @@ -1439,6 +1788,7 @@ static const struct pcie_cfg_data generi
951 .type = GENERIC,
952 .perst_set = brcm_pcie_perst_set_generic,
953 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
954 + .rc_mode = brcm_pcie_rc_mode_generic,
955 };
956
957 static const struct pcie_cfg_data bcm7425_cfg = {
958 @@ -1446,6 +1796,7 @@ static const struct pcie_cfg_data bcm742
959 .type = BCM7425,
960 .perst_set = brcm_pcie_perst_set_generic,
961 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
962 + .rc_mode = brcm_pcie_rc_mode_generic,
963 };
964
965 static const struct pcie_cfg_data bcm7435_cfg = {
966 @@ -1460,12 +1811,15 @@ static const struct pcie_cfg_data bcm490
967 .type = BCM4908,
968 .perst_set = brcm_pcie_perst_set_4908,
969 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
970 + .rc_mode = brcm_pcie_rc_mode_generic,
971 };
972
973 static const int pcie_offset_bcm7278[] = {
974 [RGR1_SW_INIT_1] = 0xc010,
975 [EXT_CFG_INDEX] = 0x9000,
976 [EXT_CFG_DATA] = 0x9004,
977 + [PCIE_HARD_DEBUG] = 0x4204,
978 + [INTR2_CPU] = 0x4300,
979 };
980
981 static const struct pcie_cfg_data bcm7278_cfg = {
982 @@ -1473,6 +1827,7 @@ static const struct pcie_cfg_data bcm727
983 .type = BCM7278,
984 .perst_set = brcm_pcie_perst_set_7278,
985 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
986 + .rc_mode = brcm_pcie_rc_mode_generic,
987 };
988
989 static const struct pcie_cfg_data bcm2711_cfg = {
990 @@ -1480,10 +1835,27 @@ static const struct pcie_cfg_data bcm271
991 .type = BCM2711,
992 .perst_set = brcm_pcie_perst_set_generic,
993 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
994 + .rc_mode = brcm_pcie_rc_mode_generic,
995 +};
996 +
997 +static const int pcie_offsets_bcm2712[] = {
998 + [EXT_CFG_INDEX] = 0x9000,
999 + [EXT_CFG_DATA] = 0x9004,
1000 + [PCIE_HARD_DEBUG] = 0x4304,
1001 + [INTR2_CPU] = 0x4400,
1002 +};
1003 +
1004 +static const struct pcie_cfg_data bcm2712_cfg = {
1005 + .offsets = pcie_offsets_bcm2712,
1006 + .type = BCM2712,
1007 + .perst_set = brcm_pcie_perst_set_2712,
1008 + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_2712,
1009 + .rc_mode = brcm_pcie_rc_mode_2712,
1010 };
1011
1012 static const struct of_device_id brcm_pcie_match[] = {
1013 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1014 + { .compatible = "brcm,bcm2712-pcie", .data = &bcm2712_cfg },
1015 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1016 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1017 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1018 @@ -1524,7 +1896,7 @@ static int brcm_pcie_probe(struct platfo
1019
1020 data = of_device_get_match_data(&pdev->dev);
1021 if (!data) {
1022 - pr_err("failed to look up compatible string\n");
1023 + dev_err(&pdev->dev, "failed to look up compatible string\n");
1024 return -EINVAL;
1025 }
1026
1027 @@ -1535,6 +1907,7 @@ static int brcm_pcie_probe(struct platfo
1028 pcie->type = data->type;
1029 pcie->perst_set = data->perst_set;
1030 pcie->bridge_sw_init_set = data->bridge_sw_init_set;
1031 + pcie->rc_mode = data->rc_mode;
1032
1033 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1034 if (IS_ERR(pcie->base))
1035 @@ -1549,6 +1922,7 @@ static int brcm_pcie_probe(struct platfo
1036
1037 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
1038 pcie->l1ss = of_property_read_bool(np, "brcm,enable-l1ss");
1039 + pcie->rcb_mps_mode = of_property_read_bool(np, "brcm,enable-mps-rcb");
1040
1041 ret = clk_prepare_enable(pcie->clk);
1042 if (ret) {
1043 @@ -1565,14 +1939,20 @@ static int brcm_pcie_probe(struct platfo
1044 clk_disable_unprepare(pcie->clk);
1045 return PTR_ERR(pcie->perst_reset);
1046 }
1047 + pcie->bridge_reset =
1048 + devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge");
1049 + if (IS_ERR(pcie->bridge_reset)) {
1050 + clk_disable_unprepare(pcie->clk);
1051 + return PTR_ERR(pcie->bridge_reset);
1052 + }
1053
1054 - ret = reset_control_reset(pcie->rescal);
1055 + ret = reset_control_deassert(pcie->rescal);
1056 if (ret)
1057 dev_err(&pdev->dev, "failed to deassert 'rescal'\n");
1058
1059 ret = brcm_phy_start(pcie);
1060 if (ret) {
1061 - reset_control_rearm(pcie->rescal);
1062 + reset_control_assert(pcie->rescal);
1063 clk_disable_unprepare(pcie->clk);
1064 return ret;
1065 }
1066 @@ -1595,6 +1975,33 @@ static int brcm_pcie_probe(struct platfo
1067 dev_err(pcie->dev, "probe of internal MSI failed");
1068 goto fail;
1069 }
1070 + } else if (pci_msi_enabled() && msi_np != pcie->np) {
1071 + /* Use RC_BAR1 for MIP access */
1072 + u64 msi_pci_addr;
1073 + u64 msi_phys_addr;
1074 +
1075 + if (of_property_read_u64(msi_np, "brcm,msi-pci-addr", &msi_pci_addr)) {
1076 + dev_err(pcie->dev, "Unable to find MSI PCI address\n");
1077 + ret = -EINVAL;
1078 + goto fail;
1079 + }
1080 +
1081 + if (of_property_read_u64(msi_np, "reg", &msi_phys_addr)) {
1082 + dev_err(pcie->dev, "Unable to find MSI physical address\n");
1083 + ret = -EINVAL;
1084 + goto fail;
1085 + }
1086 +
1087 + writel(lower_32_bits(msi_pci_addr) | brcm_pcie_encode_ibar_size(0x1000),
1088 + pcie->base + PCIE_MISC_RC_BAR1_CONFIG_LO);
1089 + writel(upper_32_bits(msi_pci_addr),
1090 + pcie->base + PCIE_MISC_RC_BAR1_CONFIG_HI);
1091 +
1092 + writel(lower_32_bits(msi_phys_addr) |
1093 + PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_ENABLE_MASK,
1094 + pcie->base + PCIE_MISC_UBUS_BAR1_CONFIG_REMAP);
1095 + writel(upper_32_bits(msi_phys_addr),
1096 + pcie->base + PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_HI);
1097 }
1098
1099 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops;
1100 @@ -1611,6 +2018,8 @@ static int brcm_pcie_probe(struct platfo
1101 return ret;
1102 }
1103
1104 + brcm_pcie_config_clkreq(pcie);
1105 +
1106 return 0;
1107
1108 fail:
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