target/linux/bcm27xx/patches-6.1/950-0859-mmc-brcmstb-add-support-for-BCM2712.patch

   1 From b627647c4500d39cb026924b608841fdf4d4d7e9 Mon Sep 17 00:00:00 2001
   2 From: Ulf Hansson <ulf.hansson@linaro.org>
   3 Date: Thu, 29 Oct 2020 09:57:16 +0800
   4 Subject: [PATCH] mmc: brcmstb: add support for BCM2712
   5
   6 BCM2712 has an SD Express capable SDHCI implementation and uses
   7 the SDIO CFG register block present on other STB chips.
   8
   9 Add plumbing for SD Express handover and BCM2712-specific functions.
  10
  11 Due to the common bus infrastructure between BCM2711 and BCM2712,
  12 the driver also needs to implement 32-bit IO accessors.
  13
  14 mmc: brcmstb: override card presence if broken-cd is set
  15
  16 Not just if the card is declared as nonremovable.
  17
  18 sdhci: brcmstb: align SD express switchover with SD spec v8.00
  19
  20 Part 1 of the Physical specification, figure 3-24, details the switch
  21 sequence for cards initially probed as SD. Add a missing check for DAT2
  22 level after switching VDD2 on.
  23
  24 sdhci: brcmstb: clean up SD Express probe and error handling
  25
  26 Refactor to avoid spurious error messages in dmesg if the requisite SD
  27 Express DT nodes aren't present.
  28
  29 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  30
  31 mmc: sdhci-brcmstb: only use the delay line PHY for tuneable speeds
  32
  33 The MMC core has a 200MHz core clock which allows the use of DDR50 and
  34 below without incremental phase tuning. SDR50/SDR104 and the EMMC HS200
  35 speeds require tuning.
  36
  37 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  38 ---
  39  drivers/mmc/host/Kconfig         |   2 +
  40  drivers/mmc/host/sdhci-brcmstb.c | 356 +++++++++++++++++++++++++++++++
  41  2 files changed, 358 insertions(+)
  42
  43 --- a/drivers/mmc/host/Kconfig
  44 +++ b/drivers/mmc/host/Kconfig
  45 @@ -1082,7 +1082,9 @@ config MMC_SDHCI_BRCMSTB
  46         tristate "Broadcom SDIO/SD/MMC support"
  47         depends on ARCH_BRCMSTB || BMIPS_GENERIC
  48         depends on MMC_SDHCI_PLTFM
  49 +       select MMC_SDHCI_IO_ACCESSORS
  50         select MMC_CQHCI
  51 +       select OF_DYNAMIC
  52         default y
  53         help
  54           This selects support for the SDIO/SD/MMC Host Controller on
  55 --- a/drivers/mmc/host/sdhci-brcmstb.c
  56 +++ b/drivers/mmc/host/sdhci-brcmstb.c
  57 @@ -11,6 +11,8 @@
  58  #include <linux/of.h>
  59  #include <linux/bitops.h>
  60  #include <linux/delay.h>
  61 +#include <linux/pinctrl/consumer.h>
  62 +#include <linux/regulator/consumer.h>
  63
  64  #include "sdhci-cqhci.h"
  65  #include "sdhci-pltfm.h"
  66 @@ -26,18 +28,43 @@
  67
  68  #define BRCMSTB_PRIV_FLAGS_HAS_CQE             BIT(0)
  69  #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK          BIT(1)
  70 +#define BRCMSTB_PRIV_FLAGS_HAS_SD_EXPRESS      BIT(2)
  71
  72  #define SDHCI_ARASAN_CQE_BASE_ADDR             0x200
  73
  74 +#define SDIO_CFG_CTRL                          0x0
  75 +#define  SDIO_CFG_CTRL_SDCD_N_TEST_EN          BIT(31)
  76 +#define  SDIO_CFG_CTRL_SDCD_N_TEST_LEV         BIT(30)
  77 +
  78 +#define SDIO_CFG_SD_PIN_SEL                    0x44
  79 +#define  SDIO_CFG_SD_PIN_SEL_MASK              0x3
  80 +#define  SDIO_CFG_SD_PIN_SEL_CARD              BIT(1)
  81 +
  82 +#define SDIO_CFG_MAX_50MHZ_MODE                        0x1ac
  83 +#define  SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE        BIT(31)
  84 +#define  SDIO_CFG_MAX_50MHZ_MODE_ENABLE                BIT(0)
  85 +
  86  struct sdhci_brcmstb_priv {
  87         void __iomem *cfg_regs;
  88         unsigned int flags;
  89         struct clk *base_clk;
  90         u32 base_freq_hz;
  91 +       u32 shadow_cmd;
  92 +       u32 shadow_blk;
  93 +       bool is_cmd_shadowed;
  94 +       bool is_blk_shadowed;
  95 +       struct regulator *sde_1v8;
  96 +       struct device_node *sde_pcie;
  97 +       void *__iomem sde_ioaddr;
  98 +       void *__iomem sde_ioaddr2;
  99 +       struct pinctrl *pinctrl;
 100 +       struct pinctrl_state *pins_default;
 101 +       struct pinctrl_state *pins_sdex;
 102  };
 103
 104  struct brcmstb_match_priv {
 105         void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
 106 +       void (*cfginit)(struct sdhci_host *host);
 107         struct sdhci_ops *ops;
 108         const unsigned int flags;
 109  };
 110 @@ -94,6 +121,124 @@ static void sdhci_brcmstb_set_clock(stru
 111         sdhci_enable_clk(host, clk);
 112  }
 113
 114 +#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
 115 +
 116 +static inline u32 sdhci_brcmstb_32only_readl(struct sdhci_host *host, int reg)
 117 +{
 118 +       u32 val = readl(host->ioaddr + reg);
 119 +
 120 +       pr_debug("%s: readl [0x%02x] 0x%08x\n",
 121 +                mmc_hostname(host->mmc), reg, val);
 122 +       return val;
 123 +}
 124 +
 125 +static u16 sdhci_brcmstb_32only_readw(struct sdhci_host *host, int reg)
 126 +{
 127 +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 128 +       struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
 129 +       u32 val;
 130 +       u16 word;
 131 +
 132 +       if ((reg == SDHCI_TRANSFER_MODE) && brcmstb_priv->is_cmd_shadowed) {
 133 +               /* Get the saved transfer mode */
 134 +               val = brcmstb_priv->shadow_cmd;
 135 +       } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
 136 +                  brcmstb_priv->is_blk_shadowed) {
 137 +               /* Get the saved block info */
 138 +               val = brcmstb_priv->shadow_blk;
 139 +       } else {
 140 +               val = sdhci_brcmstb_32only_readl(host, (reg & ~3));
 141 +       }
 142 +       word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
 143 +       return word;
 144 +}
 145 +
 146 +static u8 sdhci_brcmstb_32only_readb(struct sdhci_host *host, int reg)
 147 +{
 148 +       u32 val = sdhci_brcmstb_32only_readl(host, (reg & ~3));
 149 +       u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
 150 +       return byte;
 151 +}
 152 +
 153 +static inline void sdhci_brcmstb_32only_writel(struct sdhci_host *host, u32 val, int reg)
 154 +{
 155 +       pr_debug("%s: writel [0x%02x] 0x%08x\n",
 156 +                mmc_hostname(host->mmc), reg, val);
 157 +
 158 +       writel(val, host->ioaddr + reg);
 159 +}
 160 +
 161 +/*
 162 + * BCM2712 unfortunately carries with it a perennial bug with the SD controller
 163 + * register interface present on previous chips (2711/2709/2708). Accesses must
 164 + * be dword-sized and a read-modify-write cycle to the 32-bit registers
 165 + * containing the COMMAND, TRANSFER_MODE, BLOCK_SIZE and BLOCK_COUNT registers
 166 + * tramples the upper/lower 16 bits of data written. BCM2712 does not seem to
 167 + * need the extreme delay between each write as on previous chips, just the
 168 + * serialisation of writes to these registers in a single 32-bit operation.
 169 + */
 170 +static void sdhci_brcmstb_32only_writew(struct sdhci_host *host, u16 val, int reg)
 171 +{
 172 +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 173 +       struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
 174 +       u32 word_shift = REG_OFFSET_IN_BITS(reg);
 175 +       u32 mask = 0xffff << word_shift;
 176 +       u32 oldval, newval;
 177 +
 178 +       if (reg == SDHCI_COMMAND) {
 179 +               /* Write the block now as we are issuing a command */
 180 +               if (brcmstb_priv->is_blk_shadowed) {
 181 +                       sdhci_brcmstb_32only_writel(host, brcmstb_priv->shadow_blk,
 182 +                               SDHCI_BLOCK_SIZE);
 183 +                       brcmstb_priv->is_blk_shadowed = false;
 184 +               }
 185 +               oldval = brcmstb_priv->shadow_cmd;
 186 +               brcmstb_priv->is_cmd_shadowed = false;
 187 +       } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
 188 +                  brcmstb_priv->is_blk_shadowed) {
 189 +               /* Block size and count are stored in shadow reg */
 190 +               oldval = brcmstb_priv->shadow_blk;
 191 +       } else {
 192 +               /* Read reg, all other registers are not shadowed */
 193 +               oldval = sdhci_brcmstb_32only_readl(host, (reg & ~3));
 194 +       }
 195 +       newval = (oldval & ~mask) | (val << word_shift);
 196 +
 197 +       if (reg == SDHCI_TRANSFER_MODE) {
 198 +               /* Save the transfer mode until the command is issued */
 199 +               brcmstb_priv->shadow_cmd = newval;
 200 +               brcmstb_priv->is_cmd_shadowed = true;
 201 +       } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
 202 +               /* Save the block info until the command is issued */
 203 +               brcmstb_priv->shadow_blk = newval;
 204 +               brcmstb_priv->is_blk_shadowed = true;
 205 +       } else {
 206 +               /* Command or other regular 32-bit write */
 207 +               sdhci_brcmstb_32only_writel(host, newval, reg & ~3);
 208 +       }
 209 +}
 210 +
 211 +static void sdhci_brcmstb_32only_writeb(struct sdhci_host *host, u8 val, int reg)
 212 +{
 213 +       u32 oldval = sdhci_brcmstb_32only_readl(host, (reg & ~3));
 214 +       u32 byte_shift = REG_OFFSET_IN_BITS(reg);
 215 +       u32 mask = 0xff << byte_shift;
 216 +       u32 newval = (oldval & ~mask) | (val << byte_shift);
 217 +
 218 +       sdhci_brcmstb_32only_writel(host, newval, reg & ~3);
 219 +}
 220 +
 221 +static void sdhci_brcmstb_set_power(struct sdhci_host *host, unsigned char mode,
 222 +                                 unsigned short vdd)
 223 +{
 224 +       if (!IS_ERR(host->mmc->supply.vmmc)) {
 225 +               struct mmc_host *mmc = host->mmc;
 226 +
 227 +               mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 228 +       }
 229 +       sdhci_set_power_noreg(host, mode, vdd);
 230 +}
 231 +
 232  static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host,
 233                                             unsigned int timing)
 234  {
 235 @@ -123,6 +268,146 @@ static void sdhci_brcmstb_set_uhs_signal
 236         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 237  }
 238
 239 +static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host)
 240 +{
 241 +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 242 +       struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
 243 +       bool want_dll = false;
 244 +       u32 uhs_mask = (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104);
 245 +       u32 hsemmc_mask = (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS200_1_2V_SDR |
 246 +                          MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V);
 247 +       u32 reg;
 248 +
 249 +       if (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)) {
 250 +           if((host->mmc->caps & uhs_mask) || (host->mmc->caps2 & hsemmc_mask))
 251 +               want_dll = true;
 252 +       }
 253 +
 254 +       /*
 255 +        * If we want a speed that requires tuning,
 256 +        * then select the delay line PHY as the clock source.
 257 +        */
 258 +       if (want_dll) {
 259 +               reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE);
 260 +               reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE;
 261 +               reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE;
 262 +               writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE);
 263 +       }
 264 +
 265 +       if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
 266 +           (host->mmc->caps & MMC_CAP_NEEDS_POLL)) {
 267 +               /* Force presence */
 268 +               reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL);
 269 +               reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV;
 270 +               reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN;
 271 +               writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL);
 272 +       } else {
 273 +               /* Enable card detection line */
 274 +               reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL);
 275 +               reg &= ~SDIO_CFG_SD_PIN_SEL_MASK;
 276 +               reg |= SDIO_CFG_SD_PIN_SEL_CARD;
 277 +               writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL);
 278 +       }
 279 +}
 280 +
 281 +static int bcm2712_init_sd_express(struct sdhci_host *host, struct mmc_ios *ios)
 282 +{
 283 +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 284 +       struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
 285 +       struct device *dev = host->mmc->parent;
 286 +       u32 ctrl_val;
 287 +       u32 present_state;
 288 +       int ret;
 289 +
 290 +       if (!brcmstb_priv->sde_ioaddr || !brcmstb_priv->sde_ioaddr2)
 291 +               return -EINVAL;
 292 +
 293 +       if (!brcmstb_priv->pinctrl)
 294 +               return -EINVAL;
 295 +
 296 +       /* Turn off the SD clock first */
 297 +       sdhci_set_clock(host, 0);
 298 +
 299 +       /* Disable SD DAT0-3 pulls */
 300 +       pinctrl_select_state(brcmstb_priv->pinctrl, brcmstb_priv->pins_sdex);
 301 +
 302 +       ctrl_val = readl(brcmstb_priv->sde_ioaddr);
 303 +       dev_dbg(dev, "ctrl_val 1 %08x\n", ctrl_val);
 304 +
 305 +       /* Tri-state the SD pins */
 306 +       ctrl_val |= 0x1ff8;
 307 +       writel(ctrl_val, brcmstb_priv->sde_ioaddr);
 308 +       dev_dbg(dev, "ctrl_val 1->%08x (%08x)\n", ctrl_val, readl(brcmstb_priv->sde_ioaddr));
 309 +       /* Let voltages settle */
 310 +       udelay(100);
 311 +
 312 +       /* Enable the PCIe sideband pins */
 313 +       ctrl_val &= ~0x6000;
 314 +       writel(ctrl_val, brcmstb_priv->sde_ioaddr);
 315 +       dev_dbg(dev, "ctrl_val 1->%08x (%08x)\n", ctrl_val, readl(brcmstb_priv->sde_ioaddr));
 316 +       /* Let voltages settle */
 317 +       udelay(100);
 318 +
 319 +       /* Turn on the 1v8 VDD2 regulator */
 320 +       ret = regulator_enable(brcmstb_priv->sde_1v8);
 321 +       if (ret)
 322 +               return ret;
 323 +
 324 +       /* Wait for Tpvcrl */
 325 +       msleep(1);
 326 +
 327 +       /* Sample DAT2 (CLKREQ#) - if low, card is in PCIe mode */
 328 +       present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
 329 +       present_state = (present_state & SDHCI_DATA_LVL_MASK) >> SDHCI_DATA_LVL_SHIFT;
 330 +       dev_dbg(dev, "state = 0x%08x\n", present_state);
 331 +
 332 +       if (present_state & BIT(2)) {
 333 +               dev_err(dev, "DAT2 still high, abandoning SDex switch\n");
 334 +               return -ENODEV;
 335 +       }
 336 +
 337 +       /* Turn on the LCPLL PTEST mux */
 338 +       ctrl_val = readl(brcmstb_priv->sde_ioaddr2 + 20); // misc5
 339 +       ctrl_val &= ~(0x7 << 7);
 340 +       ctrl_val |= 3 << 7;
 341 +       writel(ctrl_val, brcmstb_priv->sde_ioaddr2 + 20);
 342 +       dev_dbg(dev, "misc 5->%08x (%08x)\n", ctrl_val, readl(brcmstb_priv->sde_ioaddr2 + 20));
 343 +
 344 +       /* PTEST diff driver enable */
 345 +       ctrl_val = readl(brcmstb_priv->sde_ioaddr2);
 346 +       ctrl_val |= BIT(21);
 347 +       writel(ctrl_val, brcmstb_priv->sde_ioaddr2);
 348 +
 349 +       dev_dbg(dev, "misc 0->%08x (%08x)\n", ctrl_val, readl(brcmstb_priv->sde_ioaddr2));
 350 +
 351 +       /* Wait for more than the minimum Tpvpgl time */
 352 +       msleep(100);
 353 +
 354 +       if (brcmstb_priv->sde_pcie) {
 355 +               struct of_changeset changeset;
 356 +               static struct property okay_property = {
 357 +                       .name = "status",
 358 +                       .value = "okay",
 359 +                       .length = 5,
 360 +               };
 361 +
 362 +               /* Enable the pcie controller */
 363 +               of_changeset_init(&changeset);
 364 +               ret = of_changeset_update_property(&changeset,
 365 +                                                  brcmstb_priv->sde_pcie,
 366 +                                                  &okay_property);
 367 +               if (ret) {
 368 +                       dev_err(dev, "%s: failed to update property - %d\n", __func__,
 369 +                              ret);
 370 +                       return -ENODEV;
 371 +               }
 372 +               ret = of_changeset_apply(&changeset);
 373 +       }
 374 +
 375 +       dev_dbg(dev, "%s -> %d\n", __func__, ret);
 376 +       return ret;
 377 +}
 378 +
 379  static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc)
 380  {
 381         sdhci_dumpregs(mmc_priv(mmc));
 382 @@ -155,6 +440,21 @@ static struct sdhci_ops sdhci_brcmstb_op
 383         .set_uhs_signaling = sdhci_set_uhs_signaling,
 384  };
 385
 386 +static struct sdhci_ops sdhci_brcmstb_ops_2712 = {
 387 +       .read_l = sdhci_brcmstb_32only_readl,
 388 +       .read_w = sdhci_brcmstb_32only_readw,
 389 +       .read_b = sdhci_brcmstb_32only_readb,
 390 +       .write_l = sdhci_brcmstb_32only_writel,
 391 +       .write_w = sdhci_brcmstb_32only_writew,
 392 +       .write_b = sdhci_brcmstb_32only_writeb,
 393 +       .set_clock = sdhci_set_clock,
 394 +       .set_power = sdhci_brcmstb_set_power,
 395 +       .set_bus_width = sdhci_set_bus_width,
 396 +       .reset = sdhci_reset,
 397 +       .set_uhs_signaling = sdhci_set_uhs_signaling,
 398 +       .init_sd_express = bcm2712_init_sd_express,
 399 +};
 400 +
 401  static struct sdhci_ops sdhci_brcmstb_ops_7216 = {
 402         .set_clock = sdhci_brcmstb_set_clock,
 403         .set_bus_width = sdhci_set_bus_width,
 404 @@ -179,10 +479,16 @@ static const struct brcmstb_match_priv m
 405         .ops = &sdhci_brcmstb_ops_7216,
 406  };
 407
 408 +static const struct brcmstb_match_priv match_priv_2712 = {
 409 +       .cfginit = sdhci_brcmstb_cfginit_2712,
 410 +       .ops = &sdhci_brcmstb_ops_2712,
 411 +};
 412 +
 413  static const struct of_device_id sdhci_brcm_of_match[] = {
 414         { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
 415         { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
 416         { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
 417 +       { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 },
 418         {},
 419  };
 420
 421 @@ -256,6 +562,7 @@ static int sdhci_brcmstb_probe(struct pl
 422         u32 actual_clock_mhz;
 423         struct sdhci_host *host;
 424         struct resource *iomem;
 425 +       bool no_pinctrl = false;
 426         struct clk *clk;
 427         struct clk *base_clk = NULL;
 428         int res;
 429 @@ -290,6 +597,11 @@ static int sdhci_brcmstb_probe(struct pl
 430                 match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
 431         }
 432
 433 +       priv->sde_pcie = of_parse_phandle(pdev->dev.of_node,
 434 +                                         "sde-pcie", 0);
 435 +       if (priv->sde_pcie)
 436 +               priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_SD_EXPRESS;
 437 +
 438         /* Map in the non-standard CFG registers */
 439         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 440         priv->cfg_regs = devm_ioremap_resource(&pdev->dev, iomem);
 441 @@ -303,6 +615,43 @@ static int sdhci_brcmstb_probe(struct pl
 442         if (res)
 443                 goto err;
 444
 445 +       priv->sde_1v8 = devm_regulator_get_optional(&pdev->dev, "sde-1v8");
 446 +       if (IS_ERR(priv->sde_1v8))
 447 +               priv->flags &= ~BRCMSTB_PRIV_FLAGS_HAS_SD_EXPRESS;
 448 +
 449 +       iomem = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 450 +       if (iomem) {
 451 +               priv->sde_ioaddr = devm_ioremap_resource(&pdev->dev, iomem);
 452 +               if (IS_ERR(priv->sde_ioaddr))
 453 +                       priv->sde_ioaddr = NULL;
 454 +       }
 455 +
 456 +       iomem = platform_get_resource(pdev, IORESOURCE_MEM, 3);
 457 +       if (iomem) {
 458 +               priv->sde_ioaddr2 = devm_ioremap_resource(&pdev->dev, iomem);
 459 +               if (IS_ERR(priv->sde_ioaddr2))
 460 +                       priv->sde_ioaddr = NULL;
 461 +       }
 462 +
 463 +       priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 464 +       if (IS_ERR(priv->pinctrl)) {
 465 +                       no_pinctrl = true;
 466 +       }
 467 +       priv->pins_default = pinctrl_lookup_state(priv->pinctrl, "default");
 468 +       if (IS_ERR(priv->pins_default)) {
 469 +                       dev_dbg(&pdev->dev, "No pinctrl default state\n");
 470 +                       no_pinctrl = true;
 471 +       }
 472 +       priv->pins_sdex = pinctrl_lookup_state(priv->pinctrl, "sd-express");
 473 +       if (IS_ERR(priv->pins_sdex)) {
 474 +                       dev_dbg(&pdev->dev, "No pinctrl sd-express state\n");
 475 +                       no_pinctrl = true;
 476 +       }
 477 +       if (no_pinctrl || !priv->sde_ioaddr || !priv->sde_ioaddr2) {
 478 +               priv->pinctrl = NULL;
 479 +               priv->flags &= ~BRCMSTB_PRIV_FLAGS_HAS_SD_EXPRESS;
 480 +       }
 481 +
 482         /*
 483          * Automatic clock gating does not work for SD cards that may
 484          * voltage switch so only enable it for non-removable devices.
 485 @@ -319,6 +668,13 @@ static int sdhci_brcmstb_probe(struct pl
 486             (host->mmc->caps2 & MMC_CAP2_HS400_ES))
 487                 host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es;
 488
 489 +       if (host->ops->init_sd_express &&
 490 +           (priv->flags & BRCMSTB_PRIV_FLAGS_HAS_SD_EXPRESS))
 491 +               host->mmc->caps2 |= MMC_CAP2_SD_EXP;
 492 +
 493 +       if(match_priv->cfginit)
 494 +               match_priv->cfginit(host);
 495 +
 496         /*
 497          * Supply the existing CAPS, but clear the UHS modes. This
 498          * will allow these modes to be specified by device tree