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bcm27xx: update 6.1 patches to latest version
[openwrt/staging/dangole.git] / target / linux / bcm27xx / patches-6.1 / 950-0857-pinctrl-bcm2712-pinctrl-pinconf-driver.patch
1 From af7e60a33f0b5ce84bffb69ba084ba1edd180195 Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.com>
3 Date: Wed, 9 Jun 2021 15:48:28 +0100
4 Subject: [PATCH] pinctrl: bcm2712 pinctrl/pinconf driver
5
6 pinctrl: bcm2712: Reject invalid pulls
7
8 Reject attempts to set pulls on aon-sgpios, and fix pull shift
9 values.
10
11 pinctrl: bcm2712: Add 7712 support, fix 2712 count
12
13 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
14
15 pinctrl-bcm2712: add EMMC pins so pulls can be set
16
17 These pins have pad controls but not mux controls. They look enough like
18 GPIOs to squeeze in at the end of the list though.
19
20 pinctrl: bcm2712: correct BCM2712C0 AON_GPIO pad pull control offset
21
22 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
23
24 pinctrl: bcm2712: on C0 the regular GPIO pad control register moves too
25
26 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
27
28 pinctrl: bcm2712: Implement (partially) pinconf_get
29
30 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
31
32 pinctrl: bcm2712: Convert to generic pinconf
33
34 Remove the legacy brcm,* pin configuration support and replace it with
35 a proper generic pinconf interface, using named functions instead of
36 alt function numbers. This is nicer for users, less error-prone, and
37 immune to some of the C0->D0 changes.
38
39 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
40
41 pinctrl: bcm2712: Remove vestigial pull parameter
42
43 Now the legacy brcm, pinconf parameters are no longer supported, this
44 custom pin config parameter is not needed.
45
46 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
47
48 pinctrl: bcm2712: Guard against bad func numbers
49
50 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
51
52 pinctrl: bcm2712: A better attempt at D0 support
53
54 The BCM2712D0 sparse pinctrl maps play havoc with the old GPIO_REGS
55 macro, so make the bit positions explicit. And delete the unwanted
56 GPIO and pinmux declarations on D0.
57
58 Note that a Pi 5 with D0 requires a separate DTS file with "bcm2712d0"
59 compatible strings.
60
61 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
62
63 pinctrl: bcm2712: Delete base register constants
64
65 BCM2712D0 deletes many GPIOs and their associated mux and pad bits,
66 so much so that the offsets to the start of the pad control registers
67 changes. Remove the constant offsets from the *GPIO_REGS macros,
68 compensating by adjusting the per-GPIO values.
69
70 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
71 ---
72 drivers/pinctrl/bcm/Kconfig | 9 +
73 drivers/pinctrl/bcm/Makefile | 1 +
74 drivers/pinctrl/bcm/pinctrl-bcm2712.c | 1216 +++++++++++++++++++++++++
75 3 files changed, 1226 insertions(+)
76 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm2712.c
77
78 --- a/drivers/pinctrl/bcm/Kconfig
79 +++ b/drivers/pinctrl/bcm/Kconfig
80 @@ -3,6 +3,15 @@
81 # Broadcom pinctrl drivers
82 #
83
84 +config PINCTRL_BCM2712
85 + bool "Broadcom BCM2712 PINCONF driver"
86 + depends on OF && (ARCH_BCM2835 || ARCH_BRCMSTB || COMPILE_TEST)
87 + select PINMUX
88 + select PINCONF
89 + select GENERIC_PINCONF
90 + help
91 + Say Y here to enable the Broadcom BCM2835 GPIO driver.
92 +
93 config PINCTRL_BCM281XX
94 bool "Broadcom BCM281xx pinctrl driver"
95 depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST)
96 --- a/drivers/pinctrl/bcm/Makefile
97 +++ b/drivers/pinctrl/bcm/Makefile
98 @@ -1,6 +1,7 @@
99 # SPDX-License-Identifier: GPL-2.0
100 # Broadcom pinctrl support
101
102 +obj-$(CONFIG_PINCTRL_BCM2712) += pinctrl-bcm2712.o
103 obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
104 obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
105 obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o
106 --- /dev/null
107 +++ b/drivers/pinctrl/bcm/pinctrl-bcm2712.c
108 @@ -0,0 +1,1216 @@
109 +// SPDX-License-Identifier: GPL-2.0+
110 +/*
111 + * Driver for Broadcom BCM2712 GPIO units (pinctrl only)
112 + *
113 + * Copyright (C) 2021-3 Raspberry Pi Ltd.
114 + * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
115 + *
116 + * Based heavily on the BCM2835 GPIO & pinctrl driver, which was inspired by:
117 + * pinctrl-nomadik.c, please see original file for copyright information
118 + * pinctrl-tegra.c, please see original file for copyright information
119 + */
120 +
121 +#include <linux/bitmap.h>
122 +#include <linux/bug.h>
123 +#include <linux/delay.h>
124 +#include <linux/device.h>
125 +#include <linux/err.h>
126 +#include <linux/io.h>
127 +#include <linux/init.h>
128 +#include <linux/interrupt.h>
129 +#include <linux/of_address.h>
130 +#include <linux/of.h>
131 +#include <linux/pinctrl/consumer.h>
132 +#include <linux/pinctrl/machine.h>
133 +#include <linux/pinctrl/pinconf.h>
134 +#include <linux/pinctrl/pinctrl.h>
135 +#include <linux/pinctrl/pinmux.h>
136 +#include <linux/pinctrl/pinconf-generic.h>
137 +#include <linux/platform_device.h>
138 +#include <linux/seq_file.h>
139 +#include <linux/slab.h>
140 +#include <linux/spinlock.h>
141 +#include <linux/types.h>
142 +
143 +#define MODULE_NAME "pinctrl-bcm2712"
144 +
145 +/* Register offsets */
146 +
147 +#define BCM2712_PULL_NONE 0
148 +#define BCM2712_PULL_DOWN 1
149 +#define BCM2712_PULL_UP 2
150 +#define BCM2712_PULL_MASK 0x3
151 +
152 +#define BCM2712_FSEL_COUNT 9
153 +#define BCM2712_FSEL_MASK 0xf
154 +
155 +#define FUNC(f) \
156 + [func_##f] = #f
157 +#define PIN(i, f1, f2, f3, f4, f5, f6, f7, f8) \
158 + [i] = { \
159 + .funcs = { \
160 + func_##f1, \
161 + func_##f2, \
162 + func_##f3, \
163 + func_##f4, \
164 + func_##f5, \
165 + func_##f6, \
166 + func_##f7, \
167 + func_##f8, \
168 + }, \
169 + }
170 +
171 +#define REG_BIT_INVALID 0xffff
172 +
173 +#define BIT_TO_REG(b) (((b) >> 5) << 2)
174 +#define BIT_TO_SHIFT(b) ((b) & 0x1f)
175 +
176 +#define GPIO_REGS(n, mr, mb, pr, pb) \
177 + [n] = { ((mr)*4)*8 + (mb)*4, ((pr)*4)*8 + (pb)*2 }
178 +
179 +#define EMMC_REGS(n, r, b) \
180 + [n] = { 0, ((r)*4)*8 + (b)*2 }
181 +
182 +#define AGPIO_REGS(n, mr, mb, pr, pb) \
183 + [n] = { ((mr)*4)*8 + (mb)*4, ((pr)*4)*8 + (pb)*2 }
184 +
185 +#define SGPIO_REGS(n, mr, mb) \
186 + [n+32] = { ((mr)*4)*8 + (mb)*4, REG_BIT_INVALID }
187 +
188 +#define GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
189 +#define AGPIO_PIN(a) PINCTRL_PIN(a, "aon_gpio" #a)
190 +#define SGPIO_PIN(a) PINCTRL_PIN(a+32, "aon_sgpio" #a)
191 +
192 +struct pin_regs {
193 + u16 mux_bit;
194 + u16 pad_bit;
195 +};
196 +
197 +struct bcm2712_pinctrl {
198 + struct device *dev;
199 + void __iomem *base;
200 + struct pinctrl_dev *pctl_dev;
201 + struct pinctrl_desc pctl_desc;
202 + const struct pin_regs *pin_regs;
203 + const struct bcm2712_pin_funcs *pin_funcs;
204 + const char *const *gpio_groups;
205 + struct pinctrl_gpio_range gpio_range;
206 + spinlock_t lock;
207 +};
208 +
209 +struct bcm_plat_data {
210 + const struct pinctrl_desc *pctl_desc;
211 + const struct pinctrl_gpio_range *gpio_range;
212 + const struct pin_regs *pin_regs;
213 + const struct bcm2712_pin_funcs *pin_funcs;
214 +};
215 +
216 +struct bcm2712_pin_funcs {
217 + u8 funcs[BCM2712_FSEL_COUNT - 1];
218 +};
219 +
220 +enum bcm2712_funcs {
221 + func_gpio,
222 + func_alt1,
223 + func_alt2,
224 + func_alt3,
225 + func_alt4,
226 + func_alt5,
227 + func_alt6,
228 + func_alt7,
229 + func_alt8,
230 + func_aon_cpu_standbyb,
231 + func_aon_fp_4sec_resetb,
232 + func_aon_gpclk,
233 + func_aon_pwm,
234 + func_arm_jtag,
235 + func_aud_fs_clk0,
236 + func_avs_pmu_bsc,
237 + func_bsc_m0,
238 + func_bsc_m1,
239 + func_bsc_m2,
240 + func_bsc_m3,
241 + func_clk_observe,
242 + func_ctl_hdmi_5v,
243 + func_enet0,
244 + func_enet0_mii,
245 + func_enet0_rgmii,
246 + func_ext_sc_clk,
247 + func_fl0,
248 + func_fl1,
249 + func_gpclk0,
250 + func_gpclk1,
251 + func_gpclk2,
252 + func_hdmi_tx0_auto_i2c,
253 + func_hdmi_tx0_bsc,
254 + func_hdmi_tx1_auto_i2c,
255 + func_hdmi_tx1_bsc,
256 + func_i2s_in,
257 + func_i2s_out,
258 + func_ir_in,
259 + func_mtsif,
260 + func_mtsif_alt,
261 + func_mtsif_alt1,
262 + func_pdm,
263 + func_pkt,
264 + func_pm_led_out,
265 + func_sc0,
266 + func_sd0,
267 + func_sd2,
268 + func_sd_card_a,
269 + func_sd_card_b,
270 + func_sd_card_c,
271 + func_sd_card_d,
272 + func_sd_card_e,
273 + func_sd_card_f,
274 + func_sd_card_g,
275 + func_spdif_out,
276 + func_spi_m,
277 + func_spi_s,
278 + func_sr_edm_sense,
279 + func_te0,
280 + func_te1,
281 + func_tsio,
282 + func_uart0,
283 + func_uart1,
284 + func_uart2,
285 + func_usb_pwr,
286 + func_usb_vbus,
287 + func_uui,
288 + func_vc_i2c0,
289 + func_vc_i2c3,
290 + func_vc_i2c4,
291 + func_vc_i2c5,
292 + func_vc_i2csl,
293 + func_vc_pcm,
294 + func_vc_pwm0,
295 + func_vc_pwm1,
296 + func_vc_spi0,
297 + func_vc_spi3,
298 + func_vc_spi4,
299 + func_vc_spi5,
300 + func_vc_uart0,
301 + func_vc_uart2,
302 + func_vc_uart3,
303 + func_vc_uart4,
304 + func__,
305 + func_count = func__
306 +};
307 +
308 +static const struct pin_regs bcm2712_c0_gpio_pin_regs[] = {
309 + GPIO_REGS(0, 0, 0, 7, 7),
310 + GPIO_REGS(1, 0, 1, 7, 8),
311 + GPIO_REGS(2, 0, 2, 7, 9),
312 + GPIO_REGS(3, 0, 3, 7, 10),
313 + GPIO_REGS(4, 0, 4, 7, 11),
314 + GPIO_REGS(5, 0, 5, 7, 12),
315 + GPIO_REGS(6, 0, 6, 7, 13),
316 + GPIO_REGS(7, 0, 7, 7, 14),
317 + GPIO_REGS(8, 1, 0, 8, 0),
318 + GPIO_REGS(9, 1, 1, 8, 1),
319 + GPIO_REGS(10, 1, 2, 8, 2),
320 + GPIO_REGS(11, 1, 3, 8, 3),
321 + GPIO_REGS(12, 1, 4, 8, 4),
322 + GPIO_REGS(13, 1, 5, 8, 5),
323 + GPIO_REGS(14, 1, 6, 8, 6),
324 + GPIO_REGS(15, 1, 7, 8, 7),
325 + GPIO_REGS(16, 2, 0, 8, 8),
326 + GPIO_REGS(17, 2, 1, 8, 9),
327 + GPIO_REGS(18, 2, 2, 8, 10),
328 + GPIO_REGS(19, 2, 3, 8, 11),
329 + GPIO_REGS(20, 2, 4, 8, 12),
330 + GPIO_REGS(21, 2, 5, 8, 13),
331 + GPIO_REGS(22, 2, 6, 8, 14),
332 + GPIO_REGS(23, 2, 7, 9, 0),
333 + GPIO_REGS(24, 3, 0, 9, 1),
334 + GPIO_REGS(25, 3, 1, 9, 2),
335 + GPIO_REGS(26, 3, 2, 9, 3),
336 + GPIO_REGS(27, 3, 3, 9, 4),
337 + GPIO_REGS(28, 3, 4, 9, 5),
338 + GPIO_REGS(29, 3, 5, 9, 6),
339 + GPIO_REGS(30, 3, 6, 9, 7),
340 + GPIO_REGS(31, 3, 7, 9, 8),
341 + GPIO_REGS(32, 4, 0, 9, 9),
342 + GPIO_REGS(33, 4, 1, 9, 10),
343 + GPIO_REGS(34, 4, 2, 9, 11),
344 + GPIO_REGS(35, 4, 3, 9, 12),
345 + GPIO_REGS(36, 4, 4, 9, 13),
346 + GPIO_REGS(37, 4, 5, 9, 14),
347 + GPIO_REGS(38, 4, 6, 10, 0),
348 + GPIO_REGS(39, 4, 7, 10, 1),
349 + GPIO_REGS(40, 5, 0, 10, 2),
350 + GPIO_REGS(41, 5, 1, 10, 3),
351 + GPIO_REGS(42, 5, 2, 10, 4),
352 + GPIO_REGS(43, 5, 3, 10, 5),
353 + GPIO_REGS(44, 5, 4, 10, 6),
354 + GPIO_REGS(45, 5, 5, 10, 7),
355 + GPIO_REGS(46, 5, 6, 10, 8),
356 + GPIO_REGS(47, 5, 7, 10, 9),
357 + GPIO_REGS(48, 6, 0, 10, 10),
358 + GPIO_REGS(49, 6, 1, 10, 11),
359 + GPIO_REGS(50, 6, 2, 10, 12),
360 + GPIO_REGS(51, 6, 3, 10, 13),
361 + GPIO_REGS(52, 6, 4, 10, 14),
362 + GPIO_REGS(53, 6, 5, 11, 0),
363 + EMMC_REGS(54, 11, 1), /* EMMC_CMD */
364 + EMMC_REGS(55, 11, 2), /* EMMC_DS */
365 + EMMC_REGS(56, 11, 3), /* EMMC_CLK */
366 + EMMC_REGS(57, 11, 4), /* EMMC_DAT0 */
367 + EMMC_REGS(58, 11, 5), /* EMMC_DAT1 */
368 + EMMC_REGS(59, 11, 6), /* EMMC_DAT2 */
369 + EMMC_REGS(60, 11, 7), /* EMMC_DAT3 */
370 + EMMC_REGS(61, 11, 8), /* EMMC_DAT4 */
371 + EMMC_REGS(62, 11, 9), /* EMMC_DAT5 */
372 + EMMC_REGS(63, 11, 10), /* EMMC_DAT6 */
373 + EMMC_REGS(64, 11, 11), /* EMMC_DAT7 */
374 +};
375 +
376 +static struct pin_regs bcm2712_c0_aon_gpio_pin_regs[] = {
377 + AGPIO_REGS(0, 3, 0, 6, 10),
378 + AGPIO_REGS(1, 3, 1, 6, 11),
379 + AGPIO_REGS(2, 3, 2, 6, 12),
380 + AGPIO_REGS(3, 3, 3, 6, 13),
381 + AGPIO_REGS(4, 3, 4, 6, 14),
382 + AGPIO_REGS(5, 3, 5, 7, 0),
383 + AGPIO_REGS(6, 3, 6, 7, 1),
384 + AGPIO_REGS(7, 3, 7, 7, 2),
385 + AGPIO_REGS(8, 4, 0, 7, 3),
386 + AGPIO_REGS(9, 4, 1, 7, 4),
387 + AGPIO_REGS(10, 4, 2, 7, 5),
388 + AGPIO_REGS(11, 4, 3, 7, 6),
389 + AGPIO_REGS(12, 4, 4, 7, 7),
390 + AGPIO_REGS(13, 4, 5, 7, 8),
391 + AGPIO_REGS(14, 4, 6, 7, 9),
392 + AGPIO_REGS(15, 4, 7, 7, 10),
393 + AGPIO_REGS(16, 5, 0, 7, 11),
394 + SGPIO_REGS(0, 0, 0),
395 + SGPIO_REGS(1, 0, 1),
396 + SGPIO_REGS(2, 0, 2),
397 + SGPIO_REGS(3, 0, 3),
398 + SGPIO_REGS(4, 1, 0),
399 + SGPIO_REGS(5, 2, 0),
400 +};
401 +
402 +static const struct pinctrl_pin_desc bcm2712_c0_gpio_pins[] = {
403 + GPIO_PIN(0),
404 + GPIO_PIN(1),
405 + GPIO_PIN(2),
406 + GPIO_PIN(3),
407 + GPIO_PIN(4),
408 + GPIO_PIN(5),
409 + GPIO_PIN(6),
410 + GPIO_PIN(7),
411 + GPIO_PIN(8),
412 + GPIO_PIN(9),
413 + GPIO_PIN(10),
414 + GPIO_PIN(11),
415 + GPIO_PIN(12),
416 + GPIO_PIN(13),
417 + GPIO_PIN(14),
418 + GPIO_PIN(15),
419 + GPIO_PIN(16),
420 + GPIO_PIN(17),
421 + GPIO_PIN(18),
422 + GPIO_PIN(19),
423 + GPIO_PIN(20),
424 + GPIO_PIN(21),
425 + GPIO_PIN(22),
426 + GPIO_PIN(23),
427 + GPIO_PIN(24),
428 + GPIO_PIN(25),
429 + GPIO_PIN(26),
430 + GPIO_PIN(27),
431 + GPIO_PIN(28),
432 + GPIO_PIN(29),
433 + GPIO_PIN(30),
434 + GPIO_PIN(31),
435 + GPIO_PIN(32),
436 + GPIO_PIN(33),
437 + GPIO_PIN(34),
438 + GPIO_PIN(35),
439 + GPIO_PIN(36),
440 + GPIO_PIN(37),
441 + GPIO_PIN(38),
442 + GPIO_PIN(39),
443 + GPIO_PIN(40),
444 + GPIO_PIN(41),
445 + GPIO_PIN(42),
446 + GPIO_PIN(43),
447 + GPIO_PIN(44),
448 + GPIO_PIN(45),
449 + GPIO_PIN(46),
450 + GPIO_PIN(47),
451 + GPIO_PIN(48),
452 + GPIO_PIN(49),
453 + GPIO_PIN(50),
454 + GPIO_PIN(51),
455 + GPIO_PIN(52),
456 + GPIO_PIN(53),
457 + PINCTRL_PIN(54, "emmc_cmd"),
458 + PINCTRL_PIN(55, "emmc_ds"),
459 + PINCTRL_PIN(56, "emmc_clk"),
460 + PINCTRL_PIN(57, "emmc_dat0"),
461 + PINCTRL_PIN(58, "emmc_dat1"),
462 + PINCTRL_PIN(59, "emmc_dat2"),
463 + PINCTRL_PIN(60, "emmc_dat3"),
464 + PINCTRL_PIN(61, "emmc_dat4"),
465 + PINCTRL_PIN(62, "emmc_dat5"),
466 + PINCTRL_PIN(63, "emmc_dat6"),
467 + PINCTRL_PIN(64, "emmc_dat7"),
468 +};
469 +
470 +static struct pinctrl_pin_desc bcm2712_c0_aon_gpio_pins[] = {
471 + AGPIO_PIN(0),
472 + AGPIO_PIN(1),
473 + AGPIO_PIN(2),
474 + AGPIO_PIN(3),
475 + AGPIO_PIN(4),
476 + AGPIO_PIN(5),
477 + AGPIO_PIN(6),
478 + AGPIO_PIN(7),
479 + AGPIO_PIN(8),
480 + AGPIO_PIN(9),
481 + AGPIO_PIN(10),
482 + AGPIO_PIN(11),
483 + AGPIO_PIN(12),
484 + AGPIO_PIN(13),
485 + AGPIO_PIN(14),
486 + AGPIO_PIN(15),
487 + AGPIO_PIN(16),
488 + SGPIO_PIN(0),
489 + SGPIO_PIN(1),
490 + SGPIO_PIN(2),
491 + SGPIO_PIN(3),
492 + SGPIO_PIN(4),
493 + SGPIO_PIN(5),
494 +};
495 +
496 +static const struct pin_regs bcm2712_d0_gpio_pin_regs[] = {
497 + GPIO_REGS(1, 0, 0, 4, 5),
498 + GPIO_REGS(2, 0, 1, 4, 6),
499 + GPIO_REGS(3, 0, 2, 4, 7),
500 + GPIO_REGS(4, 0, 3, 4, 8),
501 + GPIO_REGS(10, 0, 4, 4, 9),
502 + GPIO_REGS(11, 0, 5, 4, 10),
503 + GPIO_REGS(12, 0, 6, 4, 11),
504 + GPIO_REGS(13, 0, 7, 4, 12),
505 + GPIO_REGS(14, 1, 0, 4, 13),
506 + GPIO_REGS(15, 1, 1, 4, 14),
507 + GPIO_REGS(18, 1, 2, 5, 0),
508 + GPIO_REGS(19, 1, 3, 5, 1),
509 + GPIO_REGS(20, 1, 4, 5, 2),
510 + GPIO_REGS(21, 1, 5, 5, 3),
511 + GPIO_REGS(22, 1, 6, 5, 4),
512 + GPIO_REGS(23, 1, 7, 5, 5),
513 + GPIO_REGS(24, 2, 0, 5, 6),
514 + GPIO_REGS(25, 2, 1, 5, 7),
515 + GPIO_REGS(26, 2, 2, 5, 8),
516 + GPIO_REGS(27, 2, 3, 5, 9),
517 + GPIO_REGS(28, 2, 4, 5, 10),
518 + GPIO_REGS(29, 2, 5, 5, 11),
519 + GPIO_REGS(30, 2, 6, 5, 12),
520 + GPIO_REGS(31, 2, 7, 5, 13),
521 + GPIO_REGS(32, 3, 0, 5, 14),
522 + GPIO_REGS(33, 3, 1, 6, 0),
523 + GPIO_REGS(34, 3, 2, 6, 1),
524 + GPIO_REGS(35, 3, 3, 6, 2),
525 +};
526 +
527 +static struct pin_regs bcm2712_d0_aon_gpio_pin_regs[] = {
528 + AGPIO_REGS(0, 3, 0, 5, 9),
529 + AGPIO_REGS(1, 3, 1, 5, 10),
530 + AGPIO_REGS(2, 3, 2, 5, 11),
531 + AGPIO_REGS(3, 3, 3, 5, 12),
532 + AGPIO_REGS(4, 3, 4, 5, 13),
533 + AGPIO_REGS(5, 3, 5, 5, 14),
534 + AGPIO_REGS(6, 3, 6, 6, 0),
535 + AGPIO_REGS(8, 3, 7, 6, 1),
536 + AGPIO_REGS(9, 4, 0, 6, 2),
537 + AGPIO_REGS(12, 4, 1, 6, 3),
538 + AGPIO_REGS(13, 4, 2, 6, 4),
539 + AGPIO_REGS(14, 4, 3, 6, 5),
540 + SGPIO_REGS(0, 0, 0),
541 + SGPIO_REGS(1, 0, 1),
542 + SGPIO_REGS(2, 0, 2),
543 + SGPIO_REGS(3, 0, 3),
544 + SGPIO_REGS(4, 1, 0),
545 + SGPIO_REGS(5, 2, 0),
546 +};
547 +
548 +static const struct pinctrl_pin_desc bcm2712_d0_gpio_pins[] = {
549 + GPIO_PIN(1),
550 + GPIO_PIN(2),
551 + GPIO_PIN(3),
552 + GPIO_PIN(4),
553 + GPIO_PIN(10),
554 + GPIO_PIN(11),
555 + GPIO_PIN(12),
556 + GPIO_PIN(13),
557 + GPIO_PIN(14),
558 + GPIO_PIN(15),
559 + GPIO_PIN(18),
560 + GPIO_PIN(19),
561 + GPIO_PIN(20),
562 + GPIO_PIN(21),
563 + GPIO_PIN(22),
564 + GPIO_PIN(23),
565 + GPIO_PIN(24),
566 + GPIO_PIN(25),
567 + GPIO_PIN(26),
568 + GPIO_PIN(27),
569 + GPIO_PIN(28),
570 + GPIO_PIN(29),
571 + GPIO_PIN(30),
572 + GPIO_PIN(31),
573 + GPIO_PIN(32),
574 + GPIO_PIN(33),
575 + GPIO_PIN(34),
576 + GPIO_PIN(35),
577 +};
578 +
579 +static struct pinctrl_pin_desc bcm2712_d0_aon_gpio_pins[] = {
580 + AGPIO_PIN(0),
581 + AGPIO_PIN(1),
582 + AGPIO_PIN(2),
583 + AGPIO_PIN(3),
584 + AGPIO_PIN(4),
585 + AGPIO_PIN(5),
586 + AGPIO_PIN(6),
587 + AGPIO_PIN(8),
588 + AGPIO_PIN(9),
589 + AGPIO_PIN(12),
590 + AGPIO_PIN(13),
591 + AGPIO_PIN(14),
592 + SGPIO_PIN(0),
593 + SGPIO_PIN(1),
594 + SGPIO_PIN(2),
595 + SGPIO_PIN(3),
596 + SGPIO_PIN(4),
597 + SGPIO_PIN(5),
598 +};
599 +
600 +static const char * const bcm2712_func_names[] = {
601 + FUNC(gpio),
602 + FUNC(alt1),
603 + FUNC(alt2),
604 + FUNC(alt3),
605 + FUNC(alt4),
606 + FUNC(alt5),
607 + FUNC(alt6),
608 + FUNC(alt7),
609 + FUNC(alt8),
610 + FUNC(aon_cpu_standbyb),
611 + FUNC(aon_fp_4sec_resetb),
612 + FUNC(aon_gpclk),
613 + FUNC(aon_pwm),
614 + FUNC(arm_jtag),
615 + FUNC(aud_fs_clk0),
616 + FUNC(avs_pmu_bsc),
617 + FUNC(bsc_m0),
618 + FUNC(bsc_m1),
619 + FUNC(bsc_m2),
620 + FUNC(bsc_m3),
621 + FUNC(clk_observe),
622 + FUNC(ctl_hdmi_5v),
623 + FUNC(enet0),
624 + FUNC(enet0_mii),
625 + FUNC(enet0_rgmii),
626 + FUNC(ext_sc_clk),
627 + FUNC(fl0),
628 + FUNC(fl1),
629 + FUNC(gpclk0),
630 + FUNC(gpclk1),
631 + FUNC(gpclk2),
632 + FUNC(hdmi_tx0_auto_i2c),
633 + FUNC(hdmi_tx0_bsc),
634 + FUNC(hdmi_tx1_auto_i2c),
635 + FUNC(hdmi_tx1_bsc),
636 + FUNC(i2s_in),
637 + FUNC(i2s_out),
638 + FUNC(ir_in),
639 + FUNC(mtsif),
640 + FUNC(mtsif_alt),
641 + FUNC(mtsif_alt1),
642 + FUNC(pdm),
643 + FUNC(pkt),
644 + FUNC(pm_led_out),
645 + FUNC(sc0),
646 + FUNC(sd0),
647 + FUNC(sd2),
648 + FUNC(sd_card_a),
649 + FUNC(sd_card_b),
650 + FUNC(sd_card_c),
651 + FUNC(sd_card_d),
652 + FUNC(sd_card_e),
653 + FUNC(sd_card_f),
654 + FUNC(sd_card_g),
655 + FUNC(spdif_out),
656 + FUNC(spi_m),
657 + FUNC(spi_s),
658 + FUNC(sr_edm_sense),
659 + FUNC(te0),
660 + FUNC(te1),
661 + FUNC(tsio),
662 + FUNC(uart0),
663 + FUNC(uart1),
664 + FUNC(uart2),
665 + FUNC(usb_pwr),
666 + FUNC(usb_vbus),
667 + FUNC(uui),
668 + FUNC(vc_i2c0),
669 + FUNC(vc_i2c3),
670 + FUNC(vc_i2c4),
671 + FUNC(vc_i2c5),
672 + FUNC(vc_i2csl),
673 + FUNC(vc_pcm),
674 + FUNC(vc_pwm0),
675 + FUNC(vc_pwm1),
676 + FUNC(vc_spi0),
677 + FUNC(vc_spi3),
678 + FUNC(vc_spi4),
679 + FUNC(vc_spi5),
680 + FUNC(vc_uart0),
681 + FUNC(vc_uart2),
682 + FUNC(vc_uart3),
683 + FUNC(vc_uart4),
684 +};
685 +
686 +static const struct bcm2712_pin_funcs bcm2712_c0_aon_gpio_pin_funcs[] = {
687 + PIN(0, ir_in, vc_spi0, vc_uart3, vc_i2c3, te0, vc_i2c0, _, _),
688 + PIN(1, vc_pwm0, vc_spi0, vc_uart3, vc_i2c3, te1, aon_pwm, vc_i2c0, vc_pwm1),
689 + PIN(2, vc_pwm0, vc_spi0, vc_uart3, ctl_hdmi_5v, fl0, aon_pwm, ir_in, vc_pwm1),
690 + PIN(3, ir_in, vc_spi0, vc_uart3, aon_fp_4sec_resetb, fl1, sd_card_g, aon_gpclk, _),
691 + PIN(4, gpclk0, vc_spi0, vc_i2csl, aon_gpclk, pm_led_out, aon_pwm, sd_card_g, vc_pwm0),
692 + PIN(5, gpclk1, ir_in, vc_i2csl, clk_observe, aon_pwm, sd_card_g, vc_pwm0, _),
693 + PIN(6, uart1, vc_uart4, gpclk2, ctl_hdmi_5v, vc_uart0, vc_spi3, _, _),
694 + PIN(7, uart1, vc_uart4, gpclk0, aon_pwm, vc_uart0, vc_spi3, _, _),
695 + PIN(8, uart1, vc_uart4, vc_i2csl, ctl_hdmi_5v, vc_uart0, vc_spi3, _, _),
696 + PIN(9, uart1, vc_uart4, vc_i2csl, aon_pwm, vc_uart0, vc_spi3, _, _),
697 + PIN(10, tsio, ctl_hdmi_5v, sc0, spdif_out, vc_spi5, usb_pwr, aon_gpclk, sd_card_f),
698 + PIN(11, tsio, uart0, sc0, aud_fs_clk0, vc_spi5, usb_vbus, vc_uart2, sd_card_f),
699 + PIN(12, tsio, uart0, vc_uart0, tsio, vc_spi5, usb_pwr, vc_uart2, sd_card_f),
700 + PIN(13, bsc_m1, uart0, vc_uart0, uui, vc_spi5, arm_jtag, vc_uart2, vc_i2c3),
701 + PIN(14, bsc_m1, uart0, vc_uart0, uui, vc_spi5, arm_jtag, vc_uart2, vc_i2c3),
702 + PIN(15, ir_in, aon_fp_4sec_resetb, vc_uart0, pm_led_out, ctl_hdmi_5v, aon_pwm, aon_gpclk, _),
703 + PIN(16, aon_cpu_standbyb, gpclk0, pm_led_out, ctl_hdmi_5v, vc_pwm0, usb_pwr, aud_fs_clk0, _),
704 +};
705 +
706 +static const struct bcm2712_pin_funcs bcm2712_c0_aon_sgpio_pin_funcs[] = {
707 + PIN(0, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
708 + PIN(1, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
709 + PIN(2, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c4, ctl_hdmi_5v, _, _, _),
710 + PIN(3, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c4, _, _, _, _),
711 + PIN(4, avs_pmu_bsc, bsc_m2, vc_i2c5, ctl_hdmi_5v, _, _, _, _),
712 + PIN(5, avs_pmu_bsc, bsc_m2, vc_i2c5, _, _, _, _, _),
713 +};
714 +
715 +static const struct bcm2712_pin_funcs bcm2712_c0_gpio_pin_funcs[] = {
716 + PIN(0, bsc_m3, vc_i2c0, gpclk0, enet0, vc_pwm1, vc_spi0, ir_in, _),
717 + PIN(1, bsc_m3, vc_i2c0, gpclk1, enet0, vc_pwm1, sr_edm_sense, vc_spi0, vc_uart3),
718 + PIN(2, pdm, i2s_in, gpclk2, vc_spi4, pkt, vc_spi0, vc_uart3, _),
719 + PIN(3, pdm, i2s_in, vc_spi4, pkt, vc_spi0, vc_uart3, _, _),
720 + PIN(4, pdm, i2s_in, arm_jtag, vc_spi4, pkt, vc_spi0, vc_uart3, _),
721 + PIN(5, pdm, vc_i2c3, arm_jtag, sd_card_e, vc_spi4, pkt, vc_pcm, vc_i2c5),
722 + PIN(6, pdm, vc_i2c3, arm_jtag, sd_card_e, vc_spi4, pkt, vc_pcm, vc_i2c5),
723 + PIN(7, i2s_out, spdif_out, arm_jtag, sd_card_e, vc_i2c3, enet0_rgmii, vc_pcm, vc_spi4),
724 + PIN(8, i2s_out, aud_fs_clk0, arm_jtag, sd_card_e, vc_i2c3, enet0_mii, vc_pcm, vc_spi4),
725 + PIN(9, i2s_out, aud_fs_clk0, arm_jtag, sd_card_e, enet0_mii, sd_card_c, vc_spi4, _),
726 + PIN(10, bsc_m3, mtsif_alt1, i2s_in, i2s_out, vc_spi5, enet0_mii, sd_card_c, vc_spi4),
727 + PIN(11, bsc_m3, mtsif_alt1, i2s_in, i2s_out, vc_spi5, enet0_mii, sd_card_c, vc_spi4),
728 + PIN(12, spi_s, mtsif_alt1, i2s_in, i2s_out, vc_spi5, vc_i2csl, sd0, sd_card_d),
729 + PIN(13, spi_s, mtsif_alt1, i2s_out, usb_vbus, vc_spi5, vc_i2csl, sd0, sd_card_d),
730 + PIN(14, spi_s, vc_i2csl, enet0_rgmii, arm_jtag, vc_spi5, vc_pwm0, vc_i2c4, sd_card_d),
731 + PIN(15, spi_s, vc_i2csl, vc_spi3, arm_jtag, vc_pwm0, vc_i2c4, gpclk0, _),
732 + PIN(16, sd_card_b, i2s_out, vc_spi3, i2s_in, sd0, enet0_rgmii, gpclk1, _),
733 + PIN(17, sd_card_b, i2s_out, vc_spi3, i2s_in, ext_sc_clk, sd0, enet0_rgmii, gpclk2),
734 + PIN(18, sd_card_b, i2s_out, vc_spi3, i2s_in, sd0, enet0_rgmii, vc_pwm1, _),
735 + PIN(19, sd_card_b, usb_pwr, vc_spi3, pkt, spdif_out, sd0, ir_in, vc_pwm1),
736 + PIN(20, sd_card_b, uui, vc_uart0, arm_jtag, uart2, usb_pwr, vc_pcm, vc_uart4),
737 + PIN(21, usb_pwr, uui, vc_uart0, arm_jtag, uart2, sd_card_b, vc_pcm, vc_uart4),
738 + PIN(22, usb_pwr, enet0, vc_uart0, mtsif, uart2, usb_vbus, vc_pcm, vc_i2c5),
739 + PIN(23, usb_vbus, enet0, vc_uart0, mtsif, uart2, i2s_out, vc_pcm, vc_i2c5),
740 + PIN(24, mtsif, pkt, uart0, enet0_rgmii, enet0_rgmii, vc_i2c4, vc_uart3, _),
741 + PIN(25, mtsif, pkt, sc0, uart0, enet0_rgmii, enet0_rgmii, vc_i2c4, vc_uart3),
742 + PIN(26, mtsif, pkt, sc0, uart0, enet0_rgmii, vc_uart4, vc_spi5, _),
743 + PIN(27, mtsif, pkt, sc0, uart0, enet0_rgmii, vc_uart4, vc_spi5, _),
744 + PIN(28, mtsif, pkt, sc0, enet0_rgmii, vc_uart4, vc_spi5, _, _),
745 + PIN(29, mtsif, pkt, sc0, enet0_rgmii, vc_uart4, vc_spi5, _, _),
746 + PIN(30, mtsif, pkt, sc0, sd2, enet0_rgmii, gpclk0, vc_pwm0, _),
747 + PIN(31, mtsif, pkt, sc0, sd2, enet0_rgmii, vc_spi3, vc_pwm0, _),
748 + PIN(32, mtsif, pkt, sc0, sd2, enet0_rgmii, vc_spi3, vc_uart3, _),
749 + PIN(33, mtsif, pkt, sd2, enet0_rgmii, vc_spi3, vc_uart3, _, _),
750 + PIN(34, mtsif, pkt, ext_sc_clk, sd2, enet0_rgmii, vc_spi3, vc_i2c5, _),
751 + PIN(35, mtsif, pkt, sd2, enet0_rgmii, vc_spi3, vc_i2c5, _, _),
752 + PIN(36, sd0, mtsif, sc0, i2s_in, vc_uart3, vc_uart2, _, _),
753 + PIN(37, sd0, mtsif, sc0, vc_spi0, i2s_in, vc_uart3, vc_uart2, _),
754 + PIN(38, sd0, mtsif_alt, sc0, vc_spi0, i2s_in, vc_uart3, vc_uart2, _),
755 + PIN(39, sd0, mtsif_alt, sc0, vc_spi0, vc_uart3, vc_uart2, _, _),
756 + PIN(40, sd0, mtsif_alt, sc0, vc_spi0, bsc_m3, _, _, _),
757 + PIN(41, sd0, mtsif_alt, sc0, vc_spi0, bsc_m3, _, _, _),
758 + PIN(42, vc_spi0, mtsif_alt, vc_i2c0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
759 + PIN(43, vc_spi0, mtsif_alt, vc_i2c0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
760 + PIN(44, vc_spi0, mtsif_alt, enet0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
761 + PIN(45, vc_spi0, mtsif_alt, enet0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
762 + PIN(46, vc_spi0, mtsif_alt, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m, _),
763 + PIN(47, enet0, mtsif_alt, i2s_out, mtsif_alt1, arm_jtag, _, _, _),
764 + PIN(48, sc0, usb_pwr, spdif_out, mtsif, _, _, _, _),
765 + PIN(49, sc0, usb_pwr, aud_fs_clk0, mtsif, _, _, _, _),
766 + PIN(50, sc0, usb_vbus, sc0, _, _, _, _, _),
767 + PIN(51, sc0, enet0, sc0, sr_edm_sense, _, _, _, _),
768 + PIN(52, sc0, enet0, vc_pwm1, _, _, _, _, _),
769 + PIN(53, sc0, enet0_rgmii, ext_sc_clk, _, _, _, _, _),
770 +};
771 +
772 +static const struct bcm2712_pin_funcs bcm2712_d0_aon_gpio_pin_funcs[] = {
773 + PIN(0, ir_in, vc_spi0, vc_uart0, vc_i2c3, uart0, vc_i2c0, _, _),
774 + PIN(1, vc_pwm0, vc_spi0, vc_uart0, vc_i2c3, uart0, aon_pwm, vc_i2c0, vc_pwm1),
775 + PIN(2, vc_pwm0, vc_spi0, vc_uart0, ctl_hdmi_5v, uart0, aon_pwm, ir_in, vc_pwm1),
776 + PIN(3, ir_in, vc_spi0, vc_uart0, uart0, sd_card_g, aon_gpclk, _, _),
777 + PIN(4, gpclk0, vc_spi0, pm_led_out, aon_pwm, sd_card_g, vc_pwm0, _, _),
778 + PIN(5, gpclk1, ir_in, aon_pwm, sd_card_g, vc_pwm0, _, _, _),
779 + PIN(6, uart1, vc_uart2, ctl_hdmi_5v, gpclk2, vc_spi3, _, _, _),
780 + PIN(7, _, _, _, _, _, _, _, _),
781 + PIN(8, uart1, vc_uart2, ctl_hdmi_5v, vc_spi0, vc_spi3, _, _, _),
782 + PIN(9, uart1, vc_uart2, vc_uart0, aon_pwm, vc_spi0, vc_uart2, vc_spi3, _),
783 + PIN(10, _, _, _, _, _, _, _, _),
784 + PIN(11, _, _, _, _, _, _, _, _),
785 + PIN(12, uart1, vc_uart2, vc_uart0, vc_spi0, usb_pwr, vc_uart2, vc_spi3, _),
786 + PIN(13, bsc_m1, vc_uart0, uui, vc_spi0, arm_jtag, vc_uart2, vc_i2c3, _),
787 + PIN(14, bsc_m1, aon_gpclk, vc_uart0, uui, vc_spi0, arm_jtag, vc_uart2, vc_i2c3),
788 +};
789 +
790 +static const struct bcm2712_pin_funcs bcm2712_d0_aon_sgpio_pin_funcs[] = {
791 + PIN(0, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
792 + PIN(1, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
793 + PIN(2, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c0, ctl_hdmi_5v, _, _, _),
794 + PIN(3, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c0, _, _, _, _),
795 + PIN(4, avs_pmu_bsc, bsc_m2, vc_i2c3, ctl_hdmi_5v, _, _, _, _),
796 + PIN(5, avs_pmu_bsc, bsc_m2, vc_i2c3, _, _, _, _, _),
797 +};
798 +
799 +static const struct bcm2712_pin_funcs bcm2712_d0_gpio_pin_funcs[] = {
800 + PIN(1, vc_i2c0, usb_pwr, gpclk0, sd_card_e, vc_spi3, sr_edm_sense, vc_spi0, vc_uart0),
801 + PIN(2, vc_i2c0, usb_pwr, gpclk1, sd_card_e, vc_spi3, clk_observe, vc_spi0, vc_uart0),
802 + PIN(3, vc_i2c3, usb_vbus, gpclk2, sd_card_e, vc_spi3, vc_spi0, vc_uart0, _),
803 + PIN(4, vc_i2c3, vc_pwm1, vc_spi3, sd_card_e, vc_spi3, vc_spi0, vc_uart0, _),
804 + PIN(10, bsc_m3, vc_pwm1, vc_spi3, sd_card_e, vc_spi3, gpclk0, _, _),
805 + PIN(11, bsc_m3, vc_spi3, clk_observe, sd_card_c, gpclk1, _, _, _),
806 + PIN(12, spi_s, vc_spi3, sd_card_c, sd_card_d, _, _, _, _),
807 + PIN(13, spi_s, vc_spi3, sd_card_c, sd_card_d, _, _, _, _),
808 + PIN(14, spi_s, uui, arm_jtag, vc_pwm0, vc_i2c0, sd_card_d, _, _),
809 + PIN(15, spi_s, uui, arm_jtag, vc_pwm0, vc_i2c0, gpclk0, _, _),
810 + PIN(18, sd_card_f, vc_pwm1, _, _, _, _, _, _),
811 + PIN(19, sd_card_f, usb_pwr, vc_pwm1, _, _, _, _, _),
812 + PIN(20, vc_i2c3, uui, vc_uart0, arm_jtag, vc_uart2, _, _, _),
813 + PIN(21, vc_i2c3, uui, vc_uart0, arm_jtag, vc_uart2, _, _, _),
814 + PIN(22, sd_card_f, vc_uart0, vc_i2c3, _, _, _, _, _),
815 + PIN(23, vc_uart0, vc_i2c3, _, _, _, _, _, _),
816 + PIN(24, sd_card_b, vc_spi0, arm_jtag, uart0, usb_pwr, vc_uart2, vc_uart0, _),
817 + PIN(25, sd_card_b, vc_spi0, arm_jtag, uart0, usb_pwr, vc_uart2, vc_uart0, _),
818 + PIN(26, sd_card_b, vc_spi0, arm_jtag, uart0, usb_vbus, vc_uart2, vc_spi0, _),
819 + PIN(27, sd_card_b, vc_spi0, arm_jtag, uart0, vc_uart2, vc_spi0, _, _),
820 + PIN(28, sd_card_b, vc_spi0, arm_jtag, vc_i2c0, vc_spi0, _, _, _),
821 + PIN(29, arm_jtag, vc_i2c0, vc_spi0, _, _, _, _, _),
822 + PIN(30, sd2, gpclk0, vc_pwm0, _, _, _, _, _),
823 + PIN(31, sd2, vc_spi3, vc_pwm0, _, _, _, _, _),
824 + PIN(32, sd2, vc_spi3, vc_uart3, _, _, _, _, _),
825 + PIN(33, sd2, vc_spi3, vc_uart3, _, _, _, _, _),
826 + PIN(34, sd2, vc_spi3, vc_i2c5, _, _, _, _, _),
827 + PIN(35, sd2, vc_spi3, vc_i2c5, _, _, _, _, _),
828 +};
829 +
830 +static inline u32 bcm2712_reg_rd(struct bcm2712_pinctrl *pc, unsigned reg)
831 +{
832 + return readl(pc->base + reg);
833 +}
834 +
835 +static inline void bcm2712_reg_wr(struct bcm2712_pinctrl *pc, unsigned reg,
836 + u32 val)
837 +{
838 + writel(val, pc->base + reg);
839 +}
840 +
841 +static enum bcm2712_funcs bcm2712_pinctrl_fsel_get(
842 + struct bcm2712_pinctrl *pc, unsigned pin)
843 +{
844 + u32 bit = pc->pin_regs[pin].mux_bit;
845 + enum bcm2712_funcs func;
846 + int fsel;
847 + u32 val;
848 +
849 + if (!bit)
850 + return func_gpio;
851 +
852 + val = bcm2712_reg_rd(pc, BIT_TO_REG(bit));
853 + fsel = (val >> BIT_TO_SHIFT(bit)) & BCM2712_FSEL_MASK;
854 + func = pc->pin_funcs[pin].funcs[fsel];
855 + if (func >= func_count)
856 + func = (enum bcm2712_funcs)fsel;
857 +
858 + dev_dbg(pc->dev, "get %04x: %08x (%u => %s)\n",
859 + BIT_TO_REG(bit), val, pin,
860 + bcm2712_func_names[func]);
861 +
862 + return func;
863 +}
864 +
865 +static void bcm2712_pinctrl_fsel_set(
866 + struct bcm2712_pinctrl *pc, unsigned pin,
867 + enum bcm2712_funcs func)
868 +{
869 + u32 bit = pc->pin_regs[pin].mux_bit, val;
870 + const u8 *pin_funcs;
871 + unsigned long flags;
872 + int fsel;
873 + int cur;
874 + int i;
875 +
876 + if (!bit || func >= func_count)
877 + return;
878 +
879 + fsel = BCM2712_FSEL_COUNT;
880 +
881 + if (func >= BCM2712_FSEL_COUNT) {
882 + /* Convert to an fsel number */
883 + pin_funcs = pc->pin_funcs[pin].funcs;
884 + for (i = 1; i < BCM2712_FSEL_COUNT; i++) {
885 + if (pin_funcs[i - 1] == func) {
886 + fsel = i;
887 + break;
888 + }
889 + }
890 + } else {
891 + fsel = (enum bcm2712_funcs)func;
892 + }
893 + if (fsel >= BCM2712_FSEL_COUNT)
894 + return;
895 +
896 + spin_lock_irqsave(&pc->lock, flags);
897 +
898 + val = bcm2712_reg_rd(pc, BIT_TO_REG(bit));
899 + cur = (val >> BIT_TO_SHIFT(bit)) & BCM2712_FSEL_MASK;
900 +
901 + dev_dbg(pc->dev, "read %04x: %08x (%u => %s)\n",
902 + BIT_TO_REG(bit), val, pin,
903 + bcm2712_func_names[cur]);
904 +
905 + if (cur != fsel) {
906 + val &= ~(BCM2712_FSEL_MASK << BIT_TO_SHIFT(bit));
907 + val |= fsel << BIT_TO_SHIFT(bit);
908 +
909 + dev_dbg(pc->dev, "write %04x: %08x (%u <= %s)\n",
910 + BIT_TO_REG(bit), val, pin,
911 + bcm2712_func_names[fsel]);
912 + bcm2712_reg_wr(pc, BIT_TO_REG(bit), val);
913 + }
914 +
915 + spin_unlock_irqrestore(&pc->lock, flags);
916 +}
917 +
918 +static int bcm2712_pctl_get_groups_count(struct pinctrl_dev *pctldev)
919 +{
920 + struct bcm2712_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
921 +
922 + return pc->pctl_desc.npins;
923 +}
924 +
925 +static const char *bcm2712_pctl_get_group_name(struct pinctrl_dev *pctldev,
926 + unsigned selector)
927 +{
928 + struct bcm2712_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
929 +
930 + return pc->gpio_groups[selector];
931 +}
932 +
933 +static int bcm2712_pctl_get_group_pins(struct pinctrl_dev *pctldev,
934 + unsigned selector,
935 + const unsigned **pins,
936 + unsigned *num_pins)
937 +{
938 + struct bcm2712_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
939 +
940 + *pins = &pc->pctl_desc.pins[selector].number;
941 + *num_pins = 1;
942 +
943 + return 0;
944 +}
945 +
946 +static void bcm2712_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
947 + struct seq_file *s,
948 + unsigned offset)
949 +{
950 + struct bcm2712_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
951 + enum bcm2712_funcs fsel = bcm2712_pinctrl_fsel_get(pc, offset);
952 + const char *fname = bcm2712_func_names[fsel];
953 +
954 + seq_printf(s, "function %s", fname);
955 +}
956 +
957 +static void bcm2712_pctl_dt_free_map(struct pinctrl_dev *pctldev,
958 + struct pinctrl_map *maps, unsigned num_maps)
959 +{
960 + int i;
961 +
962 + for (i = 0; i < num_maps; i++)
963 + if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
964 + kfree(maps[i].data.configs.configs);
965 +
966 + kfree(maps);
967 +}
968 +
969 +static const struct pinctrl_ops bcm2712_pctl_ops = {
970 + .get_groups_count = bcm2712_pctl_get_groups_count,
971 + .get_group_name = bcm2712_pctl_get_group_name,
972 + .get_group_pins = bcm2712_pctl_get_group_pins,
973 + .pin_dbg_show = bcm2712_pctl_pin_dbg_show,
974 + .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
975 + .dt_free_map = bcm2712_pctl_dt_free_map,
976 +};
977 +
978 +static int bcm2712_pmx_free(struct pinctrl_dev *pctldev,
979 + unsigned offset)
980 +{
981 + struct bcm2712_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
982 +
983 + /* disable by setting to GPIO */
984 + bcm2712_pinctrl_fsel_set(pc, offset, func_gpio);
985 + return 0;
986 +}
987 +
988 +static int bcm2712_pmx_get_functions_count(struct pinctrl_dev *pctldev)
989 +{
990 + return func_count;
991 +}
992 +
993 +static const char *bcm2712_pmx_get_function_name(struct pinctrl_dev *pctldev,
994 + unsigned selector)
995 +{
996 + return (selector < func_count) ? bcm2712_func_names[selector] : NULL;
997 +}
998 +
999 +static int bcm2712_pmx_get_function_groups(struct pinctrl_dev *pctldev,
1000 + unsigned selector,
1001 + const char * const **groups,
1002 + unsigned * const num_groups)
1003 +{
1004 + struct bcm2712_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1005 + /* every pin can do every function */
1006 + *groups = pc->gpio_groups;
1007 + *num_groups = pc->pctl_desc.npins;
1008 +
1009 + return 0;
1010 +}
1011 +
1012 +static int bcm2712_pmx_set(struct pinctrl_dev *pctldev,
1013 + unsigned func_selector,
1014 + unsigned group_selector)
1015 +{
1016 + struct bcm2712_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1017 +
1018 + bcm2712_pinctrl_fsel_set(pc, group_selector, func_selector);
1019 +
1020 + return 0;
1021 +}
1022 +static int bcm2712_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
1023 + struct pinctrl_gpio_range *range,
1024 + unsigned pin)
1025 +{
1026 + struct bcm2712_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1027 +
1028 + bcm2712_pinctrl_fsel_set(pc, pin, func_gpio);
1029 +
1030 + return 0;
1031 +}
1032 +
1033 +static void bcm2712_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
1034 + struct pinctrl_gpio_range *range,
1035 + unsigned offset)
1036 +{
1037 + struct bcm2712_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1038 +
1039 + /* disable by setting to GPIO */
1040 + bcm2712_pinctrl_fsel_set(pc, offset, func_gpio);
1041 +}
1042 +
1043 +static const struct pinmux_ops bcm2712_pmx_ops = {
1044 + .free = bcm2712_pmx_free,
1045 + .get_functions_count = bcm2712_pmx_get_functions_count,
1046 + .get_function_name = bcm2712_pmx_get_function_name,
1047 + .get_function_groups = bcm2712_pmx_get_function_groups,
1048 + .set_mux = bcm2712_pmx_set,
1049 + .gpio_request_enable = bcm2712_pmx_gpio_request_enable,
1050 + .gpio_disable_free = bcm2712_pmx_gpio_disable_free,
1051 +};
1052 +
1053 +static unsigned int bcm2712_pull_config_get(struct bcm2712_pinctrl *pc,
1054 + unsigned int pin)
1055 +{
1056 + u32 bit = pc->pin_regs[pin].pad_bit, val;
1057 +
1058 + if (unlikely(bit == REG_BIT_INVALID))
1059 + return BCM2712_PULL_NONE;
1060 +
1061 + val = bcm2712_reg_rd(pc, BIT_TO_REG(bit));
1062 + return (val >> BIT_TO_SHIFT(bit)) & BCM2712_PULL_MASK;
1063 +}
1064 +
1065 +static void bcm2712_pull_config_set(struct bcm2712_pinctrl *pc,
1066 + unsigned int pin, unsigned int arg)
1067 +{
1068 + u32 bit = pc->pin_regs[pin].pad_bit, val;
1069 + unsigned long flags;
1070 +
1071 + if (unlikely(bit == REG_BIT_INVALID)) {
1072 + dev_warn(pc->dev, "can't set pulls for %s\n", pc->gpio_groups[pin]);
1073 + return;
1074 + }
1075 +
1076 + spin_lock_irqsave(&pc->lock, flags);
1077 +
1078 + val = bcm2712_reg_rd(pc, BIT_TO_REG(bit));
1079 + val &= ~(BCM2712_PULL_MASK << BIT_TO_SHIFT(bit));
1080 + val |= (arg << BIT_TO_SHIFT(bit));
1081 + bcm2712_reg_wr(pc, BIT_TO_REG(bit), val);
1082 +
1083 + spin_unlock_irqrestore(&pc->lock, flags);
1084 +}
1085 +
1086 +static int bcm2712_pinconf_get(struct pinctrl_dev *pctldev,
1087 + unsigned pin, unsigned long *config)
1088 +{
1089 + struct bcm2712_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1090 + enum pin_config_param param = pinconf_to_config_param(*config);
1091 + u32 arg;
1092 +
1093 + switch (param) {
1094 + case PIN_CONFIG_BIAS_DISABLE:
1095 + arg = (bcm2712_pull_config_get(pc, pin) == BCM2712_PULL_NONE);
1096 + break;
1097 + case PIN_CONFIG_BIAS_PULL_DOWN:
1098 + arg = (bcm2712_pull_config_get(pc, pin) == BCM2712_PULL_DOWN);
1099 + break;
1100 + case PIN_CONFIG_BIAS_PULL_UP:
1101 + arg = (bcm2712_pull_config_get(pc, pin) == BCM2712_PULL_UP);
1102 + break;
1103 + default:
1104 + return -ENOTSUPP;
1105 + }
1106 +
1107 + *config = pinconf_to_config_packed(param, arg);
1108 +
1109 + return -ENOTSUPP;
1110 +}
1111 +
1112 +static int bcm2712_pinconf_set(struct pinctrl_dev *pctldev,
1113 + unsigned int pin, unsigned long *configs,
1114 + unsigned int num_configs)
1115 +{
1116 + struct bcm2712_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1117 + u32 param, arg;
1118 + int i;
1119 +
1120 + for (i = 0; i < num_configs; i++) {
1121 + param = pinconf_to_config_param(configs[i]);
1122 + arg = pinconf_to_config_argument(configs[i]);
1123 +
1124 + switch (param) {
1125 + case PIN_CONFIG_BIAS_DISABLE:
1126 + bcm2712_pull_config_set(pc, pin, BCM2712_PULL_NONE);
1127 + break;
1128 + case PIN_CONFIG_BIAS_PULL_DOWN:
1129 + bcm2712_pull_config_set(pc, pin, BCM2712_PULL_DOWN);
1130 + break;
1131 + case PIN_CONFIG_BIAS_PULL_UP:
1132 + bcm2712_pull_config_set(pc, pin, BCM2712_PULL_UP);
1133 + break;
1134 + default:
1135 + return -ENOTSUPP;
1136 + }
1137 + } /* for each config */
1138 +
1139 + return 0;
1140 +}
1141 +
1142 +static const struct pinconf_ops bcm2712_pinconf_ops = {
1143 + .is_generic = true,
1144 + .pin_config_get = bcm2712_pinconf_get,
1145 + .pin_config_set = bcm2712_pinconf_set,
1146 +};
1147 +
1148 +static const struct pinctrl_desc bcm2712_c0_pinctrl_desc = {
1149 + .name = "pinctrl-bcm2712",
1150 + .pins = bcm2712_c0_gpio_pins,
1151 + .npins = ARRAY_SIZE(bcm2712_c0_gpio_pins),
1152 + .pctlops = &bcm2712_pctl_ops,
1153 + .pmxops = &bcm2712_pmx_ops,
1154 + .confops = &bcm2712_pinconf_ops,
1155 + .owner = THIS_MODULE,
1156 +};
1157 +
1158 +static const struct pinctrl_desc bcm2712_c0_aon_pinctrl_desc = {
1159 + .name = "aon-pinctrl-bcm2712",
1160 + .pins = bcm2712_c0_aon_gpio_pins,
1161 + .npins = ARRAY_SIZE(bcm2712_c0_aon_gpio_pins),
1162 + .pctlops = &bcm2712_pctl_ops,
1163 + .pmxops = &bcm2712_pmx_ops,
1164 + .confops = &bcm2712_pinconf_ops,
1165 + .owner = THIS_MODULE,
1166 +};
1167 +
1168 +static const struct pinctrl_desc bcm2712_d0_pinctrl_desc = {
1169 + .name = "pinctrl-bcm2712",
1170 + .pins = bcm2712_d0_gpio_pins,
1171 + .npins = ARRAY_SIZE(bcm2712_d0_gpio_pins),
1172 + .pctlops = &bcm2712_pctl_ops,
1173 + .pmxops = &bcm2712_pmx_ops,
1174 + .confops = &bcm2712_pinconf_ops,
1175 + .owner = THIS_MODULE,
1176 +};
1177 +
1178 +static const struct pinctrl_desc bcm2712_d0_aon_pinctrl_desc = {
1179 + .name = "aon-pinctrl-bcm2712",
1180 + .pins = bcm2712_d0_aon_gpio_pins,
1181 + .npins = ARRAY_SIZE(bcm2712_d0_aon_gpio_pins),
1182 + .pctlops = &bcm2712_pctl_ops,
1183 + .pmxops = &bcm2712_pmx_ops,
1184 + .confops = &bcm2712_pinconf_ops,
1185 + .owner = THIS_MODULE,
1186 +};
1187 +
1188 +static const struct pinctrl_gpio_range bcm2712_c0_pinctrl_gpio_range = {
1189 + .name = "pinctrl-bcm2712",
1190 + .npins = ARRAY_SIZE(bcm2712_c0_gpio_pins),
1191 +};
1192 +
1193 +static const struct pinctrl_gpio_range bcm2712_c0_aon_pinctrl_gpio_range = {
1194 + .name = "aon-pinctrl-bcm2712",
1195 + .npins = ARRAY_SIZE(bcm2712_c0_aon_gpio_pins),
1196 +};
1197 +
1198 +static const struct pinctrl_gpio_range bcm2712_d0_pinctrl_gpio_range = {
1199 + .name = "pinctrl-bcm2712",
1200 + .npins = ARRAY_SIZE(bcm2712_d0_gpio_pins),
1201 +};
1202 +
1203 +static const struct pinctrl_gpio_range bcm2712_d0_aon_pinctrl_gpio_range = {
1204 + .name = "aon-pinctrl-bcm2712",
1205 + .npins = ARRAY_SIZE(bcm2712_d0_aon_gpio_pins),
1206 +};
1207 +
1208 +static const struct bcm_plat_data bcm2712_c0_plat_data = {
1209 + .pctl_desc = &bcm2712_c0_pinctrl_desc,
1210 + .gpio_range = &bcm2712_c0_pinctrl_gpio_range,
1211 + .pin_regs = bcm2712_c0_gpio_pin_regs,
1212 + .pin_funcs = bcm2712_c0_gpio_pin_funcs,
1213 +};
1214 +
1215 +static const struct bcm_plat_data bcm2712_c0_aon_plat_data = {
1216 + .pctl_desc = &bcm2712_c0_aon_pinctrl_desc,
1217 + .gpio_range = &bcm2712_c0_aon_pinctrl_gpio_range,
1218 + .pin_regs = bcm2712_c0_aon_gpio_pin_regs,
1219 + .pin_funcs = bcm2712_c0_aon_gpio_pin_funcs,
1220 +};
1221 +
1222 +static const struct bcm_plat_data bcm2712_d0_plat_data = {
1223 + .pctl_desc = &bcm2712_d0_pinctrl_desc,
1224 + .gpio_range = &bcm2712_d0_pinctrl_gpio_range,
1225 + .pin_regs = bcm2712_d0_gpio_pin_regs,
1226 + .pin_funcs = bcm2712_d0_gpio_pin_funcs,
1227 +};
1228 +
1229 +static const struct bcm_plat_data bcm2712_d0_aon_plat_data = {
1230 + .pctl_desc = &bcm2712_d0_aon_pinctrl_desc,
1231 + .gpio_range = &bcm2712_d0_aon_pinctrl_gpio_range,
1232 + .pin_regs = bcm2712_d0_aon_gpio_pin_regs,
1233 + .pin_funcs = bcm2712_d0_aon_gpio_pin_funcs,
1234 +};
1235 +
1236 +static const struct of_device_id bcm2712_pinctrl_match[] = {
1237 + {
1238 + .compatible = "brcm,bcm2712-pinctrl",
1239 + .data = &bcm2712_c0_plat_data,
1240 + },
1241 + {
1242 + .compatible = "brcm,bcm2712-aon-pinctrl",
1243 + .data = &bcm2712_c0_aon_plat_data,
1244 + },
1245 +
1246 + {
1247 + .compatible = "brcm,bcm2712c0-pinctrl",
1248 + .data = &bcm2712_c0_plat_data,
1249 + },
1250 + {
1251 + .compatible = "brcm,bcm2712c0-aon-pinctrl",
1252 + .data = &bcm2712_c0_aon_plat_data,
1253 + },
1254 +
1255 + {
1256 + .compatible = "brcm,bcm2712d0-pinctrl",
1257 + .data = &bcm2712_d0_plat_data,
1258 + },
1259 + {
1260 + .compatible = "brcm,bcm2712d0-aon-pinctrl",
1261 + .data = &bcm2712_d0_aon_plat_data,
1262 + },
1263 + {}
1264 +};
1265 +
1266 +static int bcm2712_pinctrl_probe(struct platform_device *pdev)
1267 +{
1268 + struct device *dev = &pdev->dev;
1269 + struct device_node *np = dev->of_node;
1270 + const struct bcm_plat_data *pdata;
1271 + const struct of_device_id *match;
1272 + struct bcm2712_pinctrl *pc;
1273 + const char **names;
1274 + int num_pins, i;
1275 +
1276 + match = of_match_node(bcm2712_pinctrl_match, np);
1277 + if (!match)
1278 + return -EINVAL;
1279 + pdata = match->data;
1280 +
1281 + pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1282 + if (!pc)
1283 + return -ENOMEM;
1284 +
1285 + platform_set_drvdata(pdev, pc);
1286 + pc->dev = dev;
1287 + spin_lock_init(&pc->lock);
1288 +
1289 + pc->base = devm_of_iomap(dev, np, 0, NULL);
1290 + if (IS_ERR(pc->base)) {
1291 + dev_err(dev, "could not get IO memory\n");
1292 + return PTR_ERR(pc->base);
1293 + }
1294 +
1295 + pc->pctl_desc = *pdata->pctl_desc;
1296 + num_pins = pc->pctl_desc.npins;
1297 + names = devm_kmalloc_array(dev, num_pins, sizeof(const char *),
1298 + GFP_KERNEL);
1299 + if (!names)
1300 + return -ENOMEM;
1301 + for (i = 0; i < num_pins; i++)
1302 + names[i] = pc->pctl_desc.pins[i].name;
1303 + pc->gpio_groups = names;
1304 + pc->pin_regs = pdata->pin_regs;
1305 + pc->pin_funcs = pdata->pin_funcs;
1306 + pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1307 + if (IS_ERR(pc->pctl_dev))
1308 + return PTR_ERR(pc->pctl_dev);
1309 +
1310 + pc->gpio_range = *pdata->gpio_range;
1311 + pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1312 +
1313 + return 0;
1314 +}
1315 +
1316 +static struct platform_driver bcm2712_pinctrl_driver = {
1317 + .probe = bcm2712_pinctrl_probe,
1318 + .driver = {
1319 + .name = MODULE_NAME,
1320 + .of_match_table = bcm2712_pinctrl_match,
1321 + .suppress_bind_attrs = true,
1322 + },
1323 +};
1324 +builtin_platform_driver(bcm2712_pinctrl_driver);
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