package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch

   1 --- /dev/null
   2 +++ b/configs/mt7622_linksys_e8450_defconfig
   3 @@ -0,0 +1,134 @@
   4 +CONFIG_ARM=y
   5 +CONFIG_POSITION_INDEPENDENT=y
   6 +CONFIG_ARCH_MEDIATEK=y
   7 +CONFIG_TARGET_MT7622=y
   8 +CONFIG_SYS_TEXT_BASE=0x41e00000
   9 +CONFIG_SYS_MALLOC_F_LEN=0x4000
  10 +CONFIG_USE_DEFAULT_ENV_FILE=y
  11 +CONFIG_BOARD_LATE_INIT=y
  12 +CONFIG_BOOTP_SEND_HOSTNAME=y
  13 +CONFIG_DEFAULT_ENV_FILE="linksys_e8450_env"
  14 +CONFIG_NR_DRAM_BANKS=1
  15 +CONFIG_DEBUG_UART_BASE=0x11002000
  16 +CONFIG_DEBUG_UART_CLOCK=25000000
  17 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-linksys-e8450-ubi"
  18 +CONFIG_DEBUG_UART=y
  19 +CONFIG_SMBIOS_PRODUCT_NAME=""
  20 +CONFIG_AUTOBOOT_KEYED=y
  21 +CONFIG_BOOTDELAY=30
  22 +CONFIG_AUTOBOOT_MENU_SHOW=y
  23 +CONFIG_CFB_CONSOLE_ANSI=y
  24 +CONFIG_BUTTON=y
  25 +CONFIG_BUTTON_GPIO=y
  26 +CONFIG_GPIO_HOG=y
  27 +CONFIG_CMD_ENV_FLAGS=y
  28 +CONFIG_FIT=y
  29 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
  30 +CONFIG_LED=y
  31 +CONFIG_LED_BLINK=y
  32 +CONFIG_LED_GPIO=y
  33 +CONFIG_LOGLEVEL=7
  34 +CONFIG_LOG=y
  35 +CONFIG_DEFAULT_FDT_FILE="mt7622-linksys-e8450"
  36 +CONFIG_SYS_PROMPT="MT7622> "
  37 +CONFIG_CMD_BOOTMENU=y
  38 +CONFIG_CMD_BOOTP=y
  39 +CONFIG_CMD_BUTTON=y
  40 +CONFIG_CMD_CDP=y
  41 +CONFIG_CMD_DHCP=y
  42 +CONFIG_CMD_DNS=y
  43 +CONFIG_CMD_ECHO=y
  44 +CONFIG_CMD_ENV_READMEM=y
  45 +CONFIG_CMD_ERASEENV=y
  46 +CONFIG_CMD_EXT4=y
  47 +CONFIG_CMD_FAT=y
  48 +CONFIG_CMD_FS_GENERIC=y
  49 +CONFIG_CMD_FS_UUID=y
  50 +CONFIG_CMD_GPIO=y
  51 +CONFIG_CMD_GPT=y
  52 +CONFIG_CMD_HASH=y
  53 +CONFIG_CMD_ITEST=y
  54 +CONFIG_CMD_LED=y
  55 +CONFIG_CMD_LICENSE=y
  56 +CONFIG_CMD_LINK_LOCAL=y
  57 +# CONFIG_CMD_MBR is not set
  58 +CONFIG_CMD_MTD=y
  59 +CONFIG_CMD_MTDPART=y
  60 +CONFIG_CMD_PCI=y
  61 +CONFIG_CMD_SF_TEST=y
  62 +CONFIG_CMD_PING=y
  63 +CONFIG_CMD_PXE=y
  64 +CONFIG_CMD_SMC=y
  65 +CONFIG_CMD_TFTPBOOT=y
  66 +CONFIG_CMD_TFTPSRV=y
  67 +CONFIG_CMD_UBI=y
  68 +CONFIG_CMD_UBI_RENAME=y
  69 +CONFIG_CMD_UBIFS=y
  70 +CONFIG_CMD_ASKENV=y
  71 +CONFIG_CMD_PART=y
  72 +CONFIG_CMD_PSTORE=y
  73 +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
  74 +CONFIG_CMD_RARP=y
  75 +CONFIG_CMD_SETEXPR=y
  76 +CONFIG_CMD_SLEEP=y
  77 +CONFIG_CMD_SNTP=y
  78 +CONFIG_CMD_SOURCE=y
  79 +CONFIG_CMD_USB=y
  80 +CONFIG_CMD_UUID=y
  81 +CONFIG_DISPLAY_CPUINFO=y
  82 +CONFIG_DM_REGULATOR=y
  83 +CONFIG_DM_REGULATOR_FIXED=y
  84 +CONFIG_DM_REGULATOR_GPIO=y
  85 +CONFIG_DM_USB=y
  86 +CONFIG_HUSH_PARSER=y
  87 +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
  88 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  89 +CONFIG_ENV_IS_IN_UBI=y
  90 +CONFIG_ENV_UBI_PART="ubi"
  91 +CONFIG_ENV_UBI_VOLUME="ubootenv"
  92 +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
  93 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
  94 +CONFIG_VERSION_VARIABLE=y
  95 +CONFIG_PARTITION_UUIDS=y
  96 +CONFIG_NETCONSOLE=y
  97 +CONFIG_REGMAP=y
  98 +CONFIG_SYSCON=y
  99 +CONFIG_CLK=y
 100 +CONFIG_DM_MTD=y
 101 +CONFIG_DM_GPIO=y
 102 +CONFIG_PHY=y
 103 +CONFIG_PHY_MTK_TPHY=y
 104 +CONFIG_PHY_FIXED=y
 105 +CONFIG_DM_ETH=y
 106 +CONFIG_MEDIATEK_ETH=y
 107 +CONFIG_PCI=y
 108 +CONFIG_MTD=y
 109 +CONFIG_MTD_UBI_FASTMAP=y
 110 +CONFIG_DM_PCI=y
 111 +CONFIG_PCIE_MEDIATEK=y
 112 +CONFIG_PINCTRL=y
 113 +CONFIG_PINCONF=y
 114 +CONFIG_PINCTRL_MT7622=y
 115 +CONFIG_POWER_DOMAIN=y
 116 +CONFIG_PRE_CONSOLE_BUFFER=y
 117 +CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
 118 +CONFIG_MTK_POWER_DOMAIN=y
 119 +CONFIG_RAM=y
 120 +CONFIG_DM_SERIAL=y
 121 +CONFIG_MTK_SERIAL=y
 122 +CONFIG_SPI=y
 123 +CONFIG_DM_SPI=y
 124 +CONFIG_MTK_SPI_NAND=y
 125 +CONFIG_MTK_SPI_NAND_MTD=y
 126 +CONFIG_SYSRESET_WATCHDOG=y
 127 +CONFIG_WDT_MTK=y
 128 +CONFIG_LZO=y
 129 +CONFIG_ZSTD=y
 130 +CONFIG_HEXDUMP=y
 131 +CONFIG_RANDOM_UUID=y
 132 +CONFIG_REGEX=y
 133 +CONFIG_USB=y
 134 +CONFIG_USB_HOST=y
 135 +CONFIG_USB_XHCI_HCD=y
 136 +CONFIG_USB_XHCI_MTK=y
 137 +CONFIG_USB_STORAGE=y
 138 --- /dev/null
 139 +++ b/arch/arm/dts/mt7622-linksys-e8450-ubi.dts
 140 @@ -0,0 +1,195 @@
 141 +// SPDX-License-Identifier: GPL-2.0
 142 +/*
 143 + * Copyright (c) 2019 MediaTek Inc.
 144 + * Author: Sam Shih <sam.shih@mediatek.com>
 145 + */
 146 +
 147 +/dts-v1/;
 148 +#include "mt7622.dtsi"
 149 +#include "mt7622-u-boot.dtsi"
 150 +
 151 +/ {
 152 +       #address-cells = <1>;
 153 +       #size-cells = <1>;
 154 +       model = "mt7622-linksys-e8450-ubi";
 155 +       compatible = "mediatek,mt7622", "linksys,e8450-ubi";
 156 +       chosen {
 157 +               stdout-path = &uart0;
 158 +               tick-timer = &timer0;
 159 +       };
 160 +
 161 +       aliases {
 162 +               spi0 = &snand;
 163 +       };
 164 +
 165 +       gpio-keys {
 166 +               compatible = "gpio-keys";
 167 +
 168 +               factory {
 169 +                       label = "reset";
 170 +                       gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 171 +               };
 172 +
 173 +               wps {
 174 +                       label = "wps";
 175 +                       gpios = <&gpio 102 GPIO_ACTIVE_LOW>;
 176 +               };
 177 +       };
 178 +
 179 +       gpio-leds {
 180 +               compatible = "gpio-leds";
 181 +
 182 +               led_power: power_blue {
 183 +                       label = "power:blue";
 184 +                       gpios = <&gpio 95 GPIO_ACTIVE_LOW>;
 185 +                       default-state = "on";
 186 +               };
 187 +
 188 +               power_orange {
 189 +                       label = "power:orange";
 190 +                       gpios = <&gpio 96 GPIO_ACTIVE_LOW>;
 191 +                       default-state = "off";
 192 +               };
 193 +
 194 +               inet_blue {
 195 +                       label = "inet:blue";
 196 +                       gpios = <&gpio 97 GPIO_ACTIVE_LOW>;
 197 +                       default-state = "off";
 198 +               };
 199 +
 200 +               inet_orange {
 201 +                       label = "inet:orange";
 202 +                       gpios = <&gpio 98 GPIO_ACTIVE_LOW>;
 203 +                       default-state = "off";
 204 +               };
 205 +       };
 206 +
 207 +       memory@40000000 {
 208 +               device_type = "memory";
 209 +               reg = <0x40000000 0x20000000>;
 210 +       };
 211 +
 212 +       reg_1p8v: regulator-1p8v {
 213 +               compatible = "regulator-fixed";
 214 +               regulator-name = "fixed-1.8V";
 215 +               regulator-min-microvolt = <1800000>;
 216 +               regulator-max-microvolt = <1800000>;
 217 +               regulator-boot-on;
 218 +               regulator-always-on;
 219 +       };
 220 +
 221 +       reg_3p3v: regulator-3p3v {
 222 +               compatible = "regulator-fixed";
 223 +               regulator-name = "fixed-3.3V";
 224 +               regulator-min-microvolt = <3300000>;
 225 +               regulator-max-microvolt = <3300000>;
 226 +               regulator-boot-on;
 227 +               regulator-always-on;
 228 +       };
 229 +
 230 +       reg_5v: regulator-5v {
 231 +               compatible = "regulator-fixed";
 232 +               regulator-name = "fixed-5V";
 233 +               regulator-min-microvolt = <5000000>;
 234 +               regulator-max-microvolt = <5000000>;
 235 +               regulator-boot-on;
 236 +               regulator-always-on;
 237 +       };
 238 +};
 239 +
 240 +&pcie {
 241 +       pinctrl-names = "default";
 242 +       pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 243 +       status = "okay";
 244 +
 245 +       pcie@0,0 {
 246 +               status = "okay";
 247 +       };
 248 +
 249 +       pcie@1,0 {
 250 +               status = "okay";
 251 +       };
 252 +};
 253 +
 254 +&pinctrl {
 255 +       pcie0_pins: pcie0-pins {
 256 +               mux {
 257 +                       function = "pcie";
 258 +                       groups = "pcie0_pad_perst",
 259 +                                "pcie0_1_waken",
 260 +                                "pcie0_1_clkreq";
 261 +               };
 262 +       };
 263 +
 264 +       pcie1_pins: pcie1-pins {
 265 +               mux {
 266 +                       function = "pcie";
 267 +                       groups = "pcie1_pad_perst",
 268 +                                "pcie1_0_waken",
 269 +                                "pcie1_0_clkreq";
 270 +               };
 271 +       };
 272 +
 273 +       snfi_pins: snfi-pins {
 274 +               mux {
 275 +                       function = "flash";
 276 +                       groups = "snfi";
 277 +               };
 278 +       };
 279 +
 280 +       uart0_pins: uart0 {
 281 +               mux {
 282 +                       function = "uart";
 283 +                       groups = "uart0_0_tx_rx" ;
 284 +               };
 285 +       };
 286 +
 287 +       watchdog_pins: watchdog-default {
 288 +               mux {
 289 +                       function = "watchdog";
 290 +                       groups = "watchdog";
 291 +               };
 292 +       };
 293 +};
 294 +
 295 +&snand {
 296 +       pinctrl-names = "default";
 297 +       pinctrl-0 = <&snfi_pins>;
 298 +       status = "okay";
 299 +       quad-spi;
 300 +};
 301 +
 302 +&uart0 {
 303 +       pinctrl-names = "default";
 304 +       pinctrl-0 = <&uart0_pins>;
 305 +       status = "okay";
 306 +};
 307 +
 308 +&watchdog {
 309 +       pinctrl-names = "default";
 310 +       pinctrl-0 = <&watchdog_pins>;
 311 +       status = "okay";
 312 +};
 313 +
 314 +&eth {
 315 +       status = "okay";
 316 +       mediatek,gmac-id = <0>;
 317 +       phy-mode = "sgmii";
 318 +       mediatek,switch = "mt7531";
 319 +       reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
 320 +
 321 +       fixed-link {
 322 +               speed = <1000>;
 323 +               full-duplex;
 324 +       };
 325 +};
 326 +
 327 +&ssusb {
 328 +       vusb33-supply = <&reg_3p3v>;
 329 +       vbus-supply = <&reg_5v>;
 330 +       status = "okay";
 331 +};
 332 +
 333 +&u3phy {
 334 +       status = "okay";
 335 +};
 336 --- a/arch/arm/dts/Makefile
 337 +++ b/arch/arm/dts/Makefile
 338 @@ -1007,6 +1007,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 339         mt7622-rfb.dtb \
 340         mt7623a-unielec-u7623-02-emmc.dtb \
 341         mt7622-bananapi-bpi-r64.dtb \
 342 +       mt7622-linksys-e8450-ubi.dtb \
 343         mt7623n-bananapi-bpi-r2.dtb \
 344         mt7629-rfb.dtb \
 345         mt8512-bm1-emmc.dtb \
 346 --- /dev/null
 347 +++ b/linksys_e8450_env
 348 @@ -0,0 +1,57 @@
 349 +mtdparts=spi-nand0:512k(bl2),1280k(fip),1024k(factory),256k(reserved),-(ubi)
 350 +ethaddr_factory=mtd read spi-nand0 0x40080000 0x220000 0x20000 && env readmem -b ethaddr 0x4009fff4 0x6 ; setenv ethaddr_factory
 351 +ipaddr=192.168.1.1
 352 +serverip=192.168.1.254
 353 +loadaddr=0x4007ff28
 354 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
 355 +bootdelay=0
 356 +bootfile=openwrt-mediatek-mt7622-linksys_e8450-ubi-initramfs-recovery.itb
 357 +bootfile_bl2=openwrt-mediatek-mt7622-linksys_e8450-ubi-preloader.bin
 358 +bootfile_fip=openwrt-mediatek-mt7622-linksys_e8450-ubi-bl31-uboot.fip
 359 +bootfile_upg=openwrt-mediatek-mt7622-linksys_e8450-ubi-squashfs-sysupgrade.itb
 360 +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
 361 +bootmenu_default=0
 362 +bootmenu_delay=0
 363 +bootmenu_title=      \e[0;34m( ( ( \e[1;39mOpenWrt\e[0;34m ) ) )\e[0m
 364 +bootmenu_0=Initialize environment.=run _firstboot
 365 +bootmenu_0d=Run default boot command.=run boot_default
 366 +bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
 367 +bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return
 368 +bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return
 369 +bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; run boot_tftp_production ; setenv noboot ; run bootmenu_confirm_return
 370 +bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; run boot_tftp_recovery ; setenv noboot ; run bootmenu_confirm_return
 371 +bootmenu_6=\e[31mLoad BL31+U-Boot FIP via TFTP then write to flash.\e[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
 372 +bootmenu_7=\e[31mLoad BL2 preloader via TFTP then write to flash.\e[0m=run boot_tftp_write_preloader ; run bootmenu_confirm_return
 373 +bootmenu_8=Reboot.=reset
 374 +bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
 375 +boot_first=if button reset ; then run boot_tftp_forever ; fi ; setenv flag_recover 1 ; bootmenu
 376 +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; run boot_tftp_forever
 377 +boot_production=led power:blue on ; run ubi_read_production && bootm $loadaddr
 378 +boot_production_or_recovery=run boot_production ; run boot_recovery
 379 +boot_recovery=led power:blue off ; led power:orange on ; run check_recovery
 380 +boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip
 381 +boot_serial_write_preloader=loadx $loadaddr 115200 && run boot_write_preloader
 382 +boot_tftp_forever=led inet:blue on ; while true ; do run boot_tftp_recovery ; led inet:blue off ; led inet:orange on ; sleep 1 ; done
 383 +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && ubi part ubi && run ubi_write_production ubi_prepare_rootfs ; if env exists noboot ; then else bootm $loadaddr ; fi
 384 +boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && ubi part ubi && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi
 385 +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr
 386 +boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip
 387 +boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader
 388 +boot_ubi=ubi part ubi && run boot_production_or_recovery
 389 +boot_write_fip=mtd erase spi-nand0 0x80000 0x140000 && mtd write spi-nand0 $loadaddr 0x80000 0x140000
 390 +boot_write_preloader=mtd erase spi-nand0 0x0 0x80000 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000
 391 +check_recovery=run ubi_read_recovery ; if iminfo $loadaddr ; then bootm $loadaddr ; else ubi remove recovery ; fi
 392 +check_ubi=ubi part ubi || run ubi_format
 393 +reset_factory=ubi part ubi ; ubi write 0x0 ubootenv 0x0 ; ubi write 0x0 ubootenv2 0x0 ; ubi remove rootfs_data
 394 +ubi_format=ubi detach ; mtd erase spi-nand0 0x300000 0x7D00000 && ubi part ubi ; reset
 395 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 396 +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
 397 +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
 398 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
 399 +ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
 400 +ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
 401 +_create_env=ubi create ubootenv 0x100000 dynamic ; ubi create ubootenv2 0x100000 dynamic
 402 +_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv || run ubi_format ; saveenv || run ubi_format
 403 +_firstboot=setenv _firstboot ; led power:orange on ; run _switch_to_menu ; run ethaddr_factory ; run check_ubi ; run _init_env ; run boot_first
 404 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 405 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       \e[33m$ver\e[0m"