board/CZ.NIC/turris_omnia/turris_omnia.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
   4  * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
   5  *
   6  * Derived from the code for
   7  *   Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
   8  */
   9
  10 #include <common.h>
  11 #include <environment.h>
  12 #include <i2c.h>
  13 #include <miiphy.h>
  14 #include <netdev.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/soc.h>
  18 #include <dm/uclass.h>
  19 #include <fdt_support.h>
  20 #include <time.h>
  21
  22 #ifdef CONFIG_ATSHA204A
  23 # include <atsha204a-i2c.h>
  24 #endif
  25
  26 #ifdef CONFIG_WDT_ORION
  27 # include <wdt.h>
  28 #endif
  29
  30 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  31 #include <../serdes/a38x/high_speed_env_spec.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define OMNIA_I2C_EEPROM_DM_NAME        "i2c@11000->i2cmux@70->i2c@0"
  36 #define OMNIA_I2C_EEPROM                0x54
  37 #define OMNIA_I2C_EEPROM_CONFIG_ADDR    0x0
  38 #define OMNIA_I2C_EEPROM_ADDRLEN        2
  39 #define OMNIA_I2C_EEPROM_MAGIC          0x0341a034
  40
  41 #define OMNIA_I2C_MCU_DM_NAME           "i2c@11000->i2cmux@70->i2c@0"
  42 #define OMNIA_I2C_MCU_ADDR_STATUS       0x1
  43 #define OMNIA_I2C_MCU_SATA              0x20
  44 #define OMNIA_I2C_MCU_CARDDET           0x10
  45 #define OMNIA_I2C_MCU                   0x2a
  46 #define OMNIA_I2C_MCU_WDT_ADDR          0x0b
  47
  48 #define OMNIA_ATSHA204_OTP_VERSION      0
  49 #define OMNIA_ATSHA204_OTP_SERIAL       1
  50 #define OMNIA_ATSHA204_OTP_MAC0         3
  51 #define OMNIA_ATSHA204_OTP_MAC1         4
  52
  53 #define MVTWSI_ARMADA_DEBUG_REG         0x8c
  54
  55 /*
  56  * Those values and defines are taken from the Marvell U-Boot version
  57  * "u-boot-2013.01-2014_T3.0"
  58  */
  59 #define OMNIA_GPP_OUT_ENA_LOW                                   \
  60         (~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |  \
  61            BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |  \
  62            BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  63 #define OMNIA_GPP_OUT_ENA_MID                                   \
  64         (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |       \
  65            BIT(16) | BIT(17) | BIT(18)))
  66
  67 #define OMNIA_GPP_OUT_VAL_LOW   0x0
  68 #define OMNIA_GPP_OUT_VAL_MID   0x0
  69 #define OMNIA_GPP_POL_LOW       0x0
  70 #define OMNIA_GPP_POL_MID       0x0
  71
  72 static struct serdes_map board_serdes_map_pex[] = {
  73         {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  74         {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  75         {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  76         {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  77         {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  78         {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  79 };
  80
  81 static struct serdes_map board_serdes_map_sata[] = {
  82         {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  83         {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  84         {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  85         {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  86         {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  87         {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  88 };
  89
  90 static bool omnia_detect_sata(void)
  91 {
  92         struct udevice *bus, *dev;
  93         int ret, retry = 3;
  94         u16 mode;
  95
  96         puts("SERDES0 card detect: ");
  97
  98         if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) {
  99                 puts("Cannot find MCU bus!\n");
 100                 return false;
 101         }
 102
 103         ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev);
 104         if (ret) {
 105                 puts("Cannot get MCU chip!\n");
 106                 return false;
 107         }
 108
 109         for (; retry > 0; --retry) {
 110                 ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2);
 111                 if (!ret)
 112                         break;
 113         }
 114
 115         if (!retry) {
 116                 puts("I2C read failed! Default PEX\n");
 117                 return false;
 118         }
 119
 120         if (!(mode & OMNIA_I2C_MCU_CARDDET)) {
 121                 puts("NONE\n");
 122                 return false;
 123         }
 124
 125         if (mode & OMNIA_I2C_MCU_SATA) {
 126                 puts("SATA\n");
 127                 return true;
 128         } else {
 129                 puts("PEX\n");
 130                 return false;
 131         }
 132 }
 133
 134 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
 135 {
 136         if (omnia_detect_sata()) {
 137                 *serdes_map_array = board_serdes_map_sata;
 138                 *count = ARRAY_SIZE(board_serdes_map_sata);
 139         } else {
 140                 *serdes_map_array = board_serdes_map_pex;
 141                 *count = ARRAY_SIZE(board_serdes_map_pex);
 142         }
 143
 144         return 0;
 145 }
 146
 147 struct omnia_eeprom {
 148         u32 magic;
 149         u32 ramsize;
 150         char region[4];
 151         u32 crc;
 152 };
 153
 154 static bool omnia_read_eeprom(struct omnia_eeprom *oep)
 155 {
 156         struct udevice *bus, *dev;
 157         int ret, crc, retry = 3;
 158
 159         if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) {
 160                 puts("Cannot find EEPROM bus\n");
 161                 return false;
 162         }
 163
 164         ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev);
 165         if (ret) {
 166                 puts("Cannot get EEPROM chip\n");
 167                 return false;
 168         }
 169
 170         for (; retry > 0; --retry) {
 171                 ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom));
 172                 if (ret)
 173                         continue;
 174
 175                 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
 176                         puts("I2C EEPROM missing magic number!\n");
 177                         continue;
 178                 }
 179
 180                 crc = crc32(0, (unsigned char *) oep,
 181                             sizeof(struct omnia_eeprom) - 4);
 182                 if (crc == oep->crc) {
 183                         break;
 184                 } else {
 185                         printf("CRC of EEPROM memory config failed! "
 186                                "calc=0x%04x saved=0x%04x\n", crc, oep->crc);
 187                 }
 188         }
 189
 190         if (!retry) {
 191                 puts("I2C EEPROM read failed!\n");
 192                 return false;
 193         }
 194
 195         return true;
 196 }
 197
 198 /*
 199  * Define the DDR layout / topology here in the board file. This will
 200  * be used by the DDR3 init code in the SPL U-Boot version to configure
 201  * the DDR3 controller.
 202  */
 203 static struct mv_ddr_topology_map board_topology_map_1g = {
 204         DEBUG_LEVEL_ERROR,
 205         0x1, /* active interfaces */
 206         /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
 207         { { { {0x1, 0, 0, 0},
 208               {0x1, 0, 0, 0},
 209               {0x1, 0, 0, 0},
 210               {0x1, 0, 0, 0},
 211               {0x1, 0, 0, 0} },
 212             SPEED_BIN_DDR_1600K,        /* speed_bin */
 213             MV_DDR_DEV_WIDTH_16BIT,     /* memory_width */
 214             MV_DDR_DIE_CAP_4GBIT,                       /* mem_size */
 215             MV_DDR_FREQ_800,            /* frequency */
 216             0, 0,                       /* cas_wl cas_l */
 217             MV_DDR_TEMP_NORMAL,         /* temperature */
 218             MV_DDR_TIM_2T} },           /* timing */
 219         BUS_MASK_32BIT,                 /* Busses mask */
 220         MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
 221         { {0} },                        /* raw spd data */
 222         {0}                             /* timing parameters */
 223 };
 224
 225 static struct mv_ddr_topology_map board_topology_map_2g = {
 226         DEBUG_LEVEL_ERROR,
 227         0x1, /* active interfaces */
 228         /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
 229         { { { {0x1, 0, 0, 0},
 230               {0x1, 0, 0, 0},
 231               {0x1, 0, 0, 0},
 232               {0x1, 0, 0, 0},
 233               {0x1, 0, 0, 0} },
 234             SPEED_BIN_DDR_1600K,        /* speed_bin */
 235             MV_DDR_DEV_WIDTH_16BIT,     /* memory_width */
 236             MV_DDR_DIE_CAP_8GBIT,                       /* mem_size */
 237             MV_DDR_FREQ_800,            /* frequency */
 238             0, 0,                       /* cas_wl cas_l */
 239             MV_DDR_TEMP_NORMAL,         /* temperature */
 240             MV_DDR_TIM_2T} },           /* timing */
 241         BUS_MASK_32BIT,                 /* Busses mask */
 242         MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
 243         { {0} },                        /* raw spd data */
 244         {0}                             /* timing parameters */
 245 };
 246
 247 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
 248 {
 249         static int mem = 0;
 250         struct omnia_eeprom oep;
 251
 252         /* Get the board config from EEPROM */
 253         if (mem == 0) {
 254                 if(!omnia_read_eeprom(&oep))
 255                         goto out;
 256
 257                 printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
 258
 259                 if (oep.ramsize == 0x2)
 260                         mem = 2;
 261                 else
 262                         mem = 1;
 263         }
 264
 265 out:
 266         /* Hardcoded fallback */
 267         if (mem == 0) {
 268                 puts("WARNING: Memory config from EEPROM read failed.\n");
 269                 puts("Falling back to default 1GiB map.\n");
 270                 mem = 1;
 271         }
 272
 273         /* Return the board topology as defined in the board code */
 274         if (mem == 1)
 275                 return &board_topology_map_1g;
 276         if (mem == 2)
 277                 return &board_topology_map_2g;
 278
 279         return &board_topology_map_1g;
 280 }
 281
 282 #ifndef CONFIG_SPL_BUILD
 283 static int set_regdomain(void)
 284 {
 285         struct omnia_eeprom oep;
 286         char rd[3] = {' ', ' ', 0};
 287
 288         if (omnia_read_eeprom(&oep))
 289                 memcpy(rd, &oep.region, 2);
 290         else
 291                 puts("EEPROM regdomain read failed.\n");
 292
 293         printf("Regdomain set to %s\n", rd);
 294         return env_set("regdomain", rd);
 295 }
 296 #endif
 297
 298 int board_early_init_f(void)
 299 {
 300         u32 i2c_debug_reg;
 301
 302         /* Configure MPP */
 303         writel(0x11111111, MVEBU_MPP_BASE + 0x00);
 304         writel(0x11111111, MVEBU_MPP_BASE + 0x04);
 305         writel(0x11244011, MVEBU_MPP_BASE + 0x08);
 306         writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
 307         writel(0x22200002, MVEBU_MPP_BASE + 0x10);
 308         writel(0x30042022, MVEBU_MPP_BASE + 0x14);
 309         writel(0x55550555, MVEBU_MPP_BASE + 0x18);
 310         writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
 311
 312         /* Set GPP Out value */
 313         writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
 314         writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
 315
 316         /* Set GPP Polarity */
 317         writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
 318         writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
 319
 320         /* Set GPP Out Enable */
 321         writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
 322         writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
 323
 324         /*
 325          * Disable I2C debug mode blocking 0x64 I2C address.
 326          * Note: that would be redundant once Turris Omnia migrates to DM_I2C,
 327          * because the mvtwsi driver includes equivalent code.
 328          */
 329         i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
 330         i2c_debug_reg &= ~(1<<18);
 331         writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
 332
 333         return 0;
 334 }
 335
 336 #ifndef CONFIG_SPL_BUILD
 337 static bool disable_mcu_watchdog(void)
 338 {
 339         struct udevice *bus, *dev;
 340         int ret, retry = 3;
 341         uchar buf[1] = {0x0};
 342
 343         if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) {
 344                 puts("Cannot find MCU bus! Can not disable MCU WDT.\n");
 345                 return false;
 346         }
 347
 348         ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev);
 349         if (ret) {
 350                 puts("Cannot get MCU chip! Can not disable MCU WDT.\n");
 351                 return false;
 352         }
 353
 354         for (; retry > 0; --retry)
 355                 if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1))
 356                         break;
 357
 358         if (retry <= 0) {
 359                 puts("I2C MCU watchdog failed to disable!\n");
 360                 return false;
 361         }
 362
 363         return true;
 364 }
 365 #endif
 366
 367 int board_init(void)
 368 {
 369         /* adress of boot parameters */
 370         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 371
 372 #ifndef CONFIG_SPL_BUILD
 373         if (disable_mcu_watchdog())
 374                 puts("Disabled MCU startup watchdog.\n");
 375
 376         set_regdomain();
 377 #endif
 378
 379         return 0;
 380 }
 381
 382 int board_late_init(void)
 383 {
 384 #ifndef CONFIG_SPL_BUILD
 385         set_regdomain();
 386 #endif
 387
 388         return 0;
 389 }
 390
 391 #ifdef CONFIG_ATSHA204A
 392 static struct udevice *get_atsha204a_dev(void)
 393 {
 394         static struct udevice *dev = NULL;
 395
 396         if (dev != NULL)
 397                 return dev;
 398
 399         if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
 400                 puts("Cannot find ATSHA204A on I2C bus!\n");
 401                 dev = NULL;
 402         }
 403
 404         return dev;
 405 }
 406 #endif
 407
 408 int checkboard(void)
 409 {
 410         u32 version_num, serial_num;
 411         int err = 1;
 412
 413 #ifdef CONFIG_ATSHA204A
 414         struct udevice *dev = get_atsha204a_dev();
 415
 416         if (dev) {
 417                 err = atsha204a_wakeup(dev);
 418                 if (err)
 419                         goto out;
 420
 421                 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
 422                                      OMNIA_ATSHA204_OTP_VERSION,
 423                                      (u8 *) &version_num);
 424                 if (err)
 425                         goto out;
 426
 427                 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
 428                                      OMNIA_ATSHA204_OTP_SERIAL,
 429                                      (u8 *) &serial_num);
 430                 if (err)
 431                         goto out;
 432
 433                 atsha204a_sleep(dev);
 434         }
 435
 436 out:
 437 #endif
 438
 439         if (err)
 440                 printf("Board: Turris Omnia (ver N/A). SN: N/A\n");
 441         else
 442                 printf("Board: Turris Omnia SNL %08X%08X\n",
 443                        be32_to_cpu(version_num), be32_to_cpu(serial_num));
 444
 445         return 0;
 446 }
 447
 448 static void increment_mac(u8 *mac)
 449 {
 450         int i;
 451
 452         for (i = 5; i >= 3; i--) {
 453                 mac[i] += 1;
 454                 if (mac[i])
 455                         break;
 456         }
 457 }
 458
 459 int misc_init_r(void)
 460 {
 461 #ifdef CONFIG_ATSHA204A
 462         int err;
 463         struct udevice *dev = get_atsha204a_dev();
 464         u8 mac0[4], mac1[4], mac[6];
 465
 466         if (!dev)
 467                 goto out;
 468
 469         err = atsha204a_wakeup(dev);
 470         if (err)
 471                 goto out;
 472
 473         err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
 474                              OMNIA_ATSHA204_OTP_MAC0, mac0);
 475         if (err)
 476                 goto out;
 477
 478         err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
 479                              OMNIA_ATSHA204_OTP_MAC1, mac1);
 480         if (err)
 481                 goto out;
 482
 483         atsha204a_sleep(dev);
 484
 485         mac[0] = mac0[1];
 486         mac[1] = mac0[2];
 487         mac[2] = mac0[3];
 488         mac[3] = mac1[1];
 489         mac[4] = mac1[2];
 490         mac[5] = mac1[3];
 491
 492         if (is_valid_ethaddr(mac))
 493                 eth_env_set_enetaddr("ethaddr", mac);
 494
 495         increment_mac(mac);
 496
 497         if (is_valid_ethaddr(mac))
 498                 eth_env_set_enetaddr("eth1addr", mac);
 499
 500         increment_mac(mac);
 501
 502         if (is_valid_ethaddr(mac))
 503                 eth_env_set_enetaddr("eth2addr", mac);
 504
 505 out:
 506 #endif
 507
 508         return 0;
 509 }
 510