arch/arm/mach-uniphier/sg-regs.h

   1 /*
   2  * UniPhier SG (SoC Glue) block registers
   3  *
   4  * Copyright (C) 2011-2015 Copyright (C) 2011-2015 Panasonic Corporation
   5  * Copyright (C) 2016-2017 Socionext Inc.
   6  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef UNIPHIER_SG_REGS_H
  12 #define UNIPHIER_SG_REGS_H
  13
  14 /* Base Address */
  15 #define SG_CTRL_BASE                    0x5f800000
  16 #define SG_DBG_BASE                     0x5f900000
  17
  18 /* Revision */
  19 #define SG_REVISION                     (SG_CTRL_BASE | 0x0000)
  20
  21 /* Memory Configuration */
  22 #define SG_MEMCONF                      (SG_CTRL_BASE | 0x0400)
  23
  24 #define SG_MEMCONF_CH0_SZ_MASK          ((0x1 << 10) | (0x03 << 0))
  25 #define SG_MEMCONF_CH0_SZ_64M           ((0x0 << 10) | (0x01 << 0))
  26 #define SG_MEMCONF_CH0_SZ_128M          ((0x0 << 10) | (0x02 << 0))
  27 #define SG_MEMCONF_CH0_SZ_256M          ((0x0 << 10) | (0x03 << 0))
  28 #define SG_MEMCONF_CH0_SZ_512M          ((0x1 << 10) | (0x00 << 0))
  29 #define SG_MEMCONF_CH0_SZ_1G            ((0x1 << 10) | (0x01 << 0))
  30 #define SG_MEMCONF_CH0_NUM_MASK         (0x1 << 8)
  31 #define SG_MEMCONF_CH0_NUM_1            (0x1 << 8)
  32 #define SG_MEMCONF_CH0_NUM_2            (0x0 << 8)
  33
  34 #define SG_MEMCONF_CH1_SZ_MASK          ((0x1 << 11) | (0x03 << 2))
  35 #define SG_MEMCONF_CH1_SZ_64M           ((0x0 << 11) | (0x01 << 2))
  36 #define SG_MEMCONF_CH1_SZ_128M          ((0x0 << 11) | (0x02 << 2))
  37 #define SG_MEMCONF_CH1_SZ_256M          ((0x0 << 11) | (0x03 << 2))
  38 #define SG_MEMCONF_CH1_SZ_512M          ((0x1 << 11) | (0x00 << 2))
  39 #define SG_MEMCONF_CH1_SZ_1G            ((0x1 << 11) | (0x01 << 2))
  40 #define SG_MEMCONF_CH1_NUM_MASK         (0x1 << 9)
  41 #define SG_MEMCONF_CH1_NUM_1            (0x1 << 9)
  42 #define SG_MEMCONF_CH1_NUM_2            (0x0 << 9)
  43
  44 #define SG_MEMCONF_CH2_SZ_MASK          ((0x1 << 26) | (0x03 << 16))
  45 #define SG_MEMCONF_CH2_SZ_64M           ((0x0 << 26) | (0x01 << 16))
  46 #define SG_MEMCONF_CH2_SZ_128M          ((0x0 << 26) | (0x02 << 16))
  47 #define SG_MEMCONF_CH2_SZ_256M          ((0x0 << 26) | (0x03 << 16))
  48 #define SG_MEMCONF_CH2_SZ_512M          ((0x1 << 26) | (0x00 << 16))
  49 #define SG_MEMCONF_CH2_SZ_1G            ((0x1 << 26) | (0x01 << 16))
  50 #define SG_MEMCONF_CH2_NUM_MASK         (0x1 << 24)
  51 #define SG_MEMCONF_CH2_NUM_1            (0x1 << 24)
  52 #define SG_MEMCONF_CH2_NUM_2            (0x0 << 24)
  53 /* PH1-LD6b, ProXstream2, PH1-LD20 only */
  54 #define SG_MEMCONF_CH2_DISABLE          (0x1 << 21)
  55
  56 #define SG_MEMCONF_SPARSEMEM            (0x1 << 4)
  57
  58 #define SG_ETPHYPSHUT                   (SG_CTRL_BASE | 0x554)
  59 #define SG_ETPHYCNT                     (SG_CTRL_BASE | 0x550)
  60
  61 /* Pin Control */
  62 #define SG_PINCTRL_BASE                 (SG_CTRL_BASE | 0x1000)
  63
  64 /* PH1-Pro4, PH1-Pro5 */
  65 #define SG_LOADPINCTRL                  (SG_CTRL_BASE | 0x1700)
  66
  67 /* Input Enable */
  68 #define SG_IECTRL                       (SG_CTRL_BASE | 0x1d00)
  69
  70 /* Pin Monitor */
  71 #define SG_PINMON0                      (SG_DBG_BASE | 0x0100)
  72
  73 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK        (0x3 << 19)
  74 #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT     (0x0 << 19)
  75 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A     (0x2 << 19)
  76 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B     (0x3 << 19)
  77
  78 #define SG_PINMON0_CLK_MODE_AXOSEL_MASK         (0x3 << 16)
  79 #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ     (0x0 << 16)
  80 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ     (0x1 << 16)
  81 #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ      (0x2 << 16)
  82 #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ      (0x3 << 16)
  83
  84 #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT      (0x0 << 16)
  85 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U   (0x1 << 16)
  86 #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ     (0x2 << 16)
  87 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A   (0x3 << 16)
  88
  89 #ifdef __ASSEMBLY__
  90
  91         .macro  sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
  92         ldr     \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
  93         ldr     \rd, [\ra]
  94         and     \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
  95         orr     \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
  96         str     \rd, [\ra]
  97         .endm
  98
  99 #else
 100
 101 #include <linux/types.h>
 102 #include <linux/io.h>
 103
 104 static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
 105                                  unsigned mux_bits, unsigned reg_stride)
 106 {
 107         unsigned shift = pin * mux_bits % 32;
 108         unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
 109         u32 mask = (1U << mux_bits) - 1;
 110         u32 tmp;
 111
 112         tmp = readl(reg);
 113         tmp &= ~(mask << shift);
 114         tmp |= (mask & muxval) << shift;
 115         writel(tmp, reg);
 116 }
 117
 118 static inline void sg_set_iectrl(unsigned pin)
 119 {
 120         unsigned bit = pin % 32;
 121         unsigned long reg = SG_IECTRL + pin / 32 * 4;
 122         u32 tmp;
 123
 124         tmp = readl(reg);
 125         tmp |= 1 << bit;
 126         writel(tmp, reg);
 127 }
 128
 129 static inline void sg_set_iectrl_range(unsigned min, unsigned max)
 130 {
 131         int i;
 132
 133         for (i = min; i <= max; i++)
 134                 sg_set_iectrl(i);
 135 }
 136
 137 #endif /* __ASSEMBLY__ */
 138
 139 #endif /* UNIPHIER_SG_REGS_H */