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mediatek: update driver for MT7988 built-in 2.5G Ethernet PHY
[openwrt/staging/dangole.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7988a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 /* TOPRGU resets */
17 #define MT7988_TOPRGU_SGMII0_GRST 1
18 #define MT7988_TOPRGU_SGMII1_GRST 2
19 #define MT7988_TOPRGU_XFI0_GRST 12
20 #define MT7988_TOPRGU_XFI1_GRST 13
21 #define MT7988_TOPRGU_XFI_PEXTP0_GRST 14
22 #define MT7988_TOPRGU_XFI_PEXTP1_GRST 15
23 #define MT7988_TOPRGU_XFI_PLL_GRST 16
24
25 / {
26 compatible = "mediatek,mt7988";
27 interrupt-parent = <&gic>;
28 #address-cells = <2>;
29 #size-cells = <2>;
30
31 cci: cci {
32 compatible = "mediatek,mt7988-cci",
33 "mediatek,mt8183-cci";
34 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
35 <&topckgen CLK_TOP_XTAL>;
36 clock-names = "cci", "intermediate";
37 operating-points-v2 = <&cci_opp>;
38 };
39
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 cpu0: cpu@0 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a73";
46 enable-method = "psci";
47 reg = <0x0>;
48 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
49 <&topckgen CLK_TOP_XTAL>;
50 clock-names = "cpu", "intermediate";
51 operating-points-v2 = <&cluster0_opp>;
52 mediatek,cci = <&cci>;
53 };
54
55 cpu1: cpu@1 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a73";
58 enable-method = "psci";
59 reg = <0x1>;
60 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
61 <&topckgen CLK_TOP_XTAL>;
62 clock-names = "cpu", "intermediate";
63 operating-points-v2 = <&cluster0_opp>;
64 mediatek,cci = <&cci>;
65 };
66
67 cpu2: cpu@2 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a73";
70 enable-method = "psci";
71 reg = <0x2>;
72 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
73 <&topckgen CLK_TOP_XTAL>;
74 clock-names = "cpu", "intermediate";
75 operating-points-v2 = <&cluster0_opp>;
76 mediatek,cci = <&cci>;
77 };
78
79 cpu3: cpu@3 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a73";
82 enable-method = "psci";
83 reg = <0x3>;
84 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
85 <&topckgen CLK_TOP_XTAL>;
86 clock-names = "cpu", "intermediate";
87 operating-points-v2 = <&cluster0_opp>;
88 mediatek,cci = <&cci>;
89 };
90
91 cluster0_opp: opp_table0 {
92 compatible = "operating-points-v2";
93 opp-shared;
94 opp00 {
95 opp-hz = /bits/ 64 <800000000>;
96 opp-microvolt = <850000>;
97 };
98 opp01 {
99 opp-hz = /bits/ 64 <1100000000>;
100 opp-microvolt = <850000>;
101 };
102 opp02 {
103 opp-hz = /bits/ 64 <1500000000>;
104 opp-microvolt = <850000>;
105 };
106 opp03 {
107 opp-hz = /bits/ 64 <1800000000>;
108 opp-microvolt = <900000>;
109 };
110 };
111 };
112
113 cci_opp: opp_table_cci {
114 compatible = "operating-points-v2";
115 opp-shared;
116 opp00 {
117 opp-hz = /bits/ 64 <480000000>;
118 opp-microvolt = <850000>;
119 };
120 opp01 {
121 opp-hz = /bits/ 64 <660000000>;
122 opp-microvolt = <850000>;
123 };
124 opp02 {
125 opp-hz = /bits/ 64 <900000000>;
126 opp-microvolt = <850000>;
127 };
128 opp03 {
129 opp-hz = /bits/ 64 <1080000000>;
130 opp-microvolt = <900000>;
131 };
132 };
133
134 clk40m: oscillator@0 {
135 compatible = "fixed-clock";
136 clock-frequency = <40000000>;
137 #clock-cells = <0>;
138 clock-output-names = "clkxtal";
139 };
140
141 fan: pwm-fan {
142 compatible = "pwm-fan";
143 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
144 cooling-levels = <0 128 255>;
145 #cooling-cells = <2>;
146 #thermal-sensor-cells = <1>;
147 status = "disabled";
148 };
149
150 pmu {
151 compatible = "arm,cortex-a73-pmu";
152 interrupt-parent = <&gic>;
153 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
154 };
155
156 psci {
157 compatible = "arm,psci-0.2";
158 method = "smc";
159 };
160
161 reg_1p8v: regulator-1p8v {
162 compatible = "regulator-fixed";
163 regulator-name = "fixed-1.8V";
164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <1800000>;
166 regulator-boot-on;
167 regulator-always-on;
168 };
169
170 reg_3p3v: regulator-3p3v {
171 compatible = "regulator-fixed";
172 regulator-name = "fixed-3.3V";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
175 regulator-boot-on;
176 regulator-always-on;
177 };
178
179 reserved-memory {
180 #address-cells = <2>;
181 #size-cells = <2>;
182 ranges;
183
184 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
185 secmon_reserved: secmon@43000000 {
186 reg = <0 0x43000000 0 0x50000>;
187 no-map;
188 };
189 };
190
191 soc {
192 #address-cells = <2>;
193 #size-cells = <2>;
194 compatible = "simple-bus";
195 ranges;
196
197 gic: interrupt-controller@c000000 {
198 compatible = "arm,gic-v3";
199 #interrupt-cells = <3>;
200 interrupt-parent = <&gic>;
201 interrupt-controller;
202 reg = <0 0x0c000000 0 0x40000>, /* GICD */
203 <0 0x0c080000 0 0x200000>, /* GICR */
204 <0 0x0c400000 0 0x2000>, /* GICC */
205 <0 0x0c410000 0 0x1000>, /* GICH */
206 <0 0x0c420000 0 0x2000>; /* GICV */
207
208 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
209 };
210
211 phyfw: phy-firmware@f000000 {
212 compatible = "mediatek,2p5gphy-fw";
213 reg = <0 0x0f100000 0 0x20000>,
214 <0 0x0f0f0018 0 0x20>;
215 };
216
217 infracfg: infracfg@10001000 {
218 compatible = "mediatek,mt7988-infracfg", "syscon";
219 reg = <0 0x10001000 0 0x1000>;
220 #clock-cells = <1>;
221 #reset-cells = <1>;
222 };
223
224 topckgen: topckgen@1001b000 {
225 compatible = "mediatek,mt7988-topckgen", "syscon";
226 reg = <0 0x1001b000 0 0x1000>;
227 #clock-cells = <1>;
228 };
229
230 watchdog: watchdog@1001c000 {
231 compatible = "mediatek,mt7988-wdt",
232 "mediatek,mt6589-wdt",
233 "syscon";
234 reg = <0 0x1001c000 0 0x1000>;
235 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
236 #reset-cells = <1>;
237 };
238
239 apmixedsys: apmixedsys@1001e000 {
240 compatible = "mediatek,mt7988-apmixedsys";
241 reg = <0 0x1001e000 0 0x1000>;
242 #clock-cells = <1>;
243 };
244
245 pio: pinctrl@1001f000 {
246 compatible = "mediatek,mt7988-pinctrl", "syscon";
247 reg = <0 0x1001f000 0 0x1000>,
248 <0 0x11c10000 0 0x1000>,
249 <0 0x11d00000 0 0x1000>,
250 <0 0x11d20000 0 0x1000>,
251 <0 0x11e00000 0 0x1000>,
252 <0 0x11f00000 0 0x1000>,
253 <0 0x1000b000 0 0x1000>;
254 reg-names = "gpio_base", "iocfg_tr_base",
255 "iocfg_br_base", "iocfg_rb_base",
256 "iocfg_lb_base", "iocfg_tl_base", "eint";
257 gpio-controller;
258 #gpio-cells = <2>;
259 gpio-ranges = <&pio 0 0 84>;
260 interrupt-controller;
261 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
262 interrupt-parent = <&gic>;
263 #interrupt-cells = <2>;
264
265 mdio0_pins: mdio0-pins {
266 mux {
267 function = "eth";
268 groups = "mdc_mdio0";
269 };
270
271 conf {
272 groups = "mdc_mdio0";
273 drive-strength = <MTK_DRIVE_8mA>;
274 };
275 };
276
277 i2c0_pins: i2c0-pins-g0 {
278 mux {
279 function = "i2c";
280 groups = "i2c0_1";
281 };
282 };
283
284 i2c1_pins: i2c1-pins-g0 {
285 mux {
286 function = "i2c";
287 groups = "i2c1_0";
288 };
289 };
290
291 i2c1_sfp_pins: i2c1-sfp-pins-g0 {
292 mux {
293 function = "i2c";
294 groups = "i2c1_sfp";
295 };
296 };
297
298 i2c2_pins: i2c2-pins {
299 mux {
300 function = "i2c";
301 groups = "i2c2";
302 };
303 };
304
305 i2c2_0_pins: i2c2-pins-g0 {
306 mux {
307 function = "i2c";
308 groups = "i2c2_0";
309 };
310 };
311
312 i2c2_1_pins: i2c2-pins-g1 {
313 mux {
314 function = "i2c";
315 groups = "i2c2_1";
316 };
317 };
318
319 gbe0_led0_pins: gbe0-led0-pins {
320 mux {
321 function = "led";
322 groups = "gbe0_led0";
323 };
324 };
325
326 gbe1_led0_pins: gbe1-led0-pins {
327 mux {
328 function = "led";
329 groups = "gbe1_led0";
330 };
331 };
332
333 gbe2_led0_pins: gbe2-led0-pins {
334 mux {
335 function = "led";
336 groups = "gbe2_led0";
337 };
338 };
339
340 gbe3_led0_pins: gbe3-led0-pins {
341 mux {
342 function = "led";
343 groups = "gbe3_led0";
344 };
345 };
346
347 gbe0_led1_pins: gbe0-led1-pins {
348 mux {
349 function = "led";
350 groups = "gbe0_led1";
351 };
352 };
353
354 gbe1_led1_pins: gbe1-led1-pins {
355 mux {
356 function = "led";
357 groups = "gbe1_led1";
358 };
359 };
360
361 gbe2_led1_pins: gbe2-led1-pins {
362 mux {
363 function = "led";
364 groups = "gbe2_led1";
365 };
366 };
367
368 gbe3_led1_pins: gbe3-led1-pins {
369 mux {
370 function = "led";
371 groups = "gbe3_led1";
372 };
373 };
374
375 i2p5gbe_led0_pins: 2p5gbe-led0-pins {
376 mux {
377 function = "led";
378 groups = "2p5gbe_led0";
379 };
380 };
381
382 i2p5gbe_led1_pins: 2p5gbe-led1-pins {
383 mux {
384 function = "led";
385 groups = "2p5gbe_led1";
386 };
387 };
388
389 mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
390 mux {
391 function = "flash";
392 groups = "emmc_45";
393 };
394 };
395
396 mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
397 mux {
398 function = "flash";
399 groups = "emmc_51";
400 };
401 };
402
403 mmc0_pins_sdcard: mmc0-pins-sdcard {
404 mux {
405 function = "flash";
406 groups = "sdcard";
407 };
408 };
409
410 uart0_pins: uart0-pins {
411 mux {
412 function = "uart";
413 groups = "uart0";
414 };
415 };
416
417 snfi_pins: snfi-pins {
418 mux {
419 function = "flash";
420 groups = "snfi";
421 };
422 };
423
424 spi0_pins: spi0-pins {
425 mux {
426 function = "spi";
427 groups = "spi0";
428 };
429 };
430
431 spi0_flash_pins: spi0-flash-pins {
432 mux {
433 function = "spi";
434 groups = "spi0", "spi0_wp_hold";
435 };
436 };
437
438 spi1_pins: spi1-pins {
439 mux {
440 function = "spi";
441 groups = "spi1";
442 };
443 };
444
445 spi2_pins: spi2-pins {
446 mux {
447 function = "spi";
448 groups = "spi2";
449 };
450 };
451
452 spi2_flash_pins: spi2-flash-pins {
453 mux {
454 function = "spi";
455 groups = "spi2", "spi2_wp_hold";
456 };
457 };
458
459 pcie0_pins: pcie0-pins {
460 mux {
461 function = "pcie";
462 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
463 "pcie_wake_n0_0";
464 };
465 };
466
467 pcie1_pins: pcie1-pins {
468 mux {
469 function = "pcie";
470 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
471 "pcie_wake_n1_0";
472 };
473 };
474
475 pcie2_pins: pcie2-pins {
476 mux {
477 function = "pcie";
478 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
479 "pcie_wake_n2_0";
480 };
481 };
482
483 pcie3_pins: pcie3-pins {
484 mux {
485 function = "pcie";
486 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
487 "pcie_wake_n3_0";
488 };
489 };
490 };
491
492 pwm: pwm@10048000 {
493 compatible = "mediatek,mt7988-pwm";
494 reg = <0 0x10048000 0 0x1000>;
495 #pwm-cells = <2>;
496 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
497 <&infracfg CLK_INFRA_66M_PWM_HCK>,
498 <&infracfg CLK_INFRA_66M_PWM_CK1>,
499 <&infracfg CLK_INFRA_66M_PWM_CK2>,
500 <&infracfg CLK_INFRA_66M_PWM_CK3>,
501 <&infracfg CLK_INFRA_66M_PWM_CK4>,
502 <&infracfg CLK_INFRA_66M_PWM_CK5>,
503 <&infracfg CLK_INFRA_66M_PWM_CK6>,
504 <&infracfg CLK_INFRA_66M_PWM_CK7>,
505 <&infracfg CLK_INFRA_66M_PWM_CK8>;
506 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
507 "pwm4","pwm5","pwm6","pwm7","pwm8";
508 status = "disabled";
509 };
510
511 sgmiisys0: syscon@10060000 {
512 compatible = "mediatek,mt7988-sgmiisys",
513 "mediatek,mt7988-sgmiisys0",
514 "syscon",
515 "simple-mfd";
516 reg = <0 0x10060000 0 0x1000>;
517 resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
518 #clock-cells = <1>;
519
520 sgmiipcs0: pcs {
521 compatible = "mediatek,mt7988-sgmii";
522 clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
523 <&sgmiisys0 CLK_SGM0_TX_EN>,
524 <&sgmiisys0 CLK_SGM0_RX_EN>;
525 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
526 };
527 };
528
529 sgmiisys1: syscon@10070000 {
530 compatible = "mediatek,mt7988-sgmiisys",
531 "mediatek,mt7988-sgmiisys1",
532 "syscon",
533 "simple-mfd";
534 reg = <0 0x10070000 0 0x1000>;
535 resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
536 #clock-cells = <1>;
537
538 sgmiipcs1: pcs {
539 compatible = "mediatek,mt7988-sgmii";
540 clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
541 <&sgmiisys1 CLK_SGM1_TX_EN>,
542 <&sgmiisys1 CLK_SGM1_RX_EN>;
543 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
544 };
545 };
546
547 usxgmiisys0: pcs@10080000 {
548 compatible = "mediatek,mt7988-usxgmiisys";
549 reg = <0 0x10080000 0 0x1000>;
550 resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
551 clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
552 };
553
554 usxgmiisys1: pcs@10081000 {
555 compatible = "mediatek,mt7988-usxgmiisys";
556 reg = <0 0x10081000 0 0x1000>;
557 resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
558 clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
559 };
560
561 mcusys: mcusys@100e0000 {
562 compatible = "mediatek,mt7988-mcusys", "syscon";
563 reg = <0 0x100e0000 0 0x1000>;
564 #clock-cells = <1>;
565 };
566
567 uart0: serial@11000000 {
568 compatible = "mediatek,mt7986-uart",
569 "mediatek,mt6577-uart";
570 reg = <0 0x11000000 0 0x100>;
571 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
572 /*
573 * 8250-mtk driver don't control "baud" clock since commit
574 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
575 * still need to be passed to the driver to prevent probe fail
576 */
577 clocks = <&topckgen CLK_TOP_UART_SEL>,
578 <&infracfg CLK_INFRA_52M_UART0_CK>;
579 clock-names = "baud", "bus";
580 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
581 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
582 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
583 <&topckgen CLK_TOP_UART_SEL>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&uart0_pins>;
586 status = "disabled";
587 };
588
589 snand: spi@11001000 {
590 compatible = "mediatek,mt7986-snand";
591 reg = <0 0x11001000 0 0x1000>;
592 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&infracfg CLK_INFRA_SPINFI>,
594 <&infracfg CLK_INFRA_NFI>;
595 clock-names = "pad_clk", "nfi_clk";
596 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
597 <&topckgen CLK_TOP_NFI1X_SEL>;
598 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
599 <&topckgen CLK_TOP_MPLL_D8>;
600 nand-ecc-engine = <&bch>;
601 mediatek,quad-spi;
602 #address-cells = <1>;
603 #size-cells = <0>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&snfi_pins>;
606 status = "disabled";
607 };
608
609 bch: ecc@11002000 {
610 compatible = "mediatek,mt7686-ecc";
611 reg = <0 0x11002000 0 0x1000>;
612 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
614 clock-names = "nfiecc_clk";
615 status = "disabled";
616 };
617
618 i2c0: i2c@11003000 {
619 compatible = "mediatek,mt7988-i2c",
620 "mediatek,mt7981-i2c";
621 reg = <0 0x11003000 0 0x1000>,
622 <0 0x10217080 0 0x80>;
623 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
624 clock-div = <1>;
625 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
626 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
627 clock-names = "main", "dma";
628 #address-cells = <1>;
629 #size-cells = <0>;
630 status = "disabled";
631 };
632
633 i2c1: i2c@11004000 {
634 compatible = "mediatek,mt7988-i2c",
635 "mediatek,mt7981-i2c";
636 reg = <0 0x11004000 0 0x1000>,
637 <0 0x10217100 0 0x80>;
638 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
639 clock-div = <1>;
640 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
641 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
642 clock-names = "main", "dma";
643 #address-cells = <1>;
644 #size-cells = <0>;
645 status = "disabled";
646 };
647
648 i2c2: i2c@11005000 {
649 compatible = "mediatek,mt7988-i2c",
650 "mediatek,mt7981-i2c";
651 reg = <0 0x11005000 0 0x1000>,
652 <0 0x10217180 0 0x80>;
653 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
654 clock-div = <1>;
655 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
656 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
657 clock-names = "main", "dma";
658 #address-cells = <1>;
659 #size-cells = <0>;
660 status = "disabled";
661 };
662
663 spi0: spi@11007000 {
664 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
665 reg = <0 0x11007000 0 0x100>;
666 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&topckgen CLK_TOP_MPLL_D2>,
668 <&topckgen CLK_TOP_SPI_SEL>,
669 <&infracfg CLK_INFRA_104M_SPI0>,
670 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
671 clock-names = "parent-clk", "sel-clk", "spi-clk",
672 "spi-hclk";
673 #address-cells = <1>;
674 #size-cells = <0>;
675 status = "disabled";
676 };
677
678 spi1: spi@11008000 {
679 compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
680 reg = <0 0x11008000 0 0x100>;
681 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&topckgen CLK_TOP_MPLL_D2>,
683 <&topckgen CLK_TOP_SPI_SEL>,
684 <&infracfg CLK_INFRA_104M_SPI1>,
685 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
686 clock-names = "parent-clk", "sel-clk", "spi-clk",
687 "spi-hclk";
688 #address-cells = <1>;
689 #size-cells = <0>;
690 pinctrl-names = "default";
691 pinctrl-0 = <&spi1_pins>;
692 status = "disabled";
693 };
694
695 spi2: spi@11009000 {
696 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
697 reg = <0 0x11009000 0 0x100>;
698 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&topckgen CLK_TOP_MPLL_D2>,
700 <&topckgen CLK_TOP_SPI_SEL>,
701 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
702 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
703 clock-names = "parent-clk", "sel-clk", "spi-clk",
704 "spi-hclk";
705 #address-cells = <1>;
706 #size-cells = <0>;
707 status = "disabled";
708 };
709
710 lvts: lvts@1100a000 {
711 compatible = "mediatek,mt7988-lvts-ap";
712 #thermal-sensor-cells = <1>;
713 reg = <0 0x1100a000 0 0x1000>;
714 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
715 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
716 resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
717 nvmem-cells = <&lvts_calibration>;
718 nvmem-cell-names = "lvts-calib-data-1";
719 };
720
721 ssusb0: usb@11190000 {
722 compatible = "mediatek,mt7988-xhci",
723 "mediatek,mtk-xhci";
724 reg = <0 0x11190000 0 0x2e00>,
725 <0 0x11193e00 0 0x0100>;
726 reg-names = "mac", "ippc";
727 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
728 phys = <&xphyu2port0 PHY_TYPE_USB2>,
729 <&xphyu3port0 PHY_TYPE_USB3>;
730 clocks = <&infracfg CLK_INFRA_USB_SYS>,
731 <&infracfg CLK_INFRA_USB_XHCI>,
732 <&infracfg CLK_INFRA_USB_REF>,
733 <&infracfg CLK_INFRA_66M_USB_HCK>,
734 <&infracfg CLK_INFRA_133M_USB_HCK>;
735 clock-names = "sys_ck",
736 "xhci_ck",
737 "ref_ck",
738 "mcu_ck",
739 "dma_ck";
740 #address-cells = <2>;
741 #size-cells = <2>;
742 mediatek,p0_speed_fixup;
743 status = "disabled";
744 };
745
746 ssusb1: usb@11200000 {
747 compatible = "mediatek,mt7988-xhci",
748 "mediatek,mtk-xhci";
749 reg = <0 0x11200000 0 0x2e00>,
750 <0 0x11203e00 0 0x0100>;
751 reg-names = "mac", "ippc";
752 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
753 phys = <&tphyu2port0 PHY_TYPE_USB2>,
754 <&tphyu3port0 PHY_TYPE_USB3>;
755 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
756 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
757 <&infracfg CLK_INFRA_USB_CK_P1>,
758 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
759 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
760 clock-names = "sys_ck",
761 "xhci_ck",
762 "ref_ck",
763 "mcu_ck",
764 "dma_ck";
765 #address-cells = <2>;
766 #size-cells = <2>;
767 status = "disabled";
768 };
769
770 afe: audio-controller@11210000 {
771 compatible = "mediatek,mt79xx-audio";
772 reg = <0 0x11210000 0 0x9000>;
773 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
775 <&infracfg CLK_INFRA_AUD_26M>,
776 <&infracfg CLK_INFRA_AUD_L>,
777 <&infracfg CLK_INFRA_AUD_AUD>,
778 <&infracfg CLK_INFRA_AUD_EG2>,
779 <&topckgen CLK_TOP_AUD_SEL>,
780 <&topckgen CLK_TOP_AUD_I2S_M>;
781 clock-names = "aud_bus_ck",
782 "aud_26m_ck",
783 "aud_l_ck",
784 "aud_aud_ck",
785 "aud_eg2_ck",
786 "aud_sel",
787 "aud_i2s_m";
788 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
789 <&topckgen CLK_TOP_A1SYS_SEL>,
790 <&topckgen CLK_TOP_AUD_L_SEL>,
791 <&topckgen CLK_TOP_A_TUNER_SEL>;
792 assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
793 <&topckgen CLK_TOP_APLL2_D4>,
794 <&apmixedsys CLK_APMIXED_APLL2>,
795 <&topckgen CLK_TOP_APLL2_D4>;
796 status = "disabled";
797 };
798
799 mmc0: mmc@11230000 {
800 compatible = "mediatek,mt7986-mmc",
801 "mediatek,mt7981-mmc";
802 reg = <0 0x11230000 0 0x1000>,
803 <0 0x11D60000 0 0x1000>;
804 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&infracfg CLK_INFRA_MSDC400>,
806 <&infracfg CLK_INFRA_MSDC2_HCK>,
807 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
808 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
809 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
810 <&topckgen CLK_TOP_EMMC_400M_SEL>;
811 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
812 <&apmixedsys CLK_APMIXED_MSDCPLL>;
813 clock-names = "source",
814 "hclk",
815 "axi_cg",
816 "ahb_cg";
817 #address-cells = <1>;
818 #size-cells = <0>;
819 status = "disabled";
820 };
821
822 pcie2: pcie@11280000 {
823 compatible = "mediatek,mt7988-pcie",
824 "mediatek,mt7986-pcie",
825 "mediatek,mt8192-pcie";
826 device_type = "pci";
827 #address-cells = <3>;
828 #size-cells = <2>;
829 reg = <0 0x11280000 0 0x2000>;
830 reg-names = "pcie-mac";
831 linux,pci-domain = <3>;
832 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
833 bus-range = <0x00 0xff>;
834 ranges = <0x81000000 0x00 0x20000000 0x00
835 0x20000000 0x00 0x00200000>,
836 <0x82000000 0x00 0x20200000 0x00
837 0x20200000 0x00 0x07e00000>;
838 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
839 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
840 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
841 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
842 clock-names = "pl_250m", "tl_26m", "peri_26m",
843 "top_133m";
844 pinctrl-names = "default";
845 pinctrl-0 = <&pcie2_pins>;
846 status = "disabled";
847
848 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
849 phy-names = "pcie-phy";
850
851 #interrupt-cells = <1>;
852 interrupt-map-mask = <0 0 0 0x7>;
853 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
854 <0 0 0 2 &pcie_intc2 1>,
855 <0 0 0 3 &pcie_intc2 2>,
856 <0 0 0 4 &pcie_intc2 3>;
857 pcie_intc2: interrupt-controller {
858 #address-cells = <0>;
859 #interrupt-cells = <1>;
860 interrupt-controller;
861 };
862 };
863
864 pcie3: pcie@11290000 {
865 compatible = "mediatek,mt7988-pcie",
866 "mediatek,mt7986-pcie",
867 "mediatek,mt8192-pcie";
868 device_type = "pci";
869 #address-cells = <3>;
870 #size-cells = <2>;
871 reg = <0 0x11290000 0 0x2000>;
872 reg-names = "pcie-mac";
873 linux,pci-domain = <2>;
874 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
875 bus-range = <0x00 0xff>;
876 ranges = <0x81000000 0x00 0x28000000 0x00
877 0x28000000 0x00 0x00200000>,
878 <0x82000000 0x00 0x28200000 0x00
879 0x28200000 0x00 0x07e00000>;
880 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
881 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
882 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
883 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
884 clock-names = "pl_250m", "tl_26m", "peri_26m",
885 "top_133m";
886 pinctrl-names = "default";
887 pinctrl-0 = <&pcie3_pins>;
888 status = "disabled";
889
890 #interrupt-cells = <1>;
891 interrupt-map-mask = <0 0 0 0x7>;
892 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
893 <0 0 0 2 &pcie_intc3 1>,
894 <0 0 0 3 &pcie_intc3 2>,
895 <0 0 0 4 &pcie_intc3 3>;
896 pcie_intc3: interrupt-controller {
897 #address-cells = <0>;
898 #interrupt-cells = <1>;
899 interrupt-controller;
900 };
901 };
902
903 pcie0: pcie@11300000 {
904 compatible = "mediatek,mt7988-pcie",
905 "mediatek,mt7986-pcie",
906 "mediatek,mt8192-pcie";
907 device_type = "pci";
908 #address-cells = <3>;
909 #size-cells = <2>;
910 reg = <0 0x11300000 0 0x2000>;
911 reg-names = "pcie-mac";
912 linux,pci-domain = <0>;
913 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
914 bus-range = <0x00 0xff>;
915 ranges = <0x81000000 0x00 0x30000000 0x00
916 0x30000000 0x00 0x00200000>,
917 <0x82000000 0x00 0x30200000 0x00
918 0x30200000 0x00 0x07e00000>;
919 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
920 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
921 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
922 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
923 clock-names = "pl_250m", "tl_26m", "peri_26m",
924 "top_133m";
925 pinctrl-names = "default";
926 pinctrl-0 = <&pcie0_pins>;
927 status = "disabled";
928
929 #interrupt-cells = <1>;
930 interrupt-map-mask = <0 0 0 0x7>;
931 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
932 <0 0 0 2 &pcie_intc0 1>,
933 <0 0 0 3 &pcie_intc0 2>,
934 <0 0 0 4 &pcie_intc0 3>;
935 pcie_intc0: interrupt-controller {
936 #address-cells = <0>;
937 #interrupt-cells = <1>;
938 interrupt-controller;
939 };
940 };
941
942 pcie1: pcie@11310000 {
943 compatible = "mediatek,mt7988-pcie",
944 "mediatek,mt7986-pcie",
945 "mediatek,mt8192-pcie";
946 device_type = "pci";
947 #address-cells = <3>;
948 #size-cells = <2>;
949 reg = <0 0x11310000 0 0x2000>;
950 reg-names = "pcie-mac";
951 linux,pci-domain = <1>;
952 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
953 bus-range = <0x00 0xff>;
954 ranges = <0x81000000 0x00 0x38000000 0x00
955 0x38000000 0x00 0x00200000>,
956 <0x82000000 0x00 0x38200000 0x00
957 0x38200000 0x00 0x07e00000>;
958 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
959 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
960 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
961 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
962 clock-names = "pl_250m", "tl_26m", "peri_26m",
963 "top_133m";
964 pinctrl-names = "default";
965 pinctrl-0 = <&pcie1_pins>;
966 status = "disabled";
967
968 #interrupt-cells = <1>;
969 interrupt-map-mask = <0 0 0 0x7>;
970 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
971 <0 0 0 2 &pcie_intc1 1>,
972 <0 0 0 3 &pcie_intc1 2>,
973 <0 0 0 4 &pcie_intc1 3>;
974 pcie_intc1: interrupt-controller {
975 #address-cells = <0>;
976 #interrupt-cells = <1>;
977 interrupt-controller;
978 };
979 };
980
981 tphy: tphy@11c50000 {
982 compatible = "mediatek,mt7988",
983 "mediatek,generic-tphy-v2";
984 #address-cells = <2>;
985 #size-cells = <2>;
986 ranges;
987 status = "disabled";
988 tphyu2port0: usb-phy@11c50000 {
989 reg = <0 0x11c50000 0 0x700>;
990 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
991 clock-names = "ref";
992 #phy-cells = <1>;
993 };
994 tphyu3port0: usb-phy@11c50700 {
995 reg = <0 0x11c50700 0 0x900>;
996 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
997 clock-names = "ref";
998 #phy-cells = <1>;
999 mediatek,usb3-pll-ssc-delta;
1000 mediatek,usb3-pll-ssc-delta1;
1001 };
1002 };
1003
1004 topmisc: topmisc@11d10000 {
1005 compatible = "mediatek,mt7988-topmisc", "syscon",
1006 "mediatek,mt7988-power-controller";
1007 reg = <0 0x11d10000 0 0x10000>;
1008 #clock-cells = <1>;
1009 #power-domain-cells = <1>;
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1012 };
1013
1014 xphy: xphy@11e10000 {
1015 compatible = "mediatek,mt7988",
1016 "mediatek,xsphy";
1017 #address-cells = <2>;
1018 #size-cells = <2>;
1019 ranges;
1020 status = "disabled";
1021
1022 xphyu2port0: usb-phy@11e10000 {
1023 reg = <0 0x11e10000 0 0x400>;
1024 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
1025 clock-names = "ref";
1026 #phy-cells = <1>;
1027 };
1028
1029 xphyu3port0: usb-phy@11e13000 {
1030 reg = <0 0x11e13400 0 0x500>;
1031 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1032 clock-names = "ref";
1033 #phy-cells = <1>;
1034 mediatek,syscon-type = <&topmisc 0x218 0>;
1035 };
1036 };
1037
1038 xfi_tphy0: phy@11f20000 {
1039 compatible = "mediatek,mt7988-xfi-tphy";
1040 reg = <0 0x11f20000 0 0x10000>;
1041 resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
1042 clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
1043 clock-names = "xfipll", "topxtal";
1044 mediatek,usxgmii-performance-errata;
1045 #phy-cells = <0>;
1046 };
1047
1048 xfi_tphy1: phy@11f30000 {
1049 compatible = "mediatek,mt7988-xfi-tphy";
1050 reg = <0 0x11f30000 0 0x10000>;
1051 resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
1052 clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
1053 clock-names = "xfipll", "topxtal";
1054 #phy-cells = <0>;
1055 };
1056
1057 xfi_pll: clock-controller@11f40000 {
1058 compatible = "mediatek,mt7988-xfi-pll";
1059 reg = <0 0x11f40000 0 0x1000>;
1060 resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
1061 #clock-cells = <1>;
1062 };
1063
1064 efuse: efuse@11f50000 {
1065 compatible = "mediatek,efuse";
1066 reg = <0 0x11f50000 0 0x1000>;
1067 #address-cells = <1>;
1068 #size-cells = <1>;
1069
1070 lvts_calibration: calib@918 {
1071 reg = <0x918 0x28>;
1072 };
1073 phy_calibration_p0: calib@940 {
1074 reg = <0x940 0x10>;
1075 };
1076 phy_calibration_p1: calib@954 {
1077 reg = <0x954 0x10>;
1078 };
1079 phy_calibration_p2: calib@968 {
1080 reg = <0x968 0x10>;
1081 };
1082 phy_calibration_p3: calib@97c {
1083 reg = <0x97c 0x10>;
1084 };
1085 cpufreq_calibration: calib@278 {
1086 reg = <0x278 0x1>;
1087 };
1088 };
1089
1090 ethsys: syscon@15000000 {
1091 #address-cells = <1>;
1092 #size-cells = <1>;
1093 compatible = "mediatek,mt7988-ethsys", "syscon";
1094 reg = <0 0x15000000 0 0x1000>;
1095 #clock-cells = <1>;
1096 #reset-cells = <1>;
1097 };
1098
1099 switch: switch@15020000 {
1100 #address-cells = <1>;
1101 #size-cells = <1>;
1102 compatible = "mediatek,mt7988-switch";
1103 reg = <0 0x15020000 0 0x8000>;
1104 interrupt-controller;
1105 #interrupt-cells = <1>;
1106 interrupt-parent = <&gic>;
1107 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1108 resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
1109
1110 ports {
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1113
1114 gsw_port0: port@0 {
1115 reg = <0>;
1116 label = "lan0";
1117 phy-mode = "internal";
1118 phy-handle = <&gsw_phy0>;
1119 };
1120
1121 gsw_port1: port@1 {
1122 reg = <1>;
1123 label = "lan1";
1124 phy-mode = "internal";
1125 phy-handle = <&gsw_phy1>;
1126 };
1127
1128 gsw_port2: port@2 {
1129 reg = <2>;
1130 label = "lan2";
1131 phy-mode = "internal";
1132 phy-handle = <&gsw_phy2>;
1133 };
1134
1135 gsw_port3: port@3 {
1136 reg = <3>;
1137 label = "lan3";
1138 phy-mode = "internal";
1139 phy-handle = <&gsw_phy3>;
1140 };
1141
1142 port@6 {
1143 reg = <6>;
1144 ethernet = <&gmac0>;
1145 phy-mode = "internal";
1146
1147 fixed-link {
1148 speed = <10000>;
1149 full-duplex;
1150 pause;
1151 };
1152 };
1153 };
1154
1155 mdio {
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1158 mediatek,pio = <&pio>;
1159
1160 gsw_phy0: ethernet-phy@0 {
1161 compatible = "ethernet-phy-ieee802.3-c22";
1162 reg = <0>;
1163 phy-mode = "internal";
1164 nvmem-cells = <&phy_calibration_p0>;
1165 nvmem-cell-names = "phy-cal-data";
1166
1167 leds {
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1170
1171 gsw_phy0_led0: gsw-phy0-led0@0 {
1172 reg = <0>;
1173 function = LED_FUNCTION_LAN;
1174 status = "disabled";
1175 };
1176
1177 gsw_phy0_led1: gsw-phy0-led1@1 {
1178 reg = <1>;
1179 function = LED_FUNCTION_LAN;
1180 status = "disabled";
1181 };
1182 };
1183 };
1184
1185 gsw_phy1: ethernet-phy@1 {
1186 compatible = "ethernet-phy-ieee802.3-c22";
1187 reg = <1>;
1188 phy-mode = "internal";
1189 nvmem-cells = <&phy_calibration_p1>;
1190 nvmem-cell-names = "phy-cal-data";
1191
1192 leds {
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1195
1196 gsw_phy1_led0: gsw-phy1-led0@0 {
1197 reg = <0>;
1198 function = LED_FUNCTION_LAN;
1199 status = "disabled";
1200 };
1201
1202 gsw_phy1_led1: gsw-phy1-led1@1 {
1203 reg = <1>;
1204 function = LED_FUNCTION_LAN;
1205 status = "disabled";
1206 };
1207 };
1208 };
1209
1210 gsw_phy2: ethernet-phy@2 {
1211 compatible = "ethernet-phy-ieee802.3-c22";
1212 reg = <2>;
1213 phy-mode = "internal";
1214 nvmem-cells = <&phy_calibration_p2>;
1215 nvmem-cell-names = "phy-cal-data";
1216
1217 leds {
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1220
1221 gsw_phy2_led0: gsw-phy2-led0@0 {
1222 reg = <0>;
1223 function = LED_FUNCTION_LAN;
1224 status = "disabled";
1225 };
1226
1227 gsw_phy2_led1: gsw-phy2-led1@1 {
1228 reg = <1>;
1229 function = LED_FUNCTION_LAN;
1230 status = "disabled";
1231 };
1232 };
1233 };
1234
1235 gsw_phy3: ethernet-phy@3 {
1236 compatible = "ethernet-phy-ieee802.3-c22";
1237 reg = <3>;
1238 phy-mode = "internal";
1239 nvmem-cells = <&phy_calibration_p3>;
1240 nvmem-cell-names = "phy-cal-data";
1241
1242 leds {
1243 #address-cells = <1>;
1244 #size-cells = <0>;
1245
1246 gsw_phy3_led0: gsw-phy3-led0@0 {
1247 reg = <0>;
1248 function = LED_FUNCTION_LAN;
1249 status = "disabled";
1250 };
1251
1252 gsw_phy3_led1: gsw-phy3-led1@1 {
1253 reg = <1>;
1254 function = LED_FUNCTION_LAN;
1255 status = "disabled";
1256 };
1257 };
1258 };
1259 };
1260 };
1261
1262 ethwarp: clock-controller@15031000 {
1263 compatible = "mediatek,mt7988-ethwarp";
1264 reg = <0 0x15031000 0 0x1000>;
1265 #clock-cells = <1>;
1266 #reset-cells = <1>;
1267 };
1268
1269 eth: ethernet@15100000 {
1270 compatible = "mediatek,mt7988-eth";
1271 reg = <0 0x15100000 0 0x80000>,
1272 <0 0x15400000 0 0x380000>;
1273 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
1278 <&ethsys CLK_ETHDMA_XGP2_EN>,
1279 <&ethsys CLK_ETHDMA_XGP3_EN>,
1280 <&ethsys CLK_ETHDMA_FE_EN>,
1281 <&ethsys CLK_ETHDMA_GP2_EN>,
1282 <&ethsys CLK_ETHDMA_GP1_EN>,
1283 <&ethsys CLK_ETHDMA_GP3_EN>,
1284 <&ethsys CLK_ETHDMA_ESW_EN>,
1285 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
1286 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
1287 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
1288 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
1289 <&topckgen CLK_TOP_ETH_GMII_SEL>,
1290 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1291 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1292 <&topckgen CLK_TOP_ETH_SYS_SEL>,
1293 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1294 <&topckgen CLK_TOP_ETH_MII_SEL>,
1295 <&topckgen CLK_TOP_NETSYS_SEL>,
1296 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1297 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1298 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1299 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1300 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1301 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1302 "gp3", "esw", "crypto",
1303 "ethwarp_wocpu2", "ethwarp_wocpu1",
1304 "ethwarp_wocpu0", "top_eth_gmii_sel",
1305 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1306 "top_eth_sys_sel", "top_eth_xgmii_sel",
1307 "top_eth_mii_sel", "top_netsys_sel",
1308 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1309 "top_netsys_sync_250m_sel",
1310 "top_netsys_ppefb_250m_sel",
1311 "top_netsys_warp_sel";
1312 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1313 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1314 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1315 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1316 <&topckgen CLK_TOP_SGM_0_SEL>,
1317 <&topckgen CLK_TOP_SGM_1_SEL>;
1318 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1319 <&topckgen CLK_TOP_NET1PLL_D4>,
1320 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1321 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1322 <&apmixedsys CLK_APMIXED_SGMPLL>,
1323 <&apmixedsys CLK_APMIXED_SGMPLL>;
1324 mediatek,ethsys = <&ethsys>;
1325 mediatek,infracfg = <&topmisc>;
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1328
1329 gmac0: mac@0 {
1330 compatible = "mediatek,eth-mac";
1331 reg = <0>;
1332 phy-mode = "internal";
1333 status = "disabled";
1334
1335 fixed-link {
1336 speed = <10000>;
1337 full-duplex;
1338 pause;
1339 };
1340 };
1341
1342 gmac1: mac@1 {
1343 compatible = "mediatek,eth-mac";
1344 reg = <1>;
1345 status = "disabled";
1346 pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
1347 phys = <&xfi_tphy1>;
1348 };
1349
1350 gmac2: mac@2 {
1351 compatible = "mediatek,eth-mac";
1352 reg = <2>;
1353 status = "disabled";
1354 pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
1355 phys = <&xfi_tphy0>;
1356 };
1357
1358 mdio_bus: mdio-bus {
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1361
1362 /* internal 2.5G PHY */
1363 int_2p5g_phy: ethernet-phy@15 {
1364 reg = <15>;
1365 compatible = "ethernet-phy-ieee802.3-c45";
1366 phy-mode = "internal";
1367 };
1368 };
1369 };
1370
1371 crypto: crypto@15600000 {
1372 compatible = "inside-secure,safexcel-eip197b";
1373 reg = <0 0x15600000 0 0x180000>;
1374 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1378 interrupt-names = "ring0", "ring1", "ring2", "ring3";
1379 status = "okay";
1380 };
1381 };
1382
1383 thermal-zones {
1384 cpu_thermal: cpu-thermal {
1385 polling-delay-passive = <1000>;
1386 polling-delay = <1000>;
1387 thermal-sensors = <&lvts 0>;
1388 trips {
1389 cpu_trip_crit: crit {
1390 temperature = <125000>;
1391 hysteresis = <2000>;
1392 type = "critical";
1393 };
1394
1395 cpu_trip_hot: hot {
1396 temperature = <120000>;
1397 hysteresis = <2000>;
1398 type = "hot";
1399 };
1400
1401 cpu_trip_active_high: active-high {
1402 temperature = <115000>;
1403 hysteresis = <2000>;
1404 type = "active";
1405 };
1406
1407 cpu_trip_active_med: active-med {
1408 temperature = <85000>;
1409 hysteresis = <2000>;
1410 type = "active";
1411 };
1412
1413 cpu_trip_active_low: active-low {
1414 temperature = <40000>;
1415 hysteresis = <2000>;
1416 type = "active";
1417 };
1418 };
1419
1420 cooling-maps {
1421 cpu-active-high {
1422 /* active: set fan to cooling level 2 */
1423 cooling-device = <&fan 3 3>;
1424 trip = <&cpu_trip_active_high>;
1425 };
1426
1427 cpu-active-low {
1428 /* active: set fan to cooling level 1 */
1429 cooling-device = <&fan 2 2>;
1430 trip = <&cpu_trip_active_med>;
1431 };
1432
1433 cpu-passive {
1434 /* passive: set fan to cooling level 0 */
1435 cooling-device = <&fan 1 1>;
1436 trip = <&cpu_trip_active_low>;
1437 };
1438 };
1439 };
1440 };
1441
1442 timer {
1443 compatible = "arm,armv8-timer";
1444 interrupt-parent = <&gic>;
1445 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1446 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1447 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1448 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1449 };
1450 };
Staging tree of Daniel Golle