target/linux/ixp4xx/patches-6.6/0004-ARM-dts-usr8200-Fix-phy-registers.patch

   1 From 98f3b5f44b9ae86c4a80185b57149867472a2570 Mon Sep 17 00:00:00 2001
   2 From: Linus Walleij <linus.walleij@linaro.org>
   3 Date: Fri, 20 Oct 2023 15:11:41 +0200
   4 Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
   5
   6 The MV88E6060 switch has internal PHY registers at MDIO
   7 addresses 0x00..0x04. Tie each port to the corresponding
   8 PHY.
   9
  10 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  11 Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
  12 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
  13 ---
  14  .../ixp/intel-ixp42x-usrobotics-usr8200.dts   | 22 +++++++++++++++++++
  15  1 file changed, 22 insertions(+)
  16
  17 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
  18 +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
  19 @@ -165,6 +165,24 @@
  20                                 #address-cells = <1>;
  21                                 #size-cells = <0>;
  22
  23 +                               /*
  24 +                                * PHY 0..4 are internal to the MV88E6060 switch but appear
  25 +                                * as independent devices.
  26 +                                */
  27 +                               phy0: ethernet-phy@0 {
  28 +                                       reg = <0>;
  29 +                               };
  30 +                               phy1: ethernet-phy@1 {
  31 +                                       reg = <1>;
  32 +                               };
  33 +                               phy2: ethernet-phy@2 {
  34 +                                       reg = <2>;
  35 +                               };
  36 +                               phy3: ethernet-phy@3 {
  37 +                                       reg = <3>;
  38 +                               };
  39 +
  40 +                               /* Altima AMI101L used by the WAN port */
  41                                 phy9: ethernet-phy@9 {
  42                                         reg = <9>;
  43                                 };
  44 @@ -181,21 +199,25 @@
  45                                                 port@0 {
  46                                                         reg = <0>;
  47                                                         label = "lan1";
  48 +                                                       phy-handle = <&phy0>;
  49                                                 };
  50
  51                                                 port@1 {
  52                                                         reg = <1>;
  53                                                         label = "lan2";
  54 +                                                       phy-handle = <&phy1>;
  55                                                 };
  56
  57                                                 port@2 {
  58                                                         reg = <2>;
  59                                                         label = "lan3";
  60 +                                                       phy-handle = <&phy2>;
  61                                                 };
  62
  63                                                 port@3 {
  64                                                         reg = <3>;
  65                                                         label = "lan4";
  66 +                                                       phy-handle = <&phy3>;
  67                                                 };
  68
  69                                                 port@5 {