target/linux/ixp4xx/patches-6.1/0002-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch

   1 From fc58944733a2082e3290eda240eb3247a00ad73a Mon Sep 17 00:00:00 2001
   2 From: Linus Walleij <linus.walleij@linaro.org>
   3 Date: Thu, 21 Sep 2023 00:12:42 +0200
   4 Subject: [PATCH] gpio: ixp4xx: Handle clock output on pin 14 and 15
   5
   6 This makes it possible to provide basic clock output on pins
   7 14 and 15. The clocks are typically used by random electronics,
   8 not modeled in the device tree, so they just need to be provided
   9 on request.
  10
  11 In order to not disturb old systems that require that the
  12 hardware defaults are kept in the clock setting bits, we only
  13 manipulate these if either device tree property is present.
  14 Once we know a device needs one of the clocks we can set it
  15 in the device tree.
  16
  17 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  18 ---
  19  drivers/gpio/gpio-ixp4xx.c | 49 +++++++++++++++++++++++++++++++++++++-
  20  1 file changed, 48 insertions(+), 1 deletion(-)
  21
  22 --- a/drivers/gpio/gpio-ixp4xx.c
  23 +++ b/drivers/gpio/gpio-ixp4xx.c
  24 @@ -38,6 +38,18 @@
  25  #define IXP4XX_GPIO_STYLE_MASK         GENMASK(2, 0)
  26  #define IXP4XX_GPIO_STYLE_SIZE         3
  27
  28 +/*
  29 + * Clock output control register defines.
  30 + */
  31 +#define IXP4XX_GPCLK_CLK0DC_SHIFT      0
  32 +#define IXP4XX_GPCLK_CLK0TC_SHIFT      4
  33 +#define IXP4XX_GPCLK_CLK0_MASK         GENMASK(7, 0)
  34 +#define IXP4XX_GPCLK_MUX14             BIT(8)
  35 +#define IXP4XX_GPCLK_CLK1DC_SHIFT      16
  36 +#define IXP4XX_GPCLK_CLK1TC_SHIFT      20
  37 +#define IXP4XX_GPCLK_CLK1_MASK         GENMASK(23, 16)
  38 +#define IXP4XX_GPCLK_MUX15             BIT(24)
  39 +
  40  /**
  41   * struct ixp4xx_gpio - IXP4 GPIO state container
  42   * @dev: containing device for this instance
  43 @@ -203,6 +215,8 @@ static int ixp4xx_gpio_probe(struct plat
  44         struct ixp4xx_gpio *g;
  45         struct gpio_irq_chip *girq;
  46         struct device_node *irq_parent;
  47 +       bool clk_14, clk_15;
  48 +       u32 val;
  49         int ret;
  50
  51         g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
  52 @@ -233,7 +247,40 @@ static int ixp4xx_gpio_probe(struct plat
  53          */
  54         if (of_machine_is_compatible("dlink,dsm-g600-a") ||
  55             of_machine_is_compatible("iom,nas-100d"))
  56 -               __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
  57 +               val = 0;
  58 +       else
  59 +               val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
  60 +
  61 +       /*
  62 +        * If either clock output is enabled explicitly in the device tree
  63 +        * we take full control of the clock by masking off all bits for
  64 +        * the clock control and selectively enabling them. Otherwise
  65 +        * we leave the hardware default settings.
  66 +        *
  67 +        * Enable clock outputs with default timings of requested clock.
  68 +        * If you need control over TC and DC, add these to the device
  69 +        * tree bindings and use them here.
  70 +        */
  71 +       clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");
  72 +       clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");
  73 +       if (clk_14 || clk_15) {
  74 +               val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);
  75 +               val &= ~IXP4XX_GPCLK_CLK0_MASK;
  76 +               val &= ~IXP4XX_GPCLK_CLK1_MASK;
  77 +               if (clk_14) {
  78 +                       val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT);
  79 +                       val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);
  80 +                       val |= IXP4XX_GPCLK_MUX14;
  81 +               }
  82 +
  83 +               if (clk_15) {
  84 +                       val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT);
  85 +                       val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);
  86 +                       val |= IXP4XX_GPCLK_MUX15;
  87 +               }
  88 +       }
  89 +
  90 +       __raw_writel(val, g->base + IXP4XX_REG_GPCLK);
  91
  92         /*
  93          * This is a very special big-endian ARM issue: when the IXP4xx is