plat/rpi/rpi4/rpi4_bl31_setup.c

   1 /*
   2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8
   9 #include <libfdt.h>
  10
  11 #include <platform_def.h>
  12 #include <arch_helpers.h>
  13 #include <common/bl_common.h>
  14 #include <lib/mmio.h>
  15 #include <lib/xlat_tables/xlat_mmu_helpers.h>
  16 #include <lib/xlat_tables/xlat_tables_defs.h>
  17 #include <lib/xlat_tables/xlat_tables_v2.h>
  18 #include <plat/common/platform.h>
  19 #include <common/fdt_fixup.h>
  20 #include <libfdt.h>
  21
  22 #include <drivers/arm/gicv2.h>
  23
  24 #include <rpi_shared.h>
  25
  26 /*
  27  * Fields at the beginning of armstub8.bin.
  28  * While building the BL31 image, we put the stub magic into the binary.
  29  * The GPU firmware detects this at boot time, clears that field as a
  30  * confirmation and puts the kernel and DT address in the following words.
  31  */
  32 extern uint32_t stub_magic;
  33 extern uint32_t dtb_ptr32;
  34 extern uint32_t kernel_entry32;
  35
  36 static const gicv2_driver_data_t rpi4_gic_data = {
  37         .gicd_base = RPI4_GIC_GICD_BASE,
  38         .gicc_base = RPI4_GIC_GICC_BASE,
  39 };
  40
  41 /*
  42  * To be filled by the code below. At the moment BL32 is not supported.
  43  * In the future these might be passed down from BL2.
  44  */
  45 static entry_point_info_t bl32_image_ep_info;
  46 static entry_point_info_t bl33_image_ep_info;
  47
  48 /*******************************************************************************
  49  * Return a pointer to the 'entry_point_info' structure of the next image for
  50  * the security state specified. BL33 corresponds to the non-secure image type
  51  * while BL32 corresponds to the secure image type. A NULL pointer is returned
  52  * if the image does not exist.
  53  ******************************************************************************/
  54 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  55 {
  56         entry_point_info_t *next_image_info;
  57
  58         assert(sec_state_is_valid(type) != 0);
  59
  60         next_image_info = (type == NON_SECURE)
  61                         ? &bl33_image_ep_info : &bl32_image_ep_info;
  62
  63         /* None of the images can have 0x0 as the entrypoint. */
  64         if (next_image_info->pc) {
  65                 return next_image_info;
  66         } else {
  67                 return NULL;
  68         }
  69 }
  70
  71 uintptr_t plat_get_ns_image_entrypoint(void)
  72 {
  73 #ifdef PRELOADED_BL33_BASE
  74         return PRELOADED_BL33_BASE;
  75 #else
  76         /* Cleared by the GPU if kernel address is valid. */
  77         if (stub_magic == 0)
  78                 return kernel_entry32;
  79
  80         WARN("Stub magic failure, using default kernel address 0x80000\n");
  81         return 0x80000;
  82 #endif
  83 }
  84
  85 static uintptr_t rpi4_get_dtb_address(void)
  86 {
  87 #ifdef RPI3_PRELOADED_DTB_BASE
  88         return RPI3_PRELOADED_DTB_BASE;
  89 #else
  90         /* Cleared by the GPU if DTB address is valid. */
  91         if (stub_magic == 0)
  92                 return dtb_ptr32;
  93
  94         WARN("Stub magic failure, DTB address unknown\n");
  95         return 0;
  96 #endif
  97 }
  98
  99 static void ldelay(register_t delay)
 100 {
 101         __asm__ volatile (
 102                 "1:\tcbz %0, 2f\n\t"
 103                 "sub %0, %0, #1\n\t"
 104                 "b 1b\n"
 105                 "2:"
 106                 : "=&r" (delay) : "0" (delay)
 107         );
 108 }
 109
 110 /*******************************************************************************
 111  * Perform any BL31 early platform setup. Here is an opportunity to copy
 112  * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before
 113  * they are lost (potentially). This needs to be done before the MMU is
 114  * initialized so that the memory layout can be used while creating page
 115  * tables. BL2 has flushed this information to memory, so we are guaranteed
 116  * to pick up good data.
 117  ******************************************************************************/
 118 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 119                                 u_register_t arg2, u_register_t arg3)
 120
 121 {
 122         uint32_t div_reg;
 123
 124         /*
 125          * LOCAL_CONTROL:
 126          * Bit 9 clear: Increment by 1 (vs. 2).
 127          * Bit 8 clear: Timer source is 19.2MHz crystal (vs. APB).
 128          */
 129         mmio_write_32(RPI4_LOCAL_CONTROL_BASE_ADDRESS, 0);
 130
 131         /* LOCAL_PRESCALER; divide-by (0x80000000 / register_val) == 1 */
 132         mmio_write_32(RPI4_LOCAL_CONTROL_PRESCALER, 0x80000000);
 133
 134         /* Early GPU firmware revisions need a little break here. */
 135         ldelay(100000);
 136
 137         /*
 138          * Initialize the console to provide early debug support.
 139          * Different GPU firmware revisions set up the VPU divider differently,
 140          * so read the actual divider register to learn the UART base clock
 141          * rate. The divider is encoded as a 12.12 fixed point number, but we
 142          * just care about the integer part of it.
 143          */
 144         div_reg = mmio_read_32(RPI4_CLOCK_BASE + RPI4_VPU_CLOCK_DIVIDER);
 145         div_reg = (div_reg >> 12) & 0xfff;
 146         if (div_reg == 0)
 147                 div_reg = 1;
 148         rpi3_console_init(PLAT_RPI4_VPU_CLK_RATE / div_reg);
 149
 150         bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
 151         bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
 152         SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 153
 154 #if RPI3_DIRECT_LINUX_BOOT
 155 # if RPI3_BL33_IN_AARCH32
 156         /*
 157          * According to the file ``Documentation/arm/Booting`` of the Linux
 158          * kernel tree, Linux expects:
 159          * r0 = 0
 160          * r1 = machine type number, optional in DT-only platforms (~0 if so)
 161          * r2 = Physical address of the device tree blob
 162          */
 163         VERBOSE("rpi4: Preparing to boot 32-bit Linux kernel\n");
 164         bl33_image_ep_info.args.arg0 = 0U;
 165         bl33_image_ep_info.args.arg1 = ~0U;
 166         bl33_image_ep_info.args.arg2 = rpi4_get_dtb_address();
 167 # else
 168         /*
 169          * According to the file ``Documentation/arm64/booting.txt`` of the
 170          * Linux kernel tree, Linux expects the physical address of the device
 171          * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
 172          * must be 0.
 173          */
 174         VERBOSE("rpi4: Preparing to boot 64-bit Linux kernel\n");
 175         bl33_image_ep_info.args.arg0 = rpi4_get_dtb_address();
 176         bl33_image_ep_info.args.arg1 = 0ULL;
 177         bl33_image_ep_info.args.arg2 = 0ULL;
 178         bl33_image_ep_info.args.arg3 = 0ULL;
 179 # endif /* RPI3_BL33_IN_AARCH32 */
 180 #endif /* RPI3_DIRECT_LINUX_BOOT */
 181 }
 182
 183 void bl31_plat_arch_setup(void)
 184 {
 185         /*
 186          * Is the dtb_ptr32 pointer valid? If yes, map the DTB region.
 187          * We map the 2MB region the DTB start address lives in, plus
 188          * the next 2MB, to have enough room for expansion.
 189          */
 190         if (stub_magic == 0) {
 191                 unsigned long long dtb_region = dtb_ptr32;
 192
 193                 dtb_region &= ~0x1fffff;        /* Align to 2 MB. */
 194                 mmap_add_region(dtb_region, dtb_region, 4U << 20,
 195                                 MT_MEMORY | MT_RW | MT_NS);
 196         }
 197         /*
 198          * Add the first page of memory, which holds the stub magic,
 199          * the kernel and the DT address.
 200          * This is read-only, as the GPU already populated the header,
 201          * we just need to read it.
 202          */
 203         mmap_add_region(0, 0, 4096, MT_MEMORY | MT_RO | MT_SECURE);
 204
 205         rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE,
 206                                BL_CODE_BASE, BL_CODE_END,
 207                                BL_RO_DATA_BASE, BL_RO_DATA_END
 208 #if USE_COHERENT_MEM
 209                                , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
 210 #endif
 211                               );
 212
 213         enable_mmu_el3(0);
 214 }
 215
 216 static uint32_t dtb_size(const void *dtb)
 217 {
 218         const uint32_t *dtb_header = dtb;
 219
 220         return fdt32_to_cpu(dtb_header[1]);
 221 }
 222
 223 static void rpi4_prepare_dtb(void)
 224 {
 225         void *dtb = (void *)rpi4_get_dtb_address();
 226         int ret;
 227
 228         /* Return if no device tree is detected */
 229         if (fdt_check_header(dtb) != 0)
 230                 return;
 231
 232         ret = fdt_open_into(dtb, dtb, 0x100000);
 233         if (ret < 0) {
 234                 ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret);
 235                 return;
 236         }
 237
 238         if (dt_add_psci_node(dtb)) {
 239                 ERROR("Failed to add PSCI Device Tree node\n");
 240                 return;
 241         }
 242
 243         if (dt_add_psci_cpu_enable_methods(dtb)) {
 244                 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
 245                 return;
 246         }
 247
 248         ret = fdt_pack(dtb);
 249         if (ret < 0)
 250                 ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret);
 251
 252         clean_dcache_range((uintptr_t)dtb, dtb_size(dtb));
 253         INFO("Changed device tree to advertise PSCI.\n");
 254 }
 255
 256 void bl31_platform_setup(void)
 257 {
 258         rpi4_prepare_dtb();
 259
 260         /* Configure the interrupt controller */
 261         gicv2_driver_init(&rpi4_gic_data);
 262         gicv2_distif_init();
 263         gicv2_pcpu_distif_init();
 264         gicv2_cpuif_enable();
 265 }