package/kernel/mac80211/patches/rt2x00/998-wifi-rt2x00-rework-MT7620-PA-LNA-RF-calibration.patch

   1 From: Shiji Yang <yangshiji66@outlook.com>
   2 Date: Tue, 25 Jul 2023 20:05:06 +0800
   3 Subject: [PATCH] wifi: rt2x00: rework MT7620 PA/LNA RF calibration
   4
   5 1. Move MT7620 PA/LNA calibration code to dedicated functions.
   6    Calibration stage 1 is executed before configuring channels and
   7    stage 2 is executed after configuring channels.
   8 2. For external PA/LNA devices, restore RF and BBP registers before
   9    R-Calibration.
  10 3. Do Rx DCOC calibration again before RXIQ calibration.
  11 4. Correct MAC_SYS_CTRL register RX mask to 0x08 in R-Calibration
  12    function. For MAC_SYS_CTRL register, Bit[2] controls MAC_TX_EN
  13    and Bit[3] controls MAC_RX_EN (Bit index starts from 0).
  14 5. Move the channel configuration code from rt2800_vco_calibration()
  15    to the rt2800_config_channel().
  16 6. Use MT7620 SOC specific AGC initial LNA value instead of the
  17    RT5592's value.
  18 7. Adjust the register operation sequence according to the vendor
  19    driver code. This may not be useful, but it can make things
  20    clearer when developers try to review it.
  21
  22 Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
  23 ---
  24  .../net/wireless/ralink/rt2x00/rt2800lib.c    | 318 +++++++++++-------
  25  drivers/net/wireless/ralink/rt2x00/rt2x00.h   |   6 +
  26  2 files changed, 194 insertions(+), 130 deletions(-)
  27
  28 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  29 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  30 @@ -62,6 +62,9 @@ MODULE_PARM_DESC(watchdog, "Enable watch
  31         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  32                             H2M_MAILBOX_CSR_OWNER, (__reg))
  33
  34 +static void rt6352_init_palna_stage1(struct rt2x00_dev *rt2x00dev);
  35 +static void rt6352_init_palna_stage2(struct rt2x00_dev *rt2x00dev);
  36 +
  37  static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  38  {
  39         /* check for rt2872 on SoC */
  40 @@ -3881,14 +3884,6 @@ static void rt2800_config_channel_rf7620
  41                 rfcsr |= tx_agc_fc;
  42                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
  43         }
  44 -
  45 -       if (conf_is_ht40(conf)) {
  46 -               rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10);
  47 -               rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f);
  48 -       } else {
  49 -               rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a);
  50 -               rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40);
  51 -       }
  52  }
  53
  54  static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev,
  55 @@ -4151,6 +4146,9 @@ static void rt2800_config_channel(struct
  56                         rt2800_txpower_to_dev(rt2x00dev, rf->channel,
  57                                               info->default_power3);
  58
  59 +       if (rt2x00_rt(rt2x00dev, RT6352))
  60 +               rt6352_init_palna_stage1(rt2x00dev);
  61 +
  62         switch (rt2x00dev->chip.rt) {
  63         case RT3883:
  64                 rt3883_bbp_adjust(rt2x00dev, rf);
  65 @@ -4457,89 +4455,65 @@ static void rt2800_config_channel(struct
  66                 usleep_range(1000, 1500);
  67         }
  68
  69 -       if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
  70 +       if (rt2x00_rt(rt2x00dev, RT5592)) {
  71                 reg = 0x10;
  72 -               if (!conf_is_ht40(conf)) {
  73 -                       if (rt2x00_rt(rt2x00dev, RT6352) &&
  74 -                           rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
  75 -                               reg |= 0x5;
  76 -                       } else {
  77 -                               reg |= 0xa;
  78 -                       }
  79 -               }
  80 +               if (!conf_is_ht40(conf))
  81 +                       reg |= 0xa;
  82                 rt2800_bbp_write(rt2x00dev, 195, 141);
  83                 rt2800_bbp_write(rt2x00dev, 196, reg);
  84
  85 -               /* AGC init.
  86 -                * Despite the vendor driver using different values here for
  87 -                * RT6352 chip, we use 0x1c for now. This may have to be changed
  88 -                * once TSSI got implemented.
  89 -                */
  90                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
  91                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
  92 -
  93 -               if (rt2x00_rt(rt2x00dev, RT5592))
  94 -                       rt2800_iq_calibrate(rt2x00dev, rf->channel);
  95 +
  96 +               rt2800_iq_calibrate(rt2x00dev, rf->channel);
  97         }
  98
  99         if (rt2x00_rt(rt2x00dev, RT6352)) {
 100 -               if (test_bit(CAPABILITY_EXTERNAL_PA_TX0,
 101 -                            &rt2x00dev->cap_flags)) {
 102 -                       reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
 103 -                       reg |= 0x00000101;
 104 -                       rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
 105 -
 106 -                       reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
 107 -                       reg |= 0x00000101;
 108 -                       rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
 109 -
 110 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
 111 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
 112 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
 113 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
 114 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
 115 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
 116 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
 117 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
 118 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
 119 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
 120 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
 121 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
 122 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
 123 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
 124 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
 125 -                       rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
 126 +               /* BBP for GLRT BW */
 127 +               if (conf_is_ht40(conf)) {
 128 +                       rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10);
 129 +                       rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f);
 130 +               } else {
 131 +                       rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a);
 132 +                       rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40);
 133
 134 -                       rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
 135 -                                             0x36303636);
 136 -                       rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
 137 -                                             0x6C6C6B6C);
 138 -                       rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
 139 -                                             0x6C6C6B6C);
 140 +                       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 141 +                               rt2x00_has_cap_external_lna_bg(rt2x00dev))
 142 +                               rt2800_bbp_glrt_write(rt2x00dev, 141, 0x15);
 143                 }
 144
 145 -               if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 146 -                       reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
 147 -                       reg |= 0x00000101;
 148 -                       rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
 149 -
 150 -                       reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
 151 -                       reg |= 0x00000101;
 152 -                       rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
 153 -
 154 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
 155 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
 156 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42);
 157 -                       rt2800_bbp_write(rt2x00dev, 75, 0x68);
 158 -                       rt2800_bbp_write(rt2x00dev, 76, 0x4C);
 159 -                       rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 160 -                       rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 161 -                       rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 162 -                       /* bank 0 RF reg 42 and glrt BBP reg 141 will be set in
 163 -                        * config channel function in dependence of channel and
 164 -                        * HT20/HT40 so don't touch it
 165 -                        */
 166 +               if (rt2x00dev->default_ant.rx_chain_num == 1) {
 167 +                       rt2800_bbp_write(rt2x00dev, 91, 0x07);
 168 +                       rt2800_bbp_write(rt2x00dev, 95, 0x1A);
 169 +                       rt2800_bbp_write(rt2x00dev, 195, 128);
 170 +                       rt2800_bbp_write(rt2x00dev, 196, 0xA0);
 171 +                       rt2800_bbp_write(rt2x00dev, 195, 170);
 172 +                       rt2800_bbp_write(rt2x00dev, 196, 0x12);
 173 +                       rt2800_bbp_write(rt2x00dev, 195, 171);
 174 +                       rt2800_bbp_write(rt2x00dev, 196, 0x10);
 175 +               } else {
 176 +                       rt2800_bbp_write(rt2x00dev, 91, 0x06);
 177 +                       rt2800_bbp_write(rt2x00dev, 95, 0x9A);
 178 +                       rt2800_bbp_write(rt2x00dev, 195, 128);
 179 +                       rt2800_bbp_write(rt2x00dev, 196, 0xE0);
 180 +                       rt2800_bbp_write(rt2x00dev, 195, 170);
 181 +                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
 182 +                       rt2800_bbp_write(rt2x00dev, 195, 171);
 183 +                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
 184                 }
 185 +
 186 +               /* AGC init */
 187 +               reg = rf->channel <= 14 ? 0x04 + 2 * rt2x00dev->lna_gain : 0;
 188 +               rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
 189 +
 190 +               /* On 11A, We should delay and wait RF/BBP to be stable
 191 +                * and the appropriate time should be 1000 micro seconds
 192 +                * 2005/06/05 - On 11G, we also need this delay time.
 193 +                * Otherwise it's difficult to pass the WHQL.
 194 +                */
 195 +               usleep_range(1000, 1500);
 196 +
 197 +               rt6352_init_palna_stage2(rt2x00dev);
 198         }
 199
 200         bbp = rt2800_bbp_read(rt2x00dev, 4);
 201 @@ -5649,43 +5623,6 @@ void rt2800_vco_calibration(struct rt2x0
 202                 }
 203         }
 204         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 205 -
 206 -       if (rt2x00_rt(rt2x00dev, RT6352)) {
 207 -               if (rt2x00dev->default_ant.rx_chain_num == 1) {
 208 -                       rt2800_bbp_write(rt2x00dev, 91, 0x07);
 209 -                       rt2800_bbp_write(rt2x00dev, 95, 0x1A);
 210 -                       rt2800_bbp_write(rt2x00dev, 195, 128);
 211 -                       rt2800_bbp_write(rt2x00dev, 196, 0xA0);
 212 -                       rt2800_bbp_write(rt2x00dev, 195, 170);
 213 -                       rt2800_bbp_write(rt2x00dev, 196, 0x12);
 214 -                       rt2800_bbp_write(rt2x00dev, 195, 171);
 215 -                       rt2800_bbp_write(rt2x00dev, 196, 0x10);
 216 -               } else {
 217 -                       rt2800_bbp_write(rt2x00dev, 91, 0x06);
 218 -                       rt2800_bbp_write(rt2x00dev, 95, 0x9A);
 219 -                       rt2800_bbp_write(rt2x00dev, 195, 128);
 220 -                       rt2800_bbp_write(rt2x00dev, 196, 0xE0);
 221 -                       rt2800_bbp_write(rt2x00dev, 195, 170);
 222 -                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
 223 -                       rt2800_bbp_write(rt2x00dev, 195, 171);
 224 -                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
 225 -               }
 226 -
 227 -               if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 228 -                       rt2800_bbp_write(rt2x00dev, 75, 0x68);
 229 -                       rt2800_bbp_write(rt2x00dev, 76, 0x4C);
 230 -                       rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 231 -                       rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 232 -                       rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 233 -               }
 234 -
 235 -               /* On 11A, We should delay and wait RF/BBP to be stable
 236 -                * and the appropriate time should be 1000 micro seconds
 237 -                * 2005/06/05 - On 11G, we also need this delay time.
 238 -                * Otherwise it's difficult to pass the WHQL.
 239 -                */
 240 -               usleep_range(1000, 1500);
 241 -       }
 242  }
 243  EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
 244
 245 @@ -8650,7 +8587,7 @@ static void rt2800_r_calibration(struct
 246                 rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
 247
 248         maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 249 -       maccfg &= (~0x04);
 250 +       maccfg &= (~0x08);
 251         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
 252
 253         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
 254 @@ -10688,30 +10625,151 @@ static void rt2800_init_rfcsr_6352(struc
 255                 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
 256                 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
 257         }
 258 +}
 259
 260 -       rt6352_enable_pa_pin(rt2x00dev, 0);
 261 -       rt2800_r_calibration(rt2x00dev);
 262 -       rt2800_rf_self_txdc_cal(rt2x00dev);
 263 -       rt2800_rxdcoc_calibration(rt2x00dev);
 264 -       rt2800_bw_filter_calibration(rt2x00dev, true);
 265 -       rt2800_bw_filter_calibration(rt2x00dev, false);
 266 -       rt2800_loft_iq_calibration(rt2x00dev);
 267 -       rt2800_rxiq_calibration(rt2x00dev);
 268 -       rt6352_enable_pa_pin(rt2x00dev, 1);
 269 +static void rt6352_init_ext_palna(struct rt2x00_dev *rt2x00dev)
 270 +{
 271 +       u32 reg;
 272 +
 273 +       if (rt2x00_has_cap_external_pa(rt2x00dev)) {
 274 +               reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
 275 +               reg |= 0x00000101;
 276 +               rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
 277 +
 278 +               reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
 279 +               reg |= 0x00000101;
 280 +               rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
 281 +       }
 282
 283 -       if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 284 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 285 +               rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 286                 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
 287                 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
 288                 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42);
 289 +       }
 290 +
 291 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 292 +               rt2x00_has_cap_external_pa(rt2x00dev)) {
 293 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
 294 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
 295 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
 296 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
 297 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
 298 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
 299 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
 300 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
 301 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
 302 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
 303 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
 304 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
 305 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
 306 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
 307 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
 308 +       }
 309 +
 310 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 311 +               rt2x00_has_cap_external_pa(rt2x00dev)) {
 312 +               rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
 313 +       }
 314 +
 315 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 316 +               rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 317                 rt2800_bbp_write(rt2x00dev, 75, 0x68);
 318                 rt2800_bbp_write(rt2x00dev, 76, 0x4C);
 319                 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 320                 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 321                 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 322 -               /* bank 0 RF reg 42 and glrt BBP reg 141 will be set in config
 323 -                * channel function in dependence of channel and HT20/HT40,
 324 -                * so don't touch them here.
 325 -                */
 326 +       }
 327 +
 328 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 329 +               rt2x00_has_cap_external_pa(rt2x00dev)) {
 330 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x36303636);
 331 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C6B6C);
 332 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C6B6C);
 333 +       }
 334 +}
 335 +
 336 +static void rt6352_restore_rf_bbp(struct rt2x00_dev *rt2x00dev)
 337 +{
 338 +       if (rt2x00_has_cap_external_pa(rt2x00dev)) {
 339 +               rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0);
 340 +               rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0);
 341 +       }
 342 +
 343 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 344 +               rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 345 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
 346 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
 347 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
 348 +       }
 349 +
 350 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 351 +               rt2x00_has_cap_external_pa(rt2x00dev))
 352 +       {
 353 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
 354 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
 355 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
 356 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
 357 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
 358 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
 359 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
 360 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
 361 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
 362 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
 363 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
 364 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
 365 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
 366 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
 367 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
 368 +       }
 369 +
 370 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 371 +               rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 372 +               rt2800_bbp_write(rt2x00dev, 75, 0x60);
 373 +               rt2800_bbp_write(rt2x00dev, 76, 0x44);
 374 +               rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 375 +               rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 376 +               rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 377 +       }
 378 +
 379 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1
 380 +               && rt2x00_has_cap_external_pa(rt2x00dev)) {
 381 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x3630363A);
 382 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
 383 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
 384 +       }
 385 +}
 386 +
 387 +/* MT7620 PA/LNA initialization before switching channels */
 388 +static void rt6352_init_palna_stage1(struct rt2x00_dev *rt2x00dev)
 389 +{
 390 +       if (rt2x00_has_cap_external_pa(rt2x00dev) ||
 391 +               rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 392 +               rt6352_enable_pa_pin(rt2x00dev, 0);
 393 +               rt6352_restore_rf_bbp(rt2x00dev);
 394 +       }
 395 +
 396 +       rt2800_r_calibration(rt2x00dev);
 397 +}
 398 +
 399 +/* MT7620 PA/LNA initialization after switching channels */
 400 +static void rt6352_init_palna_stage2(struct rt2x00_dev *rt2x00dev)
 401 +{
 402 +       rt2800_rf_self_txdc_cal(rt2x00dev);
 403 +       rt2800_rxdcoc_calibration(rt2x00dev);
 404 +       rt2800_bw_filter_calibration(rt2x00dev, true);
 405 +       rt2800_bw_filter_calibration(rt2x00dev, false);
 406 +       rt2800_loft_iq_calibration(rt2x00dev);
 407 +
 408 +       /* missing DPD Calibration for devices using internal PA */
 409 +
 410 +       rt2800_rxdcoc_calibration(rt2x00dev);
 411 +       rt2800_rxiq_calibration(rt2x00dev);
 412 +
 413 +       if(rt2x00_has_cap_external_pa(rt2x00dev) ||
 414 +               rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 415 +               rt6352_enable_pa_pin(rt2x00dev, 1);
 416 +               rt6352_init_ext_palna(rt2x00dev);
 417         }
 418  }
 419
 420 --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h
 421 +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
 422 @@ -1277,6 +1277,12 @@ rt2x00_has_cap_external_lna_bg(struct rt
 423  }
 424
 425  static inline bool
 426 +rt2x00_has_cap_external_pa(struct rt2x00_dev *rt2x00dev)
 427 +{
 428 +       return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_PA_TX0);
 429 +}
 430 +
 431 +static inline bool
 432  rt2x00_has_cap_double_antenna(struct rt2x00_dev *rt2x00dev)
 433  {
 434         return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_DOUBLE_ANTENNA);