x86: Intel MID platforms has no microcode update
authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Fri, 17 Feb 2017 13:49:00 +0000 (16:49 +0300)
committerBin Meng <bmeng.cn@gmail.com>
Tue, 21 Feb 2017 07:10:56 +0000 (15:10 +0800)
There is no microcode update available for SoCs used on Intel MID
platforms.

Use conditional to bypass it.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
arch/x86/cpu/mp_init.c

index 988073cc7953f188cf1ffc7758263df83934b437..cfd9bb447b8bcb7035fe2acc6f9efebe09d08242 100644 (file)
@@ -248,7 +248,8 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
        if (!stack)
                return -ENOMEM;
        params->stack_top = (u32)(stack + size);
-#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
+#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \
+       !defined(CONFIG_INTEL_MID)
        params->microcode_ptr = ucode_base;
        debug("Microcode at %x\n", params->microcode_ptr);
 #endif