baa1c434173b5e27ed478f416f67af4a3d928063
[openwrt/staging/dedeckeh.git] / target / linux / bmips / dts / bcm6368.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /dts-v1/;
4
5 #include <dt-bindings/clock/bcm6368-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h>
9 #include <dt-bindings/reset/bcm6368-reset.h>
10
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "brcm,bcm6368";
15
16 aliases {
17 nflash = &nflash;
18 pflash = &pflash;
19 pinctrl = &pinctrl;
20 serial0 = &uart0;
21 serial1 = &uart1;
22 spi0 = &lsspi;
23 };
24
25 chosen {
26 bootargs = "earlycon";
27 stdout-path = "serial0:115200n8";
28 };
29
30 clocks {
31 periph_osc: periph-osc {
32 compatible = "fixed-clock";
33
34 #clock-cells = <0>;
35
36 clock-frequency = <50000000>;
37 clock-output-names = "periph";
38 };
39 };
40
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
44 mips-hpt-frequency = <200000000>;
45
46 cpu@0 {
47 compatible = "brcm,bmips4350", "mips,mips4Kc";
48 device_type = "cpu";
49 reg = <0>;
50 };
51
52 cpu@1 {
53 compatible = "brcm,bmips4350", "mips,mips4Kc";
54 device_type = "cpu";
55 reg = <1>;
56 };
57 };
58
59 cpu_intc: interrupt-controller {
60 #address-cells = <0>;
61 compatible = "mti,cpu-interrupt-controller";
62
63 interrupt-controller;
64 #interrupt-cells = <1>;
65 };
66
67 memory@0 {
68 device_type = "memory";
69 reg = <0 0>;
70 };
71
72 ubus {
73 #address-cells = <1>;
74 #size-cells = <1>;
75
76 compatible = "simple-bus";
77 ranges;
78
79 periph_clk: clock-controller@10000004 {
80 compatible = "brcm,bcm6368-clocks";
81 reg = <0x10000004 0x4>;
82 #clock-cells = <1>;
83 };
84
85 pll_cntl: syscon@10000008 {
86 compatible = "syscon", "simple-mfd";
87 reg = <0x10000008 0x4>;
88 native-endian;
89
90 syscon-reboot {
91 compatible = "syscon-reboot";
92 offset = <0x0>;
93 mask = <0x1>;
94 };
95 };
96
97 periph_rst: reset-controller@10000010 {
98 compatible = "brcm,bcm6345-reset";
99 reg = <0x10000010 0x4>;
100 #reset-cells = <1>;
101 };
102
103 ext_intc0: interrupt-controller@10000018 {
104 #address-cells = <1>;
105 compatible = "brcm,bcm6345-ext-intc";
106 reg = <0x10000018 0x4>;
107
108 interrupt-controller;
109 #interrupt-cells = <2>;
110
111 interrupt-parent = <&periph_intc>;
112 interrupts = <BCM6368_IRQ_EXT0>,
113 <BCM6368_IRQ_EXT1>,
114 <BCM6368_IRQ_EXT2>,
115 <BCM6368_IRQ_EXT3>;
116 };
117
118 ext_intc1: interrupt-controller@1000001c {
119 #address-cells = <1>;
120 compatible = "brcm,bcm6345-ext-intc";
121 reg = <0x1000001c 0x4>;
122
123 interrupt-controller;
124 #interrupt-cells = <2>;
125
126 interrupt-parent = <&periph_intc>;
127 interrupts = <BCM6368_IRQ_EXT4>,
128 <BCM6368_IRQ_EXT5>;
129 };
130
131 periph_intc: interrupt-controller@10000020 {
132 #address-cells = <1>;
133 compatible = "brcm,bcm6345-l1-intc";
134 reg = <0x10000020 0x10>,
135 <0x10000030 0x10>;
136
137 interrupt-controller;
138 #interrupt-cells = <1>;
139
140 interrupt-parent = <&cpu_intc>;
141 interrupts = <2>, <3>;
142 };
143
144 wdt: watchdog@1000005c {
145 compatible = "brcm,bcm7038-wdt";
146 reg = <0x1000005c 0xc>;
147
148 clocks = <&periph_osc>;
149
150 timeout-sec = <30>;
151 };
152
153 gpio_cntl: syscon@10000080 {
154 #address-cells = <1>;
155 #size-cells = <1>;
156 compatible = "brcm,bcm6368-gpio-sysctl",
157 "syscon", "simple-mfd";
158 reg = <0x10000080 0x80>;
159 ranges = <0 0x10000080 0x80>;
160 native-endian;
161
162 gpio: gpio@0 {
163 compatible = "brcm,bcm6368-gpio";
164 reg-names = "dirout", "dat";
165 reg = <0x0 0x8>, <0x8 0x8>;
166
167 gpio-controller;
168 gpio-ranges = <&pinctrl 0 0 38>;
169 #gpio-cells = <2>;
170 };
171
172 pinctrl: pinctrl@18 {
173 compatible = "brcm,bcm6368-pinctrl";
174 reg = <0x18 0x4>, <0x38 0x4>;
175
176 pinctrl_analog_afe_0: analog_afe_0-pins {
177 function = "analog_afe_0";
178 pins = "gpio0";
179 };
180
181 pinctrl_analog_afe_1: analog_afe_1-pins {
182 function = "analog_afe_1";
183 pins = "gpio1";
184 };
185
186 pinctrl_sys_irq: sys_irq-pins {
187 function = "sys_irq";
188 pins = "gpio2";
189 };
190
191 pinctrl_serial_led: serial_led-pins {
192 pinctrl_serial_led_data: serial_led_data-pins {
193 function = "serial_led_data";
194 pins = "gpio3";
195 };
196
197 pinctrl_serial_led_clk: serial_led_clk-pins {
198 function = "serial_led_clk";
199 pins = "gpio4";
200 };
201 };
202
203 pinctrl_inet_led: inet_led-pins {
204 function = "inet_led";
205 pins = "gpio5";
206 };
207
208 pinctrl_ephy0_led: ephy0_led-pins {
209 function = "ephy0_led";
210 pins = "gpio6";
211 };
212
213 pinctrl_ephy1_led: ephy1_led-pins {
214 function = "ephy1_led";
215 pins = "gpio7";
216 };
217
218 pinctrl_ephy2_led: ephy2_led-pins {
219 function = "ephy2_led";
220 pins = "gpio8";
221 };
222
223 pinctrl_ephy3_led: ephy3_led-pins {
224 function = "ephy3_led";
225 pins = "gpio9";
226 };
227
228 pinctrl_robosw_led_data: robosw_led_data-pins {
229 function = "robosw_led_data";
230 pins = "gpio10";
231 };
232
233 pinctrl_robosw_led_clk: robosw_led_clk-pins {
234 function = "robosw_led_clk";
235 pins = "gpio11";
236 };
237
238 pinctrl_robosw_led0: robosw_led0-pins {
239 function = "robosw_led0";
240 pins = "gpio12";
241 };
242
243 pinctrl_robosw_led1: robosw_led1-pins {
244 function = "robosw_led1";
245 pins = "gpio13";
246 };
247
248 pinctrl_usb_device_led: usb_device_led-pins {
249 function = "usb_device_led";
250 pins = "gpio14";
251 };
252
253 pinctrl_pci: pci-pins {
254 pinctrl_pci_req1: pci_req1-pins {
255 function = "pci_req1";
256 pins = "gpio16";
257 };
258
259 pinctrl_pci_gnt1: pci_gnt1-pins {
260 function = "pci_gnt1";
261 pins = "gpio17";
262 };
263
264 pinctrl_pci_intb: pci_intb-pins {
265 function = "pci_intb";
266 pins = "gpio18";
267 };
268
269 pinctrl_pci_req0: pci_req0-pins {
270 function = "pci_req0";
271 pins = "gpio19";
272 };
273
274 pinctrl_pci_gnt0: pci_gnt0-pins {
275 function = "pci_gnt0";
276 pins = "gpio20";
277 };
278 };
279
280 pinctrl_pcmcia: pcmcia-pins {
281 pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
282 function = "pcmcia_cd1";
283 pins = "gpio22";
284 };
285
286 pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
287 function = "pcmcia_cd2";
288 pins = "gpio23";
289 };
290
291 pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
292 function = "pcmcia_vs1";
293 pins = "gpio24";
294 };
295
296 pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
297 function = "pcmcia_vs2";
298 pins = "gpio25";
299 };
300 };
301
302 pinctrl_ebi_cs2: ebi_cs2-pins {
303 function = "ebi_cs2";
304 pins = "gpio26";
305 };
306
307 pinctrl_ebi_cs3: ebi_cs3-pins {
308 function = "ebi_cs3";
309 pins = "gpio27";
310 };
311
312 pinctrl_spi_cs2: spi_cs2-pins {
313 function = "spi_cs2";
314 pins = "gpio28";
315 };
316
317 pinctrl_spi_cs3: spi_cs3-pins {
318 function = "spi_cs3";
319 pins = "gpio29";
320 };
321
322 pinctrl_spi_cs4: spi_cs4-pins {
323 function = "spi_cs4";
324 pins = "gpio30";
325 };
326
327 pinctrl_spi_cs5: spi_cs5-pins {
328 function = "spi_cs5";
329 pins = "gpio31";
330 };
331
332 pinctrl_uart1: uart1-pins {
333 function = "uart1";
334 group = "uart1_grp";
335 };
336 };
337 };
338
339 leds: led-controller@100000d0 {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 compatible = "brcm,bcm6358-leds";
343 reg = <0x100000d0 0x8>;
344
345 status = "disabled";
346 };
347
348 uart0: serial@10000100 {
349 compatible = "brcm,bcm6345-uart";
350 reg = <0x10000100 0x18>;
351
352 interrupt-parent = <&periph_intc>;
353 interrupts = <BCM6368_IRQ_UART0>;
354
355 clocks = <&periph_osc>;
356 clock-names = "periph";
357
358 status = "disabled";
359 };
360
361 uart1: serial@10000120 {
362 compatible = "brcm,bcm6345-uart";
363 reg = <0x10000120 0x18>;
364
365 interrupt-parent = <&periph_intc>;
366 interrupts = <BCM6368_IRQ_UART1>;
367
368 clocks = <&periph_osc>;
369 clock-names = "periph";
370
371 status = "disabled";
372 };
373
374 nflash: nand@10000200 {
375 #address-cells = <1>;
376 #size-cells = <0>;
377 compatible = "brcm,nand-bcm6368",
378 "brcm,brcmnand-v2.1",
379 "brcm,brcmnand";
380 reg = <0x10000200 0x180>,
381 <0x10000600 0x200>,
382 <0x10000070 0x10>;
383 reg-names = "nand",
384 "nand-cache",
385 "nand-int-base";
386
387 interrupt-parent = <&periph_intc>;
388 interrupts = <BCM6368_IRQ_NAND>;
389
390 clocks = <&periph_clk BCM6368_CLK_NAND>;
391 clock-names = "nand";
392
393 status = "disabled";
394 };
395
396 lsspi: spi@10000800 {
397 #address-cells = <1>;
398 #size-cells = <0>;
399 compatible = "brcm,bcm6358-spi";
400 reg = <0x10000800 0x70c>;
401
402 interrupt-parent = <&periph_intc>;
403 interrupts = <BCM6368_IRQ_SPI>;
404
405 clocks = <&periph_clk BCM6368_CLK_SPI>;
406 clock-names = "spi";
407
408 resets = <&periph_rst BCM6368_RST_SPI>;
409
410 status = "disabled";
411 };
412
413 pci: pci@10001000 {
414 compatible = "brcm,bcm6348-pci";
415 reg = <0x10001000 0x200>;
416 #address-cells = <3>;
417 #size-cells = <2>;
418
419 device_type = "pci";
420 bus-range = <0x00 0x01>;
421 ranges = <0x2000000 0 0x30000000 0x30000000 0 0x8000000>,
422 <0x1000000 0 0x08000000 0x08000000 0 0x0010000>;
423 linux,pci-probe-only = <1>;
424
425 interrupt-parent = <&periph_intc>;
426 interrupts = <BCM6368_IRQ_MPI>;
427
428 resets = <&periph_rst BCM6368_RST_MPI>;
429 reset-names = "pci";
430
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_pci>;
433
434 brcm,remap;
435
436 status = "disabled";
437 };
438
439 ehci: usb@10001500 {
440 compatible = "brcm,bcm6368-ehci", "generic-ehci";
441 reg = <0x10001500 0x100>;
442 big-endian;
443 spurious-oc;
444
445 interrupt-parent = <&periph_intc>;
446 interrupts = <BCM6368_IRQ_EHCI>;
447
448 phys = <&usbh 0>;
449 phy-names = "usb";
450
451 status = "disabled";
452 };
453
454 ohci: usb@10001600 {
455 compatible = "brcm,bcm6368-ohci", "generic-ohci";
456 reg = <0x10001600 0x100>;
457 big-endian;
458 no-big-frame-no;
459
460 interrupt-parent = <&periph_intc>;
461 interrupts = <BCM6368_IRQ_OHCI>;
462
463 phys = <&usbh 0>;
464 phy-names = "usb";
465
466 status = "disabled";
467 };
468
469 usbh: usb-phy@10001700 {
470 compatible = "brcm,bcm6368-usbh-phy";
471 reg = <0x10001700 0x38>;
472
473 #phy-cells = <1>;
474
475 clocks = <&periph_clk BCM6368_CLK_USBH>;
476 clock-names = "usbh";
477
478 resets = <&periph_rst BCM6368_RST_USBH>;
479
480 status = "disabled";
481 };
482
483 random: rng@10004180 {
484 compatible = "brcm,bcm6368-rng";
485 reg = <0x10004180 0x14>;
486
487 clocks = <&periph_clk BCM6368_CLK_IPSEC>;
488 clock-names = "ipsec";
489
490 resets = <&periph_rst BCM6368_RST_IPSEC>;
491 };
492
493 ethernet: ethernet@10006800 {
494 compatible = "brcm,bcm6368-enetsw";
495 reg = <0x10006800 0x80>,
496 <0x10006a00 0x80>,
497 <0x10006c00 0x80>;
498 reg-names = "dma",
499 "dma-channels",
500 "dma-sram";
501
502 interrupt-parent = <&periph_intc>;
503 interrupts = <BCM6368_IRQ_ENETSW_RX_DMA0>,
504 <BCM6368_IRQ_ENETSW_TX_DMA0>;
505 interrupt-names = "rx",
506 "tx";
507
508 clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>,
509 <&periph_clk BCM6368_CLK_SWPKT_SAR>,
510 <&periph_clk BCM6368_CLK_ROBOSW>;
511
512 resets = <&periph_rst BCM6368_RST_SWITCH>,
513 <&periph_rst BCM6368_RST_EPHY>;
514
515 dma-rx = <0>;
516 dma-tx = <1>;
517
518 status = "disabled";
519 };
520
521 switch0: switch@10f00000 {
522 #address-cells = <1>;
523 #size-cells = <0>;
524 compatible = "brcm,bcm6368-switch";
525 reg = <0x10f00000 0x8000>;
526 big-endian;
527
528 ports {
529 #address-cells = <1>;
530 #size-cells = <0>;
531
532 port@8 {
533 reg = <8>;
534
535 phy-mode = "internal";
536 ethernet = <&ethernet>;
537
538 fixed-link {
539 speed = <1000>;
540 full-duplex;
541 };
542 };
543 };
544 };
545
546 mdio: mdio@10f000b0 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 compatible = "brcm,bcm6368-mdio-mux";
550 reg = <0x10f000b0 0x8>;
551
552 mdio_int: mdio@0 {
553 #address-cells = <1>;
554 #size-cells = <0>;
555 reg = <0>;
556
557 phy1: ethernet-phy@1 {
558 compatible = "ethernet-phy-ieee802.3-c22";
559 reg = <1>;
560 };
561
562 phy2: ethernet-phy@2 {
563 compatible = "ethernet-phy-ieee802.3-c22";
564 reg = <2>;
565 };
566
567 phy3: ethernet-phy@3 {
568 compatible = "ethernet-phy-ieee802.3-c22";
569 reg = <3>;
570 };
571
572 phy4: ethernet-phy@4 {
573 compatible = "ethernet-phy-ieee802.3-c22";
574 reg = <4>;
575 };
576 };
577
578 mdio_ext: mdio@1 {
579 #address-cells = <1>;
580 #size-cells = <0>;
581 reg = <1>;
582 };
583 };
584 };
585
586 pflash: nor@18000000 {
587 #address-cells = <1>;
588 #size-cells = <1>;
589 compatible = "cfi-flash";
590 reg = <0x18000000 0x2000000>;
591 bank-width = <2>;
592
593 status = "disabled";
594 };
595 };