plat/bcm/include/bcm963xx/6878_map_part.h

   1 /*
   2 <:copyright-BRCM:2015:DUAL/GPL:standard
   3
   4    Copyright (c) 2015 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22
  23 */
  24
  25 #ifndef __BCM6878_MAP_PART_H
  26 #define __BCM6878_MAP_PART_H
  27
  28 #ifdef __cplusplus
  29 extern "C" {
  30 #endif
  31
  32 #include "bcmtypes.h"
  33
  34 #define MEMC_PHYS_BASE          0x80180000
  35 #define MEMC_SIZE               0x24000
  36
  37 #define PMC_PHYS_BASE           0xffb20000
  38 #define PMC_SIZE                0x1000
  39 #define PMB_OFFSET              0x100
  40
  41 #define PERF_PHYS_BASE          0xff800000
  42 #define PERF_SIZE               0x13000
  43 #define TIMR_OFFSET             0x0400
  44 #define WDTIMR0_OFFSET          0x0480
  45 #define WDTIMR1_OFFSET          0x04c0
  46
  47 #define BIUCFG_PHYS_BASE        0x81060000
  48 #define BIUCFG_SIZE             0x3000
  49 #define BIUCFG_OFFSET           0x0000
  50
  51 #define BOOTLUT_PHYS_BASE       0xffff0000
  52 #define BOOTLUT_SIZE            0x1000
  53
  54 #define GIC_PHYS_BASE           0x81000000
  55 #define GIC_SIZE                0x10000
  56 #define GIC_OFFSET              0x0000
  57 #define GICD_OFFSET             0x1000
  58 #define GICC_OFFSET             0x2000
  59
  60 #define PMC_BASE                (PMC_PHYS_BASE + 0)
  61 #define PMB_BASE                (PMC_PHYS_BASE + PMB_OFFSET)
  62
  63 #define WDTIMR0_BASE            (PERF_PHYS_BASE + WDTIMR0_OFFSET)
  64 #define TIMR_BASE               (PERF_PHYS_BASE + TIMR_OFFSET)
  65
  66 #define BIUCFG_BASE             (BIUCFG_PHYS_BASE + BIUCFG_OFFSET)
  67
  68
  69 #ifndef __ASSEMBLER__
  70
  71 /*
  72  * Power Management Control
  73  */
  74
  75 typedef union
  76 {
  77     struct
  78     {
  79         uint32 propagate_to_err  :  1; // [00:00] -+
  80         uint32 propagate_slv_err :  1; // [01:01]  | - these are potentially dangerous and MAY cause a system crash
  81         uint32 pmbus_reset_n     :  1; // [02:02] -+
  82         uint32 reserved0         :  1; // [03:03]
  83         uint32 maxPmbIdx         :  3; // [06:04] 0-based (0-7)
  84         uint32 reserved1         :  1; // [07:07]
  85         uint32 maxClientId       : 12; // [19:08] 0-based (theoreticaly 0-4095, but code limits this to 256 devices - 0-255)
  86         uint32 numRegsPerClient  : 10; // [29:20] some power of 2 - number of 32-bit registers in each client (max = 512)
  87         uint32 startDiscovery    :  1; // [30:30] kicks off H/W discovery of clients and fills in the map (see PMB_REGS below)
  88         uint32 discoveryBusy     :  1; // [31:31] whether or not H/W discovery is still busy creating the map
  89     } Bits;
  90     uint32 Reg32;
  91 } PMB_CONFIG_REG;
  92
  93 typedef union
  94 {
  95     struct {
  96         uint32 data      : 16; // [15:00]
  97         uint32 reserved1 : 16; // [31:16]
  98     } Bits;
  99     uint32 Reg32;
 100 } SSBM_data_reg;
 101
 102 typedef union
 103 {
 104     struct {
 105         uint32  ssb_addr    : 10; // [09:00]
 106         uint32  ssb_cmd     :  2; // [11:10]
 107         uint32  ssb_en      :  1; // [12:12]
 108         uint32  ssb_add_pre :  1; // [13:13]
 109         uint32  reserved2   :  1; // [14:14]
 110         uint32  ssb_start   :  1; // [15:15]
 111         uint32  reserved1   : 16; // [31:16]
 112     } Bits;
 113     uint32 Reg32;
 114 } SSBM_control_reg;
 115
 116 typedef union
 117 {
 118     struct {
 119         uint32 busy      :  1; // [00:00]
 120         uint32 reserved1 : 31; // [31:01]
 121     } Bits;
 122     uint32 Reg32;
 123 } SSBM_status_reg;
 124
 125 typedef union
 126 {
 127     struct {
 128         uint32 swreg_th_lo : 8; // [07:00]
 129         uint32 swreg_th_hi : 8; // [15:08]
 130         uint32 reserved    :16; // [31:16]
 131     } Bits;
 132     uint32 Reg32;
 133 } SSBM_SWREG_th_hilo_reg;
 134
 135 typedef union
 136 {
 137     struct {
 138         uint32 ssb_lock_addr : 10; // [09:00]
 139         uint32 lock_bit      :  1; // [10:10]
 140         uint32 lock_mode     :  1; // [11:11]
 141         uint32 reserved      : 20; // [31:12]
 142     } Bits;
 143     uint32 Reg32;
 144 } SSBM_SWREG_lock_reg;
 145
 146 #define kSSBWrite   0x01
 147 #define kSSBRead    0x02
 148 #define kSSBEn      (1 << 12)
 149 #define kSSBStart   (1 << 15)
 150
 151 typedef struct SSBMaster {
 152     SSBM_control_reg        ssbmControl;    /* 0x0060 */
 153     SSBM_data_reg           ssbmWrData;     /* 0x0064 */
 154     SSBM_data_reg           ssbmRdData;     /* 0x0068 */
 155     SSBM_status_reg         ssbmStatus;     /* 0x006c */
 156     SSBM_SWREG_th_hilo_reg  ssbmThHiLo;     /* 0x0070 */
 157     SSBM_SWREG_lock_reg     ssbmSwLock;     /* 0x0074 */
 158 } SSBMaster;
 159
 160 typedef struct PmmReg {
 161     uint32 memPowerCtrl;            /* 0x0000 */
 162     uint32 regSecurityConfig;       /* 0x0004 */
 163 } PmmReg;
 164
 165 typedef struct keyholeReg {
 166     uint32 ctrlSts;
 167     uint32 wrData;
 168     uint32 mutex;
 169     uint32 rdData;
 170 } keyholeReg;
 171
 172 typedef struct PmbBus {
 173     PMB_CONFIG_REG config;          /* 0x0100 */
 174     uint32 arbiter;         /* 0x0104 */
 175     uint32 timeout;         /* 0x0108 */
 176     uint32 unused1;         /* 0x010c */
 177     keyholeReg keyhole[4];  /* 0x0110-0x014f */
 178     uint32 unused2[44];     /* 0x0150-0x01ff */
 179     uint32 map[64];         /* 0x0200-0x02ff */
 180 }PmbBus;
 181
 182 typedef struct Pmc {
 183     PmmReg  pmm;                        /* 0x20000 */
 184     uint32 unused11[22];                /* 0x20008-0x2005f */
 185     SSBMaster ssbMasterCtrl;            /* 0x20060-0x20077 */
 186     uint32 unused12[34];                /* 0x20078-0x200ff */
 187     PmbBus pmb;                         /* 0x20100 */
 188 } Pmc;
 189 #define PMC ((volatile Pmc * const) PMC_BASE)
 190
 191 typedef struct
 192 {
 193     uint32  control;
 194 #define PMC_PMBM_START                  (1 << 31)
 195 #define PMC_PMBM_TIMEOUT                (1 << 30)
 196 #define PMC_PMBM_SLAVE_ERR              (1 << 29)
 197 #define PMC_PMBM_BUSY                   (1 << 28)
 198 #define PMC_PMBM_BUS_SHIFT              (20)
 199 #define PMC_PMBM_Read                   (0 << 24)
 200 #define PMC_PMBM_Write                  (1 << 24)
 201     uint32  wr_data;
 202     uint32  mutex;
 203     uint32  rd_data;
 204 } PMB_keyhole_reg;
 205
 206 typedef struct PMBMaster {
 207     uint32 config;
 208 #define PMB_NUM_REGS_SHIFT (20)
 209 #define PMB_NUM_REGS_MASK  (0x3ff)
 210     uint32 arbitger;
 211     uint32 timeout;
 212     uint32 reserved;
 213     PMB_keyhole_reg keyhole[4];
 214     uint32 reserved1[44];
 215     uint32 map[64];
 216 } PMBMaster;
 217 #define PMB ((volatile PMBMaster * const) PMB_BASE)
 218
 219 /*
 220 ** Timer
 221 */
 222 #define TIMER_64BIT
 223 typedef struct Timer {
 224     uint64        TimerCtl0;
 225     uint64        TimerCtl1;
 226     uint64        TimerCtl2;
 227     uint64        TimerCtl3;
 228 #define TIMERENABLE     (1ULL << 63)
 229 #define RSTCNTCLR       (1ULL << 62)
 230     uint64        TimerCnt0;
 231     uint64        TimerCnt1;
 232     uint64        TimerCnt2;
 233     uint64        TimerCnt3;
 234 #define TIMER_COUNT_MASK   0x3FFFFFFFFFFFFFFFULL
 235     uint32        TimerMask;
 236 #define TIMER0EN        0x01
 237 #define TIMER1EN        0x02
 238 #define TIMER2EN        0x04
 239 #define TIMER3EN        0x08
 240     uint32        TimerInts;
 241 #define TIMER0          0x01
 242 #define TIMER1          0x02
 243 #define TIMER2          0x04
 244 #define TIMER3          0x08
 245     uint32        ResetReason;
 246 #define SW_INI_RESET            0x00000001
 247     uint32        spare[3];
 248 } Timer;
 249
 250 typedef struct WDTimer {
 251     uint32        WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer
 252      * Write 0xee00 0x00ee to Stop and re-load default count
 253      *      *      * Read from this register returns current watch dog count
 254      *           *           */
 255     uint32        WatchDogCtl;
 256
 257     /* Number of 50-MHz ticks for WD Reset pulse to last */
 258     uint32        WDResetCount;
 259
 260     uint32        WDTimerCtl;
 261 #define SOFT_RESET              0x00000001
 262     uint32        WDAccessCtl;
 263 } WDTimer;
 264
 265 #define TIMER ((volatile Timer * const) TIMR_BASE)
 266 #define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE)
 267
 268 typedef struct BIUCFG_Access {
 269     uint32 permission;        /* 0x0 */
 270     uint32 revd0;             /* 0x4 */
 271     uint32 cpu_defeature;     /* 0x8 */
 272     uint32 dbg_security;      /* 0xc */
 273     uint32 rsvd1[36];         /* 0x10 - 0x9f */
 274     uint32 ts_access;         /* 0xa0 - 0xa3 */
 275     uint32 rsvd2[23];         /* 0xa4 - 0xff */
 276 }BIUCFG_Access;
 277
 278
 279 typedef struct BIUCFG_Cluster {
 280     uint32 permission;        /* 0x0 */
 281     uint32 config;            /* 0x4 */
 282     uint32 status;            /* 0x8 */
 283     uint32 control;           /* 0xc */
 284     uint32 cpucfg;            /* 0x10 */
 285     uint32 dbgrom;            /* 0x14 */
 286     uint32 rsvd1[2];          /* 0x18 - 0x1f */
 287     uint64 rvbar_addr[4];     /* 0x20 - 0x3f */
 288     uint32 rsvd2[48];         /* 0x40 - 0xff */
 289 }BIUCFG_Cluster;
 290
 291 typedef struct BIUCFG {
 292     BIUCFG_Access access;         /* 0x0 - 0xff*/
 293     BIUCFG_Cluster cluster[2];    /* 0x100 - 0x2ff*/
 294     uint32 anonymous[2880];       /* 0x300 - 0x2fff*/
 295 }BIUCFG;
 296 #define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
 297
 298 #endif /* __ASSEMBLER__ */
 299
 300
 301 #ifdef __cplusplus
 302 }
 303 #endif
 304
 305 #endif