include/lib/cpus/aarch64/cortex_a53.h

   1 /*
   2  * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef CORTEX_A53_H
   8 #define CORTEX_A53_H
   9
  10 #include <lib/utils_def.h>
  11
  12 /* Cortex-A53 midr for revision 0 */
  13 #define CORTEX_A53_MIDR                 U(0x410FD030)
  14 #define CORTEX_B53_MIDR                 U(0x420F1000)
  15
  16 /* Retention timer tick definitions */
  17 #define RETENTION_ENTRY_TICKS_2         U(0x1)
  18 #define RETENTION_ENTRY_TICKS_8         U(0x2)
  19 #define RETENTION_ENTRY_TICKS_32        U(0x3)
  20 #define RETENTION_ENTRY_TICKS_64        U(0x4)
  21 #define RETENTION_ENTRY_TICKS_128       U(0x5)
  22 #define RETENTION_ENTRY_TICKS_256       U(0x6)
  23 #define RETENTION_ENTRY_TICKS_512       U(0x7)
  24
  25 /*******************************************************************************
  26  * CPU Extended Control register specific definitions.
  27  ******************************************************************************/
  28 #define CORTEX_A53_ECTLR_EL1                            S3_1_C15_C2_1
  29
  30 #define CORTEX_A53_ECTLR_SMP_BIT                        (ULL(1) << 6)
  31
  32 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT             U(0)
  33 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK              (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
  34
  35 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT             U(3)
  36 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK              (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
  37
  38 /*******************************************************************************
  39  * CPU Memory Error Syndrome register specific definitions.
  40  ******************************************************************************/
  41 #define CORTEX_A53_MERRSR_EL1                           S3_1_C15_C2_2
  42
  43 /*******************************************************************************
  44  * CPU Auxiliary Control register specific definitions.
  45  ******************************************************************************/
  46 #define CORTEX_A53_CPUACTLR_EL1                         S3_1_C15_C2_0
  47
  48 #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT         U(44)
  49 #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI               (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
  50 #define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT             U(27)
  51 #define CORTEX_A53_CPUACTLR_EL1_RADIS                   (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
  52 #define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT           U(25)
  53 #define CORTEX_A53_CPUACTLR_EL1_L1RADIS                 (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
  54 #define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT              U(24)
  55 #define CORTEX_A53_CPUACTLR_EL1_DTAH                    (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
  56
  57 /*******************************************************************************
  58  * L2 Auxiliary Control register specific definitions.
  59  ******************************************************************************/
  60 #define CORTEX_A53_L2ACTLR_EL1                          S3_1_C15_C0_0
  61
  62 #define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN           (U(1) << 14)
  63 #define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH           (U(1) << 3)
  64 /*******************************************************************************
  65  * L2 Extended Control register specific definitions.
  66  ******************************************************************************/
  67 #define CORTEX_A53_L2ECTLR_EL1                          S3_1_C11_C0_3
  68
  69 #define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT               U(0)
  70 #define CORTEX_A53_L2ECTLR_RET_CTRL_MASK                (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
  71
  72 /*******************************************************************************
  73  * L2 Memory Error Syndrome register specific definitions.
  74  ******************************************************************************/
  75 #define CORTEX_A53_L2MERRSR_EL1                         S3_1_C15_C2_3
  76
  77 /*******************************************************************************
  78  * Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs
  79  ******************************************************************************/
  80 #ifndef __ASSEMBLER__
  81 DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1)
  82 #endif /* __ASSEMBLER__ */
  83
  84 #endif /* CORTEX_A53_H */