include/lib/cpus/aarch64/cortex_a53.h

   1 /*
   2  * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef CORTEX_A53_H
   8 #define CORTEX_A53_H
   9
  10 #include <lib/utils_def.h>
  11
  12 /* Cortex-A53 midr for revision 0 */
  13 #define CORTEX_A53_MIDR                 U(0x410FD030)
  14
  15 /* Retention timer tick definitions */
  16 #define RETENTION_ENTRY_TICKS_2         U(0x1)
  17 #define RETENTION_ENTRY_TICKS_8         U(0x2)
  18 #define RETENTION_ENTRY_TICKS_32        U(0x3)
  19 #define RETENTION_ENTRY_TICKS_64        U(0x4)
  20 #define RETENTION_ENTRY_TICKS_128       U(0x5)
  21 #define RETENTION_ENTRY_TICKS_256       U(0x6)
  22 #define RETENTION_ENTRY_TICKS_512       U(0x7)
  23
  24 /*******************************************************************************
  25  * CPU Extended Control register specific definitions.
  26  ******************************************************************************/
  27 #define CORTEX_A53_ECTLR_EL1                            S3_1_C15_C2_1
  28
  29 #define CORTEX_A53_ECTLR_SMP_BIT                        (ULL(1) << 6)
  30
  31 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT             U(0)
  32 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK              (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
  33
  34 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT             U(3)
  35 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK              (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
  36
  37 /*******************************************************************************
  38  * CPU Memory Error Syndrome register specific definitions.
  39  ******************************************************************************/
  40 #define CORTEX_A53_MERRSR_EL1                           S3_1_C15_C2_2
  41
  42 /*******************************************************************************
  43  * CPU Auxiliary Control register specific definitions.
  44  ******************************************************************************/
  45 #define CORTEX_A53_CPUACTLR_EL1                         S3_1_C15_C2_0
  46
  47 #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT         U(44)
  48 #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI               (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
  49 #define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT             U(27)
  50 #define CORTEX_A53_CPUACTLR_EL1_RADIS                   (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
  51 #define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT           U(25)
  52 #define CORTEX_A53_CPUACTLR_EL1_L1RADIS                 (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
  53 #define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT              U(24)
  54 #define CORTEX_A53_CPUACTLR_EL1_DTAH                    (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
  55
  56 /*******************************************************************************
  57  * L2 Auxiliary Control register specific definitions.
  58  ******************************************************************************/
  59 #define CORTEX_A53_L2ACTLR_EL1                          S3_1_C15_C0_0
  60
  61 #define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN           (U(1) << 14)
  62 #define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH           (U(1) << 3)
  63 /*******************************************************************************
  64  * L2 Extended Control register specific definitions.
  65  ******************************************************************************/
  66 #define CORTEX_A53_L2ECTLR_EL1                          S3_1_C11_C0_3
  67
  68 #define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT               U(0)
  69 #define CORTEX_A53_L2ECTLR_RET_CTRL_MASK                (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
  70
  71 /*******************************************************************************
  72  * L2 Memory Error Syndrome register specific definitions.
  73  ******************************************************************************/
  74 #define CORTEX_A53_L2MERRSR_EL1                         S3_1_C15_C2_3
  75
  76 /*******************************************************************************
  77  * Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs
  78  ******************************************************************************/
  79 #ifndef __ASSEMBLER__
  80 DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1)
  81 #endif /* __ASSEMBLER__ */
  82
  83 #endif /* CORTEX_A53_H */