include/arch/aarch32/el3_common_macros.S

   1 /*
   2  * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef EL3_COMMON_MACROS_S
   8 #define EL3_COMMON_MACROS_S
   9
  10 #include <arch.h>
  11 #include <asm_macros.S>
  12 #include <assert_macros.S>
  13
  14         /*
  15          * Helper macro to initialise EL3 registers we care about.
  16          */
  17         .macro el3_arch_init_common
  18         /* ---------------------------------------------------------------------
  19          * SCTLR has already been initialised - read current value before
  20          * modifying.
  21          *
  22          * SCTLR.I: Enable the instruction cache.
  23          *
  24          * SCTLR.A: Enable Alignment fault checking. All instructions that load
  25          *  or store one or more registers have an alignment check that the
  26          *  address being accessed is aligned to the size of the data element(s)
  27          *  being accessed.
  28          * ---------------------------------------------------------------------
  29          */
  30         ldr     r1, =(SCTLR_I_BIT | SCTLR_A_BIT)
  31         ldcopr  r0, SCTLR
  32         orr     r0, r0, r1
  33         stcopr  r0, SCTLR
  34         isb
  35
  36         /* ---------------------------------------------------------------------
  37          * Initialise SCR, setting all fields rather than relying on the hw.
  38          *
  39          * SCR.SIF: Enabled so that Secure state instruction fetches from
  40          *  Non-secure memory are not permitted.
  41          * ---------------------------------------------------------------------
  42          */
  43         ldr     r0, =(SCR_RESET_VAL | SCR_SIF_BIT)
  44         stcopr  r0, SCR
  45
  46         /* -----------------------------------------------------
  47          * Enable the Asynchronous data abort now that the
  48          * exception vectors have been setup.
  49          * -----------------------------------------------------
  50          */
  51         cpsie   a
  52         isb
  53
  54         /* ---------------------------------------------------------------------
  55          * Initialise NSACR, setting all the fields, except for the
  56          * IMPLEMENTATION DEFINED field, rather than relying on the hw. Some
  57          * fields are architecturally UNKNOWN on reset.
  58          *
  59          * NSACR_ENABLE_FP_ACCESS: Represents NSACR.cp11 and NSACR.cp10. The
  60          *  cp11 field is ignored, but is set to same value as cp10. The cp10
  61          *  field is set to allow access to Advanced SIMD and floating point
  62          *  features from both Security states.
  63          * ---------------------------------------------------------------------
  64          */
  65         ldcopr  r0, NSACR
  66         and     r0, r0, #NSACR_IMP_DEF_MASK
  67         orr     r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS)
  68         stcopr  r0, NSACR
  69         isb
  70
  71         /* ---------------------------------------------------------------------
  72          * Initialise CPACR, setting all fields rather than relying on hw. Some
  73          * fields are architecturally UNKNOWN on reset.
  74          *
  75          * CPACR.TRCDIS: Trap control for PL0 and PL1 System register accesses
  76          *  to trace registers. Set to zero to allow access.
  77          *
  78          * CPACR_ENABLE_FP_ACCESS: Represents CPACR.cp11 and CPACR.cp10. The
  79          *  cp11 field is ignored, but is set to same value as cp10. The cp10
  80          *  field is set to allow full access from PL0 and PL1 to floating-point
  81          *  and Advanced SIMD features.
  82          * ---------------------------------------------------------------------
  83          */
  84         ldr     r0, =((CPACR_RESET_VAL | CPACR_ENABLE_FP_ACCESS) & ~(TRCDIS_BIT))
  85         stcopr  r0, CPACR
  86         isb
  87
  88         /* ---------------------------------------------------------------------
  89          * Initialise FPEXC, setting all fields rather than relying on hw. Some
  90          * fields are architecturally UNKNOWN on reset and are set to zero
  91          * except for field(s) listed below.
  92          *
  93          * FPEXC.EN: Enable access to Advanced SIMD and floating point features
  94          *  from all exception levels.
  95          *
  96          * __SOFTFP__: Predefined macro exposed by soft-float toolchain.
  97          *  ARMv7 and Cortex-A32(ARMv8/aarch32) has both soft-float and
  98          *  hard-float variants of toolchain, avoid compiling below code with
  99          *  soft-float toolchain as "vmsr" instruction will not be recognized.
 100          * ---------------------------------------------------------------------
 101          */
 102 #if ((ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP)) && !(__SOFTFP__)
 103         /* BRCM_PATCH: BCM63138 does not have NEON in 2nd CPU */
 104 #if defined (PLATFORM_FLAVOR_63138)
 105         bl      plat_my_core_pos
 106         cmp     r0, #0
 107         ldreq   r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT)
 108         vmsreq  FPEXC, r0
 109 #else
 110         ldr     r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT)
 111         vmsr    FPEXC, r0
 112 #endif
 113         isb
 114 #endif
 115
 116 #if (ARM_ARCH_MAJOR > 7)
 117         /* ---------------------------------------------------------------------
 118          * Initialise SDCR, setting all the fields rather than relying on hw.
 119          *
 120          * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from
 121          *  Secure EL1 are disabled.
 122          *
 123          * SDCR.SCCD: Set to one so that cycle counting by PMCCNTR is prohibited
 124          *  in Secure state. This bit is RES0 in versions of the architecture
 125          *  earlier than ARMv8.5, setting it to 1 doesn't have any effect on
 126          *  them.
 127          * ---------------------------------------------------------------------
 128          */
 129         ldr     r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE) | SDCR_SCCD_BIT)
 130         stcopr  r0, SDCR
 131
 132         /* ---------------------------------------------------------------------
 133          * Initialise PMCR, setting all fields rather than relying
 134          * on hw. Some fields are architecturally UNKNOWN on reset.
 135          *
 136          * PMCR.LP: Set to one so that event counter overflow, that
 137          *  is recorded in PMOVSCLR[0-30], occurs on the increment
 138          *  that changes PMEVCNTR<n>[63] from 1 to 0, when ARMv8.5-PMU
 139          *  is implemented. This bit is RES0 in versions of the architecture
 140          *  earlier than ARMv8.5, setting it to 1 doesn't have any effect
 141          *  on them.
 142          *  This bit is Reserved, UNK/SBZP in ARMv7.
 143          *
 144          * PMCR.LC: Set to one so that cycle counter overflow, that
 145          *  is recorded in PMOVSCLR[31], occurs on the increment
 146          *  that changes PMCCNTR[63] from 1 to 0.
 147          *  This bit is Reserved, UNK/SBZP in ARMv7.
 148          *
 149          * PMCR.DP: Set to one to prohibit cycle counting whilst in Secure mode.
 150          * ---------------------------------------------------------------------
 151          */
 152         ldr     r0, =(PMCR_RESET_VAL | PMCR_DP_BIT | PMCR_LC_BIT | \
 153                       PMCR_LP_BIT)
 154 #else
 155         ldr     r0, =(PMCR_RESET_VAL | PMCR_DP_BIT)
 156 #endif
 157         /* BRCM_PATCH: Do not overwrite the setting done by BRCM boot loaders
 158         stcopr  r0, PMCR
 159         */
 160
 161         /*
 162          * If Data Independent Timing (DIT) functionality is implemented,
 163          * always enable DIT in EL3
 164          */
 165         ldcopr  r0, ID_PFR0
 166         and     r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT)
 167         cmp     r0, #ID_PFR0_DIT_SUPPORTED
 168         bne     1f
 169         mrs     r0, cpsr
 170         orr     r0, r0, #CPSR_DIT_BIT
 171         msr     cpsr_cxsf, r0
 172 1:
 173         .endm
 174
 175 /* -----------------------------------------------------------------------------
 176  * This is the super set of actions that need to be performed during a cold boot
 177  * or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN).
 178  *
 179  * This macro will always perform reset handling, architectural initialisations
 180  * and stack setup. The rest of the actions are optional because they might not
 181  * be needed, depending on the context in which this macro is called. This is
 182  * why this macro is parameterised ; each parameter allows to enable/disable
 183  * some actions.
 184  *
 185  *  _init_sctlr:
 186  *      Whether the macro needs to initialise the SCTLR register including
 187  *      configuring the endianness of data accesses.
 188  *
 189  *  _warm_boot_mailbox:
 190  *      Whether the macro needs to detect the type of boot (cold/warm). The
 191  *      detection is based on the platform entrypoint address : if it is zero
 192  *      then it is a cold boot, otherwise it is a warm boot. In the latter case,
 193  *      this macro jumps on the platform entrypoint address.
 194  *
 195  *  _secondary_cold_boot:
 196  *      Whether the macro needs to identify the CPU that is calling it: primary
 197  *      CPU or secondary CPU. The primary CPU will be allowed to carry on with
 198  *      the platform initialisations, while the secondaries will be put in a
 199  *      platform-specific state in the meantime.
 200  *
 201  *      If the caller knows this macro will only be called by the primary CPU
 202  *      then this parameter can be defined to 0 to skip this step.
 203  *
 204  * _init_memory:
 205  *      Whether the macro needs to initialise the memory.
 206  *
 207  * _init_c_runtime:
 208  *      Whether the macro needs to initialise the C runtime environment.
 209  *
 210  * _exception_vectors:
 211  *      Address of the exception vectors to program in the VBAR_EL3 register.
 212  * -----------------------------------------------------------------------------
 213  */
 214         .macro el3_entrypoint_common                                    \
 215                 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot,  \
 216                 _init_memory, _init_c_runtime, _exception_vectors
 217
 218         /* Make sure we are in Secure Mode */
 219 #if ENABLE_ASSERTIONS
 220         ldcopr  r0, SCR
 221         tst     r0, #SCR_NS_BIT
 222         ASM_ASSERT(eq)
 223 #endif
 224
 225         .if \_init_sctlr
 226                 /* -------------------------------------------------------------
 227                  * This is the initialisation of SCTLR and so must ensure that
 228                  * all fields are explicitly set rather than relying on hw. Some
 229                  * fields reset to an IMPLEMENTATION DEFINED value.
 230                  *
 231                  * SCTLR.TE: Set to zero so that exceptions to an Exception
 232                  *  Level executing at PL1 are taken to A32 state.
 233                  *
 234                  * SCTLR.EE: Set the CPU endianness before doing anything that
 235                  *  might involve memory reads or writes. Set to zero to select
 236                  *  Little Endian.
 237                  *
 238                  * SCTLR.V: Set to zero to select the normal exception vectors
 239                  *  with base address held in VBAR.
 240                  *
 241                  * SCTLR.DSSBS: Set to zero to disable speculation store bypass
 242                  *  safe behaviour upon exception entry to EL3.
 243                  * -------------------------------------------------------------
 244                  */
 245                 ldr     r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | \
 246                                 SCTLR_V_BIT | SCTLR_DSSBS_BIT))
 247                 stcopr  r0, SCTLR
 248                 isb
 249         .endif /* _init_sctlr */
 250
 251         /* Switch to monitor mode */
 252         cps     #MODE32_mon
 253         isb
 254
 255         .if \_warm_boot_mailbox
 256                 /* -------------------------------------------------------------
 257                  * This code will be executed for both warm and cold resets.
 258                  * Now is the time to distinguish between the two.
 259                  * Query the platform entrypoint address and if it is not zero
 260                  * then it means it is a warm boot so jump to this address.
 261                  * -------------------------------------------------------------
 262                  */
 263                 bl      plat_get_my_entrypoint
 264                 cmp     r0, #0
 265                 bxne    r0
 266         .endif /* _warm_boot_mailbox */
 267
 268         /* ---------------------------------------------------------------------
 269          * Set the exception vectors (VBAR/MVBAR).
 270          * ---------------------------------------------------------------------
 271          */
 272         ldr     r0, =\_exception_vectors
 273         stcopr  r0, VBAR
 274         stcopr  r0, MVBAR
 275         isb
 276
 277         /* ---------------------------------------------------------------------
 278          * It is a cold boot.
 279          * Perform any processor specific actions upon reset e.g. cache, TLB
 280          * invalidations etc.
 281          * ---------------------------------------------------------------------
 282          */
 283         bl      reset_handler
 284
 285         el3_arch_init_common
 286
 287         .if \_secondary_cold_boot
 288                 /* -------------------------------------------------------------
 289                  * Check if this is a primary or secondary CPU cold boot.
 290                  * The primary CPU will set up the platform while the
 291                  * secondaries are placed in a platform-specific state until the
 292                  * primary CPU performs the necessary actions to bring them out
 293                  * of that state and allows entry into the OS.
 294                  * -------------------------------------------------------------
 295                  */
 296                 bl      plat_is_my_cpu_primary
 297                 cmp     r0, #0
 298                 bne     do_primary_cold_boot
 299
 300                 /* This is a cold boot on a secondary CPU */
 301                 bl      plat_secondary_cold_boot_setup
 302                 /* plat_secondary_cold_boot_setup() is not supposed to return */
 303                 no_ret  plat_panic_handler
 304
 305         do_primary_cold_boot:
 306         .endif /* _secondary_cold_boot */
 307
 308         /* ---------------------------------------------------------------------
 309          * Initialize memory now. Secondary CPU initialization won't get to this
 310          * point.
 311          * ---------------------------------------------------------------------
 312          */
 313
 314         .if \_init_memory
 315                 bl      platform_mem_init
 316         .endif /* _init_memory */
 317
 318         /* ---------------------------------------------------------------------
 319          * Init C runtime environment:
 320          *   - Zero-initialise the NOBITS sections. There are 2 of them:
 321          *       - the .bss section;
 322          *       - the coherent memory section (if any).
 323          *   - Relocate the data section from ROM to RAM, if required.
 324          * ---------------------------------------------------------------------
 325          */
 326         .if \_init_c_runtime
 327 #if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
 328                 /* -----------------------------------------------------------------
 329                  * Invalidate the RW memory used by the image. This
 330                  * includes the data and NOBITS sections. This is done to
 331                  * safeguard against possible corruption of this memory by
 332                  * dirty cache lines in a system cache as a result of use by
 333                  * an earlier boot loader stage.
 334                  * -----------------------------------------------------------------
 335                  */
 336                 ldr     r0, =__RW_START__
 337                 ldr     r1, =__RW_END__
 338                 sub     r1, r1, r0
 339                 bl      inv_dcache_range
 340 #endif
 341
 342                 ldr     r0, =__BSS_START__
 343                 ldr     r1, =__BSS_SIZE__
 344                 bl      zeromem
 345
 346 #if USE_COHERENT_MEM
 347                 ldr     r0, =__COHERENT_RAM_START__
 348                 ldr     r1, =__COHERENT_RAM_UNALIGNED_SIZE__
 349                 bl      zeromem
 350 #endif
 351
 352 #if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM)
 353                 /* -----------------------------------------------------
 354                  * Copy data from ROM to RAM.
 355                  * -----------------------------------------------------
 356                  */
 357                 ldr     r0, =__DATA_RAM_START__
 358                 ldr     r1, =__DATA_ROM_START__
 359                 ldr     r2, =__DATA_SIZE__
 360                 bl      memcpy4
 361 #endif
 362         .endif /* _init_c_runtime */
 363
 364         /* ---------------------------------------------------------------------
 365          * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
 366          * the MMU is enabled. There is no risk of reading stale stack memory
 367          * after enabling the MMU as only the primary CPU is running at the
 368          * moment.
 369          * ---------------------------------------------------------------------
 370          */
 371         bl      plat_set_my_stack
 372
 373 #if STACK_PROTECTOR_ENABLED
 374         .if \_init_c_runtime
 375         bl      update_stack_protector_canary
 376         .endif /* _init_c_runtime */
 377 #endif
 378         .endm
 379
 380 #endif /* EL3_COMMON_MACROS_S */