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realtek: Trap all frames with switch as destination to CPU-port
[openwrt/staging/chunkeey.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_info("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134 if (priv->family_id == RTL9310_FAMILY_ID) {
135 info.if_id = 0;
136 info.multicast_grp_mask = 0;
137 info.l2_tunnel_list_id = -1;
138 }
139
140 // Initialize all vlans 0-4095
141 for (i = 0; i < MAX_VLANS; i ++)
142 priv->r->vlan_set_tagged(i, &info);
143
144 // reset PVIDs; defaults to 1 on reset
145 for (i = 0; i <= priv->ds->num_ports; i++) {
146 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
147 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
148 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
149 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
150 }
151
152 // Set forwarding action based on inner VLAN tag
153 for (i = 0; i < priv->cpu_port; i++)
154 priv->r->vlan_fwd_on_inner(i, true);
155 }
156
157 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
158 {
159 int i;
160
161 for (i = 0; i < priv->cpu_port; i++)
162 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
163 }
164
165 static int rtl83xx_setup(struct dsa_switch *ds)
166 {
167 int i;
168 struct rtl838x_switch_priv *priv = ds->priv;
169 u64 port_bitmap = BIT_ULL(priv->cpu_port);
170
171 pr_debug("%s called\n", __func__);
172
173 /* Disable MAC polling the PHY so that we can start configuration */
174 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
175
176 for (i = 0; i < ds->num_ports; i++)
177 priv->ports[i].enable = false;
178 priv->ports[priv->cpu_port].enable = true;
179
180 /* Isolate ports from each other: traffic only CPU <-> port */
181 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
182 * traffic from source port i to destination port j
183 */
184 for (i = 0; i < priv->cpu_port; i++) {
185 if (priv->ports[i].phy) {
186 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
187 priv->r->port_iso_ctrl(i));
188 port_bitmap |= BIT_ULL(i);
189 }
190 }
191 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
192
193 if (priv->family_id == RTL8380_FAMILY_ID)
194 rtl838x_print_matrix();
195 else
196 rtl839x_print_matrix();
197
198 rtl83xx_init_stats(priv);
199
200 rtl83xx_vlan_setup(priv);
201
202 rtl83xx_setup_bpdu_traps(priv);
203
204 ds->configure_vlan_while_not_filtering = true;
205
206 priv->r->l2_learning_setup();
207
208 /*
209 * Make sure all frames sent to the switch's MAC are trapped to the CPU-port
210 * 0: FWD, 1: DROP, 2: TRAP2CPU
211 */
212 if (priv->family_id == RTL8380_FAMILY_ID)
213 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
214 else
215 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
216
217 /* Enable MAC Polling PHY again */
218 rtl83xx_enable_phy_polling(priv);
219 pr_debug("Please wait until PHY is settled\n");
220 msleep(1000);
221 priv->r->pie_init(priv);
222
223 return 0;
224 }
225
226 static int rtl93xx_setup(struct dsa_switch *ds)
227 {
228 int i;
229 struct rtl838x_switch_priv *priv = ds->priv;
230 u32 port_bitmap = BIT(priv->cpu_port);
231
232 pr_info("%s called\n", __func__);
233
234 /* Disable MAC polling the PHY so that we can start configuration */
235 if (priv->family_id == RTL9300_FAMILY_ID)
236 sw_w32(0, RTL930X_SMI_POLL_CTRL);
237
238 if (priv->family_id == RTL9310_FAMILY_ID) {
239 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
240 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
241 }
242
243 // Disable all ports except CPU port
244 for (i = 0; i < ds->num_ports; i++)
245 priv->ports[i].enable = false;
246 priv->ports[priv->cpu_port].enable = true;
247
248 for (i = 0; i < priv->cpu_port; i++) {
249 if (priv->ports[i].phy) {
250 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
251 port_bitmap |= BIT_ULL(i);
252 }
253 }
254 priv->r->traffic_set(priv->cpu_port, port_bitmap);
255
256 rtl930x_print_matrix();
257
258 // TODO: Initialize statistics
259
260 rtl83xx_vlan_setup(priv);
261
262 ds->configure_vlan_while_not_filtering = true;
263
264 priv->r->l2_learning_setup();
265
266 rtl83xx_enable_phy_polling(priv);
267
268 priv->r->pie_init(priv);
269
270 priv->r->led_init(priv);
271
272 return 0;
273 }
274
275 static int rtl93xx_get_sds(struct phy_device *phydev)
276 {
277 struct device *dev = &phydev->mdio.dev;
278 struct device_node *dn;
279 u32 sds_num;
280
281 if (!dev)
282 return -1;
283 if (dev->of_node) {
284 dn = dev->of_node;
285 if (of_property_read_u32(dn, "sds", &sds_num))
286 sds_num = -1;
287 } else {
288 dev_err(dev, "No DT node.\n");
289 return -1;
290 }
291
292 return sds_num;
293 }
294
295 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
296 unsigned long *supported,
297 struct phylink_link_state *state)
298 {
299 struct rtl838x_switch_priv *priv = ds->priv;
300 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
301
302 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
303
304 if (!phy_interface_mode_is_rgmii(state->interface) &&
305 state->interface != PHY_INTERFACE_MODE_NA &&
306 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
307 state->interface != PHY_INTERFACE_MODE_MII &&
308 state->interface != PHY_INTERFACE_MODE_REVMII &&
309 state->interface != PHY_INTERFACE_MODE_GMII &&
310 state->interface != PHY_INTERFACE_MODE_QSGMII &&
311 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
312 state->interface != PHY_INTERFACE_MODE_SGMII) {
313 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
314 dev_err(ds->dev,
315 "Unsupported interface: %d for port %d\n",
316 state->interface, port);
317 return;
318 }
319
320 /* Allow all the expected bits */
321 phylink_set(mask, Autoneg);
322 phylink_set_port_modes(mask);
323 phylink_set(mask, Pause);
324 phylink_set(mask, Asym_Pause);
325
326 /* With the exclusion of MII and Reverse MII, we support Gigabit,
327 * including Half duplex
328 */
329 if (state->interface != PHY_INTERFACE_MODE_MII &&
330 state->interface != PHY_INTERFACE_MODE_REVMII) {
331 phylink_set(mask, 1000baseT_Full);
332 phylink_set(mask, 1000baseT_Half);
333 }
334
335 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
336 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
337 phylink_set(mask, 1000baseX_Full);
338
339 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
340 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
341 phylink_set(mask, 1000baseX_Full);
342
343 phylink_set(mask, 10baseT_Half);
344 phylink_set(mask, 10baseT_Full);
345 phylink_set(mask, 100baseT_Half);
346 phylink_set(mask, 100baseT_Full);
347
348 bitmap_and(supported, supported, mask,
349 __ETHTOOL_LINK_MODE_MASK_NBITS);
350 bitmap_and(state->advertising, state->advertising, mask,
351 __ETHTOOL_LINK_MODE_MASK_NBITS);
352 }
353
354 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
355 unsigned long *supported,
356 struct phylink_link_state *state)
357 {
358 struct rtl838x_switch_priv *priv = ds->priv;
359 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
360
361 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
362 phy_modes(state->interface));
363
364 if (!phy_interface_mode_is_rgmii(state->interface) &&
365 state->interface != PHY_INTERFACE_MODE_NA &&
366 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
367 state->interface != PHY_INTERFACE_MODE_MII &&
368 state->interface != PHY_INTERFACE_MODE_REVMII &&
369 state->interface != PHY_INTERFACE_MODE_GMII &&
370 state->interface != PHY_INTERFACE_MODE_QSGMII &&
371 state->interface != PHY_INTERFACE_MODE_XGMII &&
372 state->interface != PHY_INTERFACE_MODE_HSGMII &&
373 state->interface != PHY_INTERFACE_MODE_10GBASER &&
374 state->interface != PHY_INTERFACE_MODE_10GKR &&
375 state->interface != PHY_INTERFACE_MODE_USXGMII &&
376 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
377 state->interface != PHY_INTERFACE_MODE_SGMII) {
378 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
379 dev_err(ds->dev,
380 "Unsupported interface: %d for port %d\n",
381 state->interface, port);
382 return;
383 }
384
385 /* Allow all the expected bits */
386 phylink_set(mask, Autoneg);
387 phylink_set_port_modes(mask);
388 phylink_set(mask, Pause);
389 phylink_set(mask, Asym_Pause);
390
391 /* With the exclusion of MII and Reverse MII, we support Gigabit,
392 * including Half duplex
393 */
394 if (state->interface != PHY_INTERFACE_MODE_MII &&
395 state->interface != PHY_INTERFACE_MODE_REVMII) {
396 phylink_set(mask, 1000baseT_Full);
397 phylink_set(mask, 1000baseT_Half);
398 }
399
400 // Internal phys of the RTL93xx family provide 10G
401 if (priv->ports[port].phy_is_integrated
402 && state->interface == PHY_INTERFACE_MODE_1000BASEX) {
403 phylink_set(mask, 1000baseX_Full);
404 } else if (priv->ports[port].phy_is_integrated) {
405 phylink_set(mask, 1000baseX_Full);
406 phylink_set(mask, 10000baseKR_Full);
407 phylink_set(mask, 10000baseSR_Full);
408 phylink_set(mask, 10000baseCR_Full);
409 }
410 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
411 phylink_set(mask, 1000baseX_Full);
412 phylink_set(mask, 1000baseT_Full);
413 phylink_set(mask, 10000baseKR_Full);
414 phylink_set(mask, 10000baseT_Full);
415 phylink_set(mask, 10000baseSR_Full);
416 phylink_set(mask, 10000baseCR_Full);
417 }
418
419 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
420 phylink_set(mask, 10000baseT_Full);
421
422 phylink_set(mask, 10baseT_Half);
423 phylink_set(mask, 10baseT_Full);
424 phylink_set(mask, 100baseT_Half);
425 phylink_set(mask, 100baseT_Full);
426
427 bitmap_and(supported, supported, mask,
428 __ETHTOOL_LINK_MODE_MASK_NBITS);
429 bitmap_and(state->advertising, state->advertising, mask,
430 __ETHTOOL_LINK_MODE_MASK_NBITS);
431 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
432 }
433
434 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
435 struct phylink_link_state *state)
436 {
437 struct rtl838x_switch_priv *priv = ds->priv;
438 u64 speed;
439 u64 link;
440
441 if (port < 0 || port > priv->cpu_port)
442 return -EINVAL;
443
444 state->link = 0;
445 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
446 if (link & BIT_ULL(port))
447 state->link = 1;
448 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
449
450 state->duplex = 0;
451 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
452 state->duplex = 1;
453
454 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
455 speed >>= (port % 16) << 1;
456 switch (speed & 0x3) {
457 case 0:
458 state->speed = SPEED_10;
459 break;
460 case 1:
461 state->speed = SPEED_100;
462 break;
463 case 2:
464 state->speed = SPEED_1000;
465 break;
466 case 3:
467 if (priv->family_id == RTL9300_FAMILY_ID
468 && (port == 24 || port == 26)) /* Internal serdes */
469 state->speed = SPEED_2500;
470 else
471 state->speed = SPEED_100; /* Is in fact 500Mbit */
472 }
473
474 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
475 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
476 state->pause |= MLO_PAUSE_RX;
477 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
478 state->pause |= MLO_PAUSE_TX;
479 return 1;
480 }
481
482 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
483 struct phylink_link_state *state)
484 {
485 struct rtl838x_switch_priv *priv = ds->priv;
486 u64 speed;
487 u64 link;
488 u64 media;
489
490 if (port < 0 || port > priv->cpu_port)
491 return -EINVAL;
492
493 /*
494 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
495 * state needs to be read twice in order to read a correct result.
496 * This would not be necessary for ports connected e.g. to RTL8218D
497 * PHYs.
498 */
499 state->link = 0;
500 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
501 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
502 if (link & BIT_ULL(port))
503 state->link = 1;
504
505 if (priv->family_id == RTL9310_FAMILY_ID)
506 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
507
508 if (priv->family_id == RTL9300_FAMILY_ID)
509 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
510
511 if (media & BIT_ULL(port))
512 state->link = 1;
513
514 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
515 link & BIT_ULL(port), media);
516
517 state->duplex = 0;
518 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
519 state->duplex = 1;
520
521 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
522 speed >>= (port % 8) << 2;
523 switch (speed & 0xf) {
524 case 0:
525 state->speed = SPEED_10;
526 break;
527 case 1:
528 state->speed = SPEED_100;
529 break;
530 case 2:
531 case 7:
532 state->speed = SPEED_1000;
533 break;
534 case 4:
535 state->speed = SPEED_10000;
536 break;
537 case 5:
538 case 8:
539 state->speed = SPEED_2500;
540 break;
541 case 6:
542 state->speed = SPEED_5000;
543 break;
544 default:
545 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
546 }
547
548 if (priv->family_id == RTL9310_FAMILY_ID
549 && (port >= 52 || port <= 55)) { /* Internal serdes */
550 state->speed = SPEED_10000;
551 state->link = 1;
552 state->duplex = 1;
553 }
554
555 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
556 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
557 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
558 state->pause |= MLO_PAUSE_RX;
559 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
560 state->pause |= MLO_PAUSE_TX;
561 return 1;
562 }
563
564 static void rtl83xx_config_interface(int port, phy_interface_t interface)
565 {
566 u32 old, int_shift, sds_shift;
567
568 switch (port) {
569 case 24:
570 int_shift = 0;
571 sds_shift = 5;
572 break;
573 case 26:
574 int_shift = 3;
575 sds_shift = 0;
576 break;
577 default:
578 return;
579 }
580
581 old = sw_r32(RTL838X_SDS_MODE_SEL);
582 switch (interface) {
583 case PHY_INTERFACE_MODE_1000BASEX:
584 if ((old >> sds_shift & 0x1f) == 4)
585 return;
586 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
587 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
588 break;
589 case PHY_INTERFACE_MODE_SGMII:
590 if ((old >> sds_shift & 0x1f) == 2)
591 return;
592 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
593 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
594 break;
595 default:
596 return;
597 }
598 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
599 }
600
601 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
602 unsigned int mode,
603 const struct phylink_link_state *state)
604 {
605 struct rtl838x_switch_priv *priv = ds->priv;
606 u32 reg;
607 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
608
609 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
610
611 if (port == priv->cpu_port) {
612 /* Set Speed, duplex, flow control
613 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
614 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
615 * | MEDIA_SEL
616 */
617 if (priv->family_id == RTL8380_FAMILY_ID) {
618 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
619 /* allow CRC errors on CPU-port */
620 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
621 } else {
622 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
623 }
624 return;
625 }
626
627 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
628 /* Auto-Negotiation does not work for MAC in RTL8390 */
629 if (priv->family_id == RTL8380_FAMILY_ID) {
630 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
631 pr_debug("PHY autonegotiates\n");
632 reg |= RTL838X_NWAY_EN;
633 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
634 rtl83xx_config_interface(port, state->interface);
635 return;
636 }
637 }
638
639 if (mode != MLO_AN_FIXED)
640 pr_debug("Fixed state.\n");
641
642 /* Clear id_mode_dis bit, and the existing port mode, let
643 * RGMII_MODE_EN bet set by mac_link_{up,down} */
644 if (priv->family_id == RTL8380_FAMILY_ID) {
645 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
646 if (state->pause & MLO_PAUSE_TXRX_MASK) {
647 if (state->pause & MLO_PAUSE_TX)
648 reg |= RTL838X_TX_PAUSE_EN;
649 reg |= RTL838X_RX_PAUSE_EN;
650 }
651 } else if (priv->family_id == RTL8390_FAMILY_ID) {
652 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
653 if (state->pause & MLO_PAUSE_TXRX_MASK) {
654 if (state->pause & MLO_PAUSE_TX)
655 reg |= RTL839X_TX_PAUSE_EN;
656 reg |= RTL839X_RX_PAUSE_EN;
657 }
658 }
659
660
661 reg &= ~(3 << speed_bit);
662 switch (state->speed) {
663 case SPEED_1000:
664 reg |= 2 << speed_bit;
665 break;
666 case SPEED_100:
667 reg |= 1 << speed_bit;
668 break;
669 default:
670 break; // Ignore, including 10MBit which has a speed value of 0
671 }
672
673 if (priv->family_id == RTL8380_FAMILY_ID) {
674 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
675 if (state->link)
676 reg |= RTL838X_FORCE_LINK_EN;
677 if (state->duplex == RTL838X_DUPLEX_MODE)
678 reg |= RTL838X_DUPLEX_MODE;
679 } else if (priv->family_id == RTL8390_FAMILY_ID) {
680 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
681 if (state->link)
682 reg |= RTL839X_FORCE_LINK_EN;
683 if (state->duplex == RTL839X_DUPLEX_MODE)
684 reg |= RTL839X_DUPLEX_MODE;
685 }
686
687 // LAG members must use DUPLEX and we need to enable the link
688 if (priv->lagmembers & BIT_ULL(port)) {
689 switch(priv->family_id) {
690 case RTL8380_FAMILY_ID:
691 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
692 break;
693 case RTL8390_FAMILY_ID:
694 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
695 break;
696 }
697 }
698
699 // Disable AN
700 if (priv->family_id == RTL8380_FAMILY_ID)
701 reg &= ~RTL838X_NWAY_EN;
702 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
703 }
704
705 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
706 unsigned int mode,
707 const struct phylink_link_state *state)
708 {
709 struct rtl838x_switch_priv *priv = ds->priv;
710 int sds_num;
711 u32 reg, band;
712
713 sds_num = priv->ports[port].sds_num;
714 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
715
716 switch (state->interface) {
717 case PHY_INTERFACE_MODE_HSGMII:
718 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
719 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
720 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
721 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
722 break;
723 case PHY_INTERFACE_MODE_1000BASEX:
724 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
725 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
726 break;
727 case PHY_INTERFACE_MODE_XGMII:
728 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
729 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
730 break;
731 case PHY_INTERFACE_MODE_10GBASER:
732 case PHY_INTERFACE_MODE_10GKR:
733 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
734 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
735 break;
736 case PHY_INTERFACE_MODE_USXGMII:
737 // Translates to MII_USXGMII_10GSXGMII
738 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
739 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
740 break;
741 case PHY_INTERFACE_MODE_SGMII:
742 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
743 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
744 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
745 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
746 break;
747 case PHY_INTERFACE_MODE_QSGMII:
748 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
749 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
750 break;
751 default:
752 pr_err("%s: unknown serdes mode: %s\n",
753 __func__, phy_modes(state->interface));
754 return;
755 }
756
757 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
758 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
759
760 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
761
762 reg &= ~(0xf << 12);
763 reg |= 0x2 << 12; // Set SMI speed to 0x2
764
765 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
766
767 if (priv->lagmembers & BIT_ULL(port))
768 reg |= RTL931X_DUPLEX_MODE;
769
770 if (state->duplex == DUPLEX_FULL)
771 reg |= RTL931X_DUPLEX_MODE;
772
773 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
774
775 }
776
777 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
778 unsigned int mode,
779 const struct phylink_link_state *state)
780 {
781 struct rtl838x_switch_priv *priv = ds->priv;
782 int sds_num, sds_mode;
783 u32 reg;
784
785 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
786 port, mode, phy_modes(state->interface), state->speed, state->link);
787
788 // Nothing to be done for the CPU-port
789 if (port == priv->cpu_port)
790 return;
791
792 if (priv->family_id == RTL9310_FAMILY_ID)
793 return rtl931x_phylink_mac_config(ds, port, mode, state);
794
795 sds_num = priv->ports[port].sds_num;
796 pr_info("%s SDS is %d\n", __func__, sds_num);
797 if (sds_num >= 0) {
798 switch (state->interface) {
799 case PHY_INTERFACE_MODE_HSGMII:
800 sds_mode = 0x12;
801 break;
802 case PHY_INTERFACE_MODE_1000BASEX:
803 sds_mode = 0x04;
804 break;
805 case PHY_INTERFACE_MODE_XGMII:
806 sds_mode = 0x10;
807 break;
808 case PHY_INTERFACE_MODE_10GBASER:
809 case PHY_INTERFACE_MODE_10GKR:
810 sds_mode = 0x1b; // 10G 1000X Auto
811 break;
812 case PHY_INTERFACE_MODE_USXGMII:
813 sds_mode = 0x0d;
814 break;
815 default:
816 pr_err("%s: unknown serdes mode: %s\n",
817 __func__, phy_modes(state->interface));
818 return;
819 }
820 rtl9300_sds_rst(sds_num, sds_mode);
821 }
822
823 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
824 reg &= ~(0xf << 3);
825
826 switch (state->speed) {
827 case SPEED_10000:
828 reg |= 4 << 3;
829 break;
830 case SPEED_5000:
831 reg |= 6 << 3;
832 break;
833 case SPEED_2500:
834 reg |= 5 << 3;
835 break;
836 case SPEED_1000:
837 reg |= 2 << 3;
838 break;
839 default:
840 reg |= 2 << 3;
841 break;
842 }
843
844 if (state->link)
845 reg |= RTL930X_FORCE_LINK_EN;
846
847 if (priv->lagmembers & BIT_ULL(port))
848 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
849
850 if (state->duplex == DUPLEX_FULL)
851 reg |= RTL930X_DUPLEX_MODE;
852
853 if (priv->ports[port].phy_is_integrated)
854 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
855 else
856 reg |= RTL930X_FORCE_EN;
857
858 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
859 }
860
861 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
862 unsigned int mode,
863 phy_interface_t interface)
864 {
865 struct rtl838x_switch_priv *priv = ds->priv;
866 u32 v;
867
868 /* Stop TX/RX to port */
869 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
870
871 // No longer force link
872 if (priv->family_id == RTL9300_FAMILY_ID)
873 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
874 else if (priv->family_id == RTL9310_FAMILY_ID)
875 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
876 sw_w32_mask(v, 0, priv->r->mac_port_ctrl(port));
877 }
878
879 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
880 unsigned int mode,
881 phy_interface_t interface)
882 {
883 struct rtl838x_switch_priv *priv = ds->priv;
884 /* Stop TX/RX to port */
885 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
886
887 // No longer force link
888 sw_w32_mask(3, 0, priv->r->mac_force_mode_ctrl(port));
889 }
890
891 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
892 unsigned int mode,
893 phy_interface_t interface,
894 struct phy_device *phydev,
895 int speed, int duplex,
896 bool tx_pause, bool rx_pause)
897 {
898 struct rtl838x_switch_priv *priv = ds->priv;
899 /* Restart TX/RX to port */
900 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
901 // TODO: Set speed/duplex/pauses
902 }
903
904 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
905 unsigned int mode,
906 phy_interface_t interface,
907 struct phy_device *phydev,
908 int speed, int duplex,
909 bool tx_pause, bool rx_pause)
910 {
911 struct rtl838x_switch_priv *priv = ds->priv;
912
913 /* Restart TX/RX to port */
914 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
915 // TODO: Set speed/duplex/pauses
916 }
917
918 static void rtl83xx_get_strings(struct dsa_switch *ds,
919 int port, u32 stringset, u8 *data)
920 {
921 int i;
922
923 if (stringset != ETH_SS_STATS)
924 return;
925
926 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
927 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
928 ETH_GSTRING_LEN);
929 }
930
931 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
932 uint64_t *data)
933 {
934 struct rtl838x_switch_priv *priv = ds->priv;
935 const struct rtl83xx_mib_desc *mib;
936 int i;
937 u64 h;
938
939 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
940 mib = &rtl83xx_mib[i];
941
942 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
943 if (mib->size == 2) {
944 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
945 data[i] |= h << 32;
946 }
947 }
948 }
949
950 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
951 {
952 if (sset != ETH_SS_STATS)
953 return 0;
954
955 return ARRAY_SIZE(rtl83xx_mib);
956 }
957
958 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
959 {
960 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
961 u64 portmask;
962
963 if (mc_group >= MAX_MC_GROUPS - 1)
964 return -1;
965
966 if (priv->is_lagmember[port]) {
967 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
968 return 0;
969 }
970
971 set_bit(mc_group, priv->mc_group_bm);
972 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
973 portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port);
974 priv->r->write_mcast_pmask(mc_group, portmask);
975
976 return mc_group;
977 }
978
979 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
980 {
981 u64 portmask = priv->r->read_mcast_pmask(mc_group);
982
983 pr_debug("%s: %d\n", __func__, port);
984 if (priv->is_lagmember[port]) {
985 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
986 return portmask;
987 }
988 portmask |= BIT_ULL(port);
989 priv->r->write_mcast_pmask(mc_group, portmask);
990
991 return portmask;
992 }
993
994 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
995 {
996 u64 portmask = priv->r->read_mcast_pmask(mc_group);
997
998 pr_debug("%s: %d\n", __func__, port);
999 if (priv->is_lagmember[port]) {
1000 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1001 return portmask;
1002 }
1003 priv->r->write_mcast_pmask(mc_group, portmask);
1004 if (portmask == BIT_ULL(priv->cpu_port)) {
1005 portmask &= ~BIT_ULL(priv->cpu_port);
1006 priv->r->write_mcast_pmask(mc_group, portmask);
1007 clear_bit(mc_group, priv->mc_group_bm);
1008 }
1009
1010 return portmask;
1011 }
1012
1013 static void store_mcgroups(struct rtl838x_switch_priv *priv, int port)
1014 {
1015 int mc_group;
1016
1017 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1018 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1019 if (portmask & BIT_ULL(port)) {
1020 priv->mc_group_saves[mc_group] = port;
1021 rtl83xx_mc_group_del_port(priv, mc_group, port);
1022 }
1023 }
1024 }
1025
1026 static void load_mcgroups(struct rtl838x_switch_priv *priv, int port)
1027 {
1028 int mc_group;
1029
1030 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1031 if (priv->mc_group_saves[mc_group] == port) {
1032 rtl83xx_mc_group_add_port(priv, mc_group, port);
1033 priv->mc_group_saves[mc_group] = -1;
1034 }
1035 }
1036 }
1037
1038 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1039 struct phy_device *phydev)
1040 {
1041 struct rtl838x_switch_priv *priv = ds->priv;
1042 u64 v;
1043
1044 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1045 priv->ports[port].enable = true;
1046
1047 /* enable inner tagging on egress, do not keep any tags */
1048 if (priv->family_id == RTL9310_FAMILY_ID)
1049 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
1050 else
1051 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
1052
1053 if (dsa_is_cpu_port(ds, port))
1054 return 0;
1055
1056 /* add port to switch mask of CPU_PORT */
1057 priv->r->traffic_enable(priv->cpu_port, port);
1058
1059 load_mcgroups(priv, port);
1060
1061 if (priv->is_lagmember[port]) {
1062 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1063 return 0;
1064 }
1065
1066 /* add all other ports in the same bridge to switch mask of port */
1067 v = priv->r->traffic_get(port);
1068 v |= priv->ports[port].pm;
1069 priv->r->traffic_set(port, v);
1070
1071 // TODO: Figure out if this is necessary
1072 if (priv->family_id == RTL9300_FAMILY_ID) {
1073 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1074 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1075 }
1076
1077 if (priv->ports[port].sds_num < 0)
1078 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1079
1080 return 0;
1081 }
1082
1083 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1084 {
1085 struct rtl838x_switch_priv *priv = ds->priv;
1086 u64 v;
1087
1088 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1089 /* you can only disable user ports */
1090 if (!dsa_is_user_port(ds, port))
1091 return;
1092
1093 // BUG: This does not work on RTL931X
1094 /* remove port from switch mask of CPU_PORT */
1095 priv->r->traffic_disable(priv->cpu_port, port);
1096 store_mcgroups(priv, port);
1097
1098 /* remove all other ports in the same bridge from switch mask of port */
1099 v = priv->r->traffic_get(port);
1100 v &= ~priv->ports[port].pm;
1101 priv->r->traffic_set(port, v);
1102
1103 priv->ports[port].enable = false;
1104 }
1105
1106 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1107 struct ethtool_eee *e)
1108 {
1109 struct rtl838x_switch_priv *priv = ds->priv;
1110
1111 if (e->eee_enabled && !priv->eee_enabled) {
1112 pr_info("Globally enabling EEE\n");
1113 priv->r->init_eee(priv, true);
1114 }
1115
1116 priv->r->port_eee_set(priv, port, e->eee_enabled);
1117
1118 if (e->eee_enabled)
1119 pr_info("Enabled EEE for port %d\n", port);
1120 else
1121 pr_info("Disabled EEE for port %d\n", port);
1122 return 0;
1123 }
1124
1125 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1126 struct ethtool_eee *e)
1127 {
1128 struct rtl838x_switch_priv *priv = ds->priv;
1129
1130 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1131
1132 priv->r->eee_port_ability(priv, e, port);
1133
1134 e->eee_enabled = priv->ports[port].eee_enabled;
1135
1136 e->eee_active = !!(e->advertised & e->lp_advertised);
1137
1138 return 0;
1139 }
1140
1141 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1142 struct ethtool_eee *e)
1143 {
1144 struct rtl838x_switch_priv *priv = ds->priv;
1145
1146 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
1147 | SUPPORTED_2500baseX_Full;
1148
1149 priv->r->eee_port_ability(priv, e, port);
1150
1151 e->eee_enabled = priv->ports[port].eee_enabled;
1152
1153 e->eee_active = !!(e->advertised & e->lp_advertised);
1154
1155 return 0;
1156 }
1157
1158 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1159 {
1160 struct rtl838x_switch_priv *priv = ds->priv;
1161
1162 priv->r->set_ageing_time(msec);
1163 return 0;
1164 }
1165
1166 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1167 struct net_device *bridge)
1168 {
1169 struct rtl838x_switch_priv *priv = ds->priv;
1170 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1171 int i;
1172
1173 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1174
1175 if (priv->is_lagmember[port]) {
1176 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1177 return 0;
1178 }
1179
1180 mutex_lock(&priv->reg_mutex);
1181 for (i = 0; i < ds->num_ports; i++) {
1182 /* Add this port to the port matrix of the other ports in the
1183 * same bridge. If the port is disabled, port matrix is kept
1184 * and not being setup until the port becomes enabled.
1185 */
1186 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1187 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1188 continue;
1189 if (priv->ports[i].enable)
1190 priv->r->traffic_enable(i, port);
1191
1192 priv->ports[i].pm |= BIT_ULL(port);
1193 port_bitmap |= BIT_ULL(i);
1194 }
1195 }
1196 load_mcgroups(priv, port);
1197
1198 /* Add all other ports to this port matrix. */
1199 if (priv->ports[port].enable) {
1200 priv->r->traffic_enable(priv->cpu_port, port);
1201 v = priv->r->traffic_get(port);
1202 v |= port_bitmap;
1203 priv->r->traffic_set(port, v);
1204 }
1205 priv->ports[port].pm |= port_bitmap;
1206 mutex_unlock(&priv->reg_mutex);
1207
1208 return 0;
1209 }
1210
1211 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1212 struct net_device *bridge)
1213 {
1214 struct rtl838x_switch_priv *priv = ds->priv;
1215 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1216 int i;
1217
1218 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1219 mutex_lock(&priv->reg_mutex);
1220 for (i = 0; i < ds->num_ports; i++) {
1221 /* Remove this port from the port matrix of the other ports
1222 * in the same bridge. If the port is disabled, port matrix
1223 * is kept and not being setup until the port becomes enabled.
1224 * And the other port's port matrix cannot be broken when the
1225 * other port is still a VLAN-aware port.
1226 */
1227 if (dsa_is_user_port(ds, i) && i != port) {
1228 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1229 continue;
1230 if (priv->ports[i].enable)
1231 priv->r->traffic_disable(i, port);
1232
1233 priv->ports[i].pm |= BIT_ULL(port);
1234 port_bitmap &= ~BIT_ULL(i);
1235 }
1236 }
1237 store_mcgroups(priv, port);
1238
1239 /* Add all other ports to this port matrix. */
1240 if (priv->ports[port].enable) {
1241 v = priv->r->traffic_get(port);
1242 v |= port_bitmap;
1243 priv->r->traffic_set(port, v);
1244 }
1245 priv->ports[port].pm &= ~port_bitmap;
1246
1247 mutex_unlock(&priv->reg_mutex);
1248 }
1249
1250 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1251 {
1252 u32 msti = 0;
1253 u32 port_state[4];
1254 int index, bit;
1255 int pos = port;
1256 struct rtl838x_switch_priv *priv = ds->priv;
1257 int n = priv->port_width << 1;
1258
1259 /* Ports above or equal CPU port can never be configured */
1260 if (port >= priv->cpu_port)
1261 return;
1262
1263 mutex_lock(&priv->reg_mutex);
1264
1265 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1266 * have 64 bit fields, 839x and 931x have 128 bit fields
1267 */
1268 if (priv->family_id == RTL8390_FAMILY_ID)
1269 pos += 12;
1270 if (priv->family_id == RTL9300_FAMILY_ID)
1271 pos += 3;
1272 if (priv->family_id == RTL9310_FAMILY_ID)
1273 pos += 8;
1274
1275 index = n - (pos >> 4) - 1;
1276 bit = (pos << 1) % 32;
1277
1278 priv->r->stp_get(priv, msti, port_state);
1279
1280 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1281 port_state[index] &= ~(3 << bit);
1282
1283 switch (state) {
1284 case BR_STATE_DISABLED: /* 0 */
1285 port_state[index] |= (0 << bit);
1286 break;
1287 case BR_STATE_BLOCKING: /* 4 */
1288 case BR_STATE_LISTENING: /* 1 */
1289 port_state[index] |= (1 << bit);
1290 break;
1291 case BR_STATE_LEARNING: /* 2 */
1292 port_state[index] |= (2 << bit);
1293 break;
1294 case BR_STATE_FORWARDING: /* 3*/
1295 port_state[index] |= (3 << bit);
1296 default:
1297 break;
1298 }
1299
1300 priv->r->stp_set(priv, msti, port_state);
1301
1302 mutex_unlock(&priv->reg_mutex);
1303 }
1304
1305 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1306 {
1307 struct rtl838x_switch_priv *priv = ds->priv;
1308 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1309
1310 pr_debug("FAST AGE port %d\n", port);
1311 mutex_lock(&priv->reg_mutex);
1312 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1313 * port fields:
1314 * 0-4: Replacing port
1315 * 5-9: Flushed/replaced port
1316 * 10-21: FVID
1317 * 22: Entry types: 1: dynamic, 0: also static
1318 * 23: Match flush port
1319 * 24: Match FVID
1320 * 25: Flush (0) or replace (1) L2 entries
1321 * 26: Status of action (1: Start, 0: Done)
1322 */
1323 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1324
1325 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1326
1327 mutex_unlock(&priv->reg_mutex);
1328 }
1329
1330 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1331 {
1332 struct rtl838x_switch_priv *priv = ds->priv;
1333
1334 pr_info("%s port %d\n", __func__, port);
1335 mutex_lock(&priv->reg_mutex);
1336 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1337
1338 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1339
1340 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1341
1342 mutex_unlock(&priv->reg_mutex);
1343 }
1344
1345 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1346 {
1347 struct rtl838x_switch_priv *priv = ds->priv;
1348
1349 if (priv->family_id == RTL9310_FAMILY_ID)
1350 return rtl931x_fast_age(ds, port);
1351
1352 pr_debug("FAST AGE port %d\n", port);
1353 mutex_lock(&priv->reg_mutex);
1354 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1355
1356 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1357
1358 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1359
1360 mutex_unlock(&priv->reg_mutex);
1361 }
1362
1363 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1364 bool vlan_filtering,
1365 struct switchdev_trans *trans)
1366 {
1367 struct rtl838x_switch_priv *priv = ds->priv;
1368
1369 pr_debug("%s: port %d\n", __func__, port);
1370 mutex_lock(&priv->reg_mutex);
1371
1372 if (vlan_filtering) {
1373 /* Enable ingress and egress filtering
1374 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1375 * the filter action:
1376 * 0: Always Forward
1377 * 1: Drop packet
1378 * 2: Trap packet to CPU port
1379 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1380 */
1381 if (port != priv->cpu_port)
1382 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1383
1384 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1385 } else {
1386 /* Disable ingress and egress filtering */
1387 if (port != priv->cpu_port)
1388 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1389
1390 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1391 }
1392
1393 /* Do we need to do something to the CPU-Port, too? */
1394 mutex_unlock(&priv->reg_mutex);
1395
1396 return 0;
1397 }
1398
1399 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1400 const struct switchdev_obj_port_vlan *vlan)
1401 {
1402 struct rtl838x_vlan_info info;
1403 struct rtl838x_switch_priv *priv = ds->priv;
1404
1405 priv->r->vlan_tables_read(0, &info);
1406
1407 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1408 info.tagged_ports, info.untagged_ports, info.profile_id,
1409 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1410
1411 priv->r->vlan_tables_read(1, &info);
1412 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1413 info.tagged_ports, info.untagged_ports, info.profile_id,
1414 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1415 priv->r->vlan_set_untagged(1, info.untagged_ports);
1416 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1417
1418 priv->r->vlan_set_tagged(1, &info);
1419 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1420
1421 return 0;
1422 }
1423
1424 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1425 const struct switchdev_obj_port_vlan *vlan)
1426 {
1427 struct rtl838x_vlan_info info;
1428 struct rtl838x_switch_priv *priv = ds->priv;
1429 int v;
1430
1431 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1432 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1433
1434 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1435 dev_err(priv->dev, "VLAN out of range: %d - %d",
1436 vlan->vid_begin, vlan->vid_end);
1437 return;
1438 }
1439
1440 mutex_lock(&priv->reg_mutex);
1441
1442 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1443 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1444 if (!v)
1445 continue;
1446 /* Set both inner and outer PVID of the port */
1447 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, v);
1448 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, v);
1449 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1450 PBVLAN_MODE_UNTAG_AND_PRITAG);
1451 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1452 PBVLAN_MODE_UNTAG_AND_PRITAG);
1453
1454 priv->ports[port].pvid = vlan->vid_end;
1455 }
1456 }
1457
1458 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1459 /* Get port memberships of this vlan */
1460 priv->r->vlan_tables_read(v, &info);
1461
1462 /* new VLAN? */
1463 if (!info.tagged_ports) {
1464 info.fid = 0;
1465 info.hash_mc_fid = false;
1466 info.hash_uc_fid = false;
1467 info.profile_id = 0;
1468 }
1469
1470 /* sanitize untagged_ports - must be a subset */
1471 if (info.untagged_ports & ~info.tagged_ports)
1472 info.untagged_ports = 0;
1473
1474 info.tagged_ports |= BIT_ULL(port);
1475 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1476 info.untagged_ports |= BIT_ULL(port);
1477
1478 priv->r->vlan_set_untagged(v, info.untagged_ports);
1479 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1480
1481 priv->r->vlan_set_tagged(v, &info);
1482 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1483 }
1484
1485 mutex_unlock(&priv->reg_mutex);
1486 }
1487
1488 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1489 const struct switchdev_obj_port_vlan *vlan)
1490 {
1491 struct rtl838x_vlan_info info;
1492 struct rtl838x_switch_priv *priv = ds->priv;
1493 int v;
1494 u16 pvid;
1495
1496 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1497 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1498
1499 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1500 dev_err(priv->dev, "VLAN out of range: %d - %d",
1501 vlan->vid_begin, vlan->vid_end);
1502 return -ENOTSUPP;
1503 }
1504
1505 mutex_lock(&priv->reg_mutex);
1506 pvid = priv->ports[port].pvid;
1507
1508 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1509 /* Reset to default if removing the current PVID */
1510 if (v == pvid) {
1511 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);
1512 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);
1513 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1514 PBVLAN_MODE_UNTAG_AND_PRITAG);
1515 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1516 PBVLAN_MODE_UNTAG_AND_PRITAG);
1517 }
1518 /* Get port memberships of this vlan */
1519 priv->r->vlan_tables_read(v, &info);
1520
1521 /* remove port from both tables */
1522 info.untagged_ports &= (~BIT_ULL(port));
1523 info.tagged_ports &= (~BIT_ULL(port));
1524
1525 priv->r->vlan_set_untagged(v, info.untagged_ports);
1526 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1527
1528 priv->r->vlan_set_tagged(v, &info);
1529 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1530 }
1531 mutex_unlock(&priv->reg_mutex);
1532
1533 return 0;
1534 }
1535
1536 static void dump_l2_entry(struct rtl838x_l2_entry *e)
1537 {
1538 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
1539 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
1540 e->vid, e->rvid, e->port, e->valid);
1541
1542 if (e->type != L2_MULTICAST) {
1543 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
1544 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
1545 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
1546 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
1547 }
1548 if (e->type == L2_MULTICAST)
1549 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
1550 if (e->is_ip_mc || e->is_ipv6_mc)
1551 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1552 e->mc_portmask_index, e->mc_gip, e->mc_sip);
1553 pr_info(" stack_dev: %d\n", e->stack_dev);
1554 if (e->next_hop)
1555 pr_info(" nh_route_id: %d\n", e->nh_route_id);
1556 }
1557
1558 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1559 {
1560 e->is_ip_mc = e->is_ipv6_mc = false;
1561 e->valid = true;
1562 e->age = 3;
1563 e->port = port,
1564 e->vid = vid;
1565 u64_to_ether_addr(mac, e->mac);
1566 }
1567
1568 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1569 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1570 {
1571 e->is_ip_mc = e->is_ipv6_mc = false;
1572 e->valid = true;
1573 e->mc_portmask_index = mc_group;
1574 e->type = L2_MULTICAST;
1575 e->rvid = e->vid = vid;
1576 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1577 u64_to_ether_addr(mac, e->mac);
1578 }
1579
1580 /*
1581 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1582 * over the entries in the bucket until either a matching entry is found or an empty slot
1583 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1584 * when an empty slot was found and must exist is false, the index of the slot is returned
1585 * when no slots are available returns -1
1586 */
1587 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1588 bool must_exist, struct rtl838x_l2_entry *e)
1589 {
1590 int i, idx = -1;
1591 u32 key = priv->r->l2_hash_key(priv, seed);
1592 u64 entry;
1593
1594 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1595 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1596 for (i = 0; i < priv->l2_bucket_size; i++) {
1597 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1598 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1599 if (must_exist && !e->valid)
1600 continue;
1601 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1602 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1603 break;
1604 }
1605 }
1606
1607 return idx;
1608 }
1609
1610 /*
1611 * Uses the seed to identify an entry in the CAM by looping over all its entries
1612 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1613 * when an empty slot was found the index of the slot is returned
1614 * when no slots are available returns -1
1615 */
1616 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1617 bool must_exist, struct rtl838x_l2_entry *e)
1618 {
1619 int i, idx = -1;
1620 u64 entry;
1621
1622 for (i = 0; i < 64; i++) {
1623 entry = priv->r->read_cam(i, e);
1624 if (!must_exist && !e->valid) {
1625 if (idx < 0) /* First empty entry? */
1626 idx = i;
1627 break;
1628 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1629 pr_debug("Found entry in CAM\n");
1630 idx = i;
1631 break;
1632 }
1633 }
1634 return idx;
1635 }
1636
1637 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1638 const unsigned char *addr, u16 vid)
1639 {
1640 struct rtl838x_switch_priv *priv = ds->priv;
1641 u64 mac = ether_addr_to_u64(addr);
1642 struct rtl838x_l2_entry e;
1643 int err = 0, idx;
1644 u64 seed = priv->r->l2_hash_seed(mac, vid);
1645
1646 if (priv->is_lagmember[port]) {
1647 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1648 return 0;
1649 }
1650
1651 mutex_lock(&priv->reg_mutex);
1652
1653 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1654
1655 // Found an existing or empty entry
1656 if (idx >= 0) {
1657 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1658 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1659 goto out;
1660 }
1661
1662 // Hash buckets full, try CAM
1663 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1664
1665 if (idx >= 0) {
1666 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1667 priv->r->write_cam(idx, &e);
1668 goto out;
1669 }
1670
1671 err = -ENOTSUPP;
1672 out:
1673 mutex_unlock(&priv->reg_mutex);
1674 return err;
1675 }
1676
1677 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1678 const unsigned char *addr, u16 vid)
1679 {
1680 struct rtl838x_switch_priv *priv = ds->priv;
1681 u64 mac = ether_addr_to_u64(addr);
1682 struct rtl838x_l2_entry e;
1683 int err = 0, idx;
1684 u64 seed = priv->r->l2_hash_seed(mac, vid);
1685
1686 pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1687 mutex_lock(&priv->reg_mutex);
1688
1689 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1690
1691 pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1692 if (idx >= 0) {
1693 e.valid = false;
1694 dump_l2_entry(&e);
1695 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1696 goto out;
1697 }
1698
1699 /* Check CAM for spillover from hash buckets */
1700 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1701
1702 if (idx >= 0) {
1703 e.valid = false;
1704 priv->r->write_cam(idx, &e);
1705 goto out;
1706 }
1707 err = -ENOENT;
1708 out:
1709 mutex_unlock(&priv->reg_mutex);
1710 return err;
1711 }
1712
1713 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1714 dsa_fdb_dump_cb_t *cb, void *data)
1715 {
1716 struct rtl838x_l2_entry e;
1717 struct rtl838x_switch_priv *priv = ds->priv;
1718 int i;
1719 u32 fid, pkey;
1720 u64 mac;
1721
1722 mutex_lock(&priv->reg_mutex);
1723
1724 for (i = 0; i < priv->fib_entries; i++) {
1725 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1726
1727 if (!e.valid)
1728 continue;
1729
1730 if (e.port == port || e.port == RTL930X_PORT_IGNORE) {
1731 u64 seed;
1732 u32 key;
1733
1734 fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
1735 mac = ether_addr_to_u64(&e.mac[0]);
1736 pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
1737 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1738 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1739 i, i >> 2, i & 0x3, mac, fid, e.rvid);
1740 dump_l2_entry(&e);
1741 seed = priv->r->l2_hash_seed(mac, e.rvid);
1742 key = priv->r->l2_hash_key(priv, seed);
1743 pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
1744 cb(e.mac, e.vid, e.is_static, data);
1745 }
1746 if (e.type == L2_MULTICAST) {
1747 u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
1748
1749 if (portmask & BIT_ULL(port)) {
1750 dump_l2_entry(&e);
1751 pr_info(" PM: %016llx\n", portmask);
1752 }
1753 }
1754 }
1755
1756 for (i = 0; i < 64; i++) {
1757 priv->r->read_cam(i, &e);
1758
1759 if (!e.valid)
1760 continue;
1761
1762 if (e.port == port)
1763 cb(e.mac, e.vid, e.is_static, data);
1764 }
1765
1766 mutex_unlock(&priv->reg_mutex);
1767 return 0;
1768 }
1769
1770 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1771 const struct switchdev_obj_port_mdb *mdb)
1772 {
1773 struct rtl838x_switch_priv *priv = ds->priv;
1774
1775 if (priv->id >= 0x9300)
1776 return -EOPNOTSUPP;
1777
1778 return 0;
1779 }
1780
1781 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1782 const struct switchdev_obj_port_mdb *mdb)
1783 {
1784 struct rtl838x_switch_priv *priv = ds->priv;
1785 u64 mac = ether_addr_to_u64(mdb->addr);
1786 struct rtl838x_l2_entry e;
1787 int err = 0, idx;
1788 int vid = mdb->vid;
1789 u64 seed = priv->r->l2_hash_seed(mac, vid);
1790 int mc_group;
1791
1792 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1793
1794 if (priv->is_lagmember[port]) {
1795 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1796 return;
1797 }
1798
1799 mutex_lock(&priv->reg_mutex);
1800
1801 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1802
1803 // Found an existing or empty entry
1804 if (idx >= 0) {
1805 if (e.valid) {
1806 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1807 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1808 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1809 } else {
1810 pr_debug("New entry for seed %016llx\n", seed);
1811 mc_group = rtl83xx_mc_group_alloc(priv, port);
1812 if (mc_group < 0) {
1813 err = -ENOTSUPP;
1814 goto out;
1815 }
1816 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1817 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1818 }
1819 goto out;
1820 }
1821
1822 // Hash buckets full, try CAM
1823 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1824
1825 if (idx >= 0) {
1826 if (e.valid) {
1827 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1828 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1829 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1830 } else {
1831 pr_debug("New entry\n");
1832 mc_group = rtl83xx_mc_group_alloc(priv, port);
1833 if (mc_group < 0) {
1834 err = -ENOTSUPP;
1835 goto out;
1836 }
1837 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1838 priv->r->write_cam(idx, &e);
1839 }
1840 goto out;
1841 }
1842
1843 err = -ENOTSUPP;
1844 out:
1845 mutex_unlock(&priv->reg_mutex);
1846 if (err)
1847 dev_err(ds->dev, "failed to add MDB entry\n");
1848 }
1849
1850 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1851 const struct switchdev_obj_port_mdb *mdb)
1852 {
1853 struct rtl838x_switch_priv *priv = ds->priv;
1854 u64 mac = ether_addr_to_u64(mdb->addr);
1855 struct rtl838x_l2_entry e;
1856 int err = 0, idx;
1857 int vid = mdb->vid;
1858 u64 seed = priv->r->l2_hash_seed(mac, vid);
1859 u64 portmask;
1860
1861 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1862
1863 if (priv->is_lagmember[port]) {
1864 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1865 return 0;
1866 }
1867
1868 mutex_lock(&priv->reg_mutex);
1869
1870 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1871
1872 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1873 if (idx >= 0) {
1874 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1875 if (!portmask) {
1876 e.valid = false;
1877 // dump_l2_entry(&e);
1878 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1879 }
1880 goto out;
1881 }
1882
1883 /* Check CAM for spillover from hash buckets */
1884 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1885
1886 if (idx >= 0) {
1887 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1888 if (!portmask) {
1889 e.valid = false;
1890 // dump_l2_entry(&e);
1891 priv->r->write_cam(idx, &e);
1892 }
1893 goto out;
1894 }
1895 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1896 out:
1897 mutex_unlock(&priv->reg_mutex);
1898 return err;
1899 }
1900
1901 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1902 struct dsa_mall_mirror_tc_entry *mirror,
1903 bool ingress)
1904 {
1905 /* We support 4 mirror groups, one destination port per group */
1906 int group;
1907 struct rtl838x_switch_priv *priv = ds->priv;
1908 int ctrl_reg, dpm_reg, spm_reg;
1909
1910 pr_debug("In %s\n", __func__);
1911
1912 for (group = 0; group < 4; group++) {
1913 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1914 break;
1915 }
1916 if (group >= 4) {
1917 for (group = 0; group < 4; group++) {
1918 if (priv->mirror_group_ports[group] < 0)
1919 break;
1920 }
1921 }
1922
1923 if (group >= 4)
1924 return -ENOSPC;
1925
1926 ctrl_reg = priv->r->mir_ctrl + group * 4;
1927 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1928 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1929
1930 pr_debug("Using group %d\n", group);
1931 mutex_lock(&priv->reg_mutex);
1932
1933 if (priv->family_id == RTL8380_FAMILY_ID) {
1934 /* Enable mirroring to port across VLANs (bit 11) */
1935 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1936 } else {
1937 /* Enable mirroring to destination port */
1938 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1939 }
1940
1941 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1942 mutex_unlock(&priv->reg_mutex);
1943 return -EEXIST;
1944 }
1945 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1946 mutex_unlock(&priv->reg_mutex);
1947 return -EEXIST;
1948 }
1949
1950 if (ingress)
1951 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1952 else
1953 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1954
1955 priv->mirror_group_ports[group] = mirror->to_local_port;
1956 mutex_unlock(&priv->reg_mutex);
1957 return 0;
1958 }
1959
1960 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1961 struct dsa_mall_mirror_tc_entry *mirror)
1962 {
1963 int group = 0;
1964 struct rtl838x_switch_priv *priv = ds->priv;
1965 int ctrl_reg, dpm_reg, spm_reg;
1966
1967 pr_debug("In %s\n", __func__);
1968 for (group = 0; group < 4; group++) {
1969 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1970 break;
1971 }
1972 if (group >= 4)
1973 return;
1974
1975 ctrl_reg = priv->r->mir_ctrl + group * 4;
1976 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1977 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1978
1979 mutex_lock(&priv->reg_mutex);
1980 if (mirror->ingress) {
1981 /* Ingress, clear source port matrix */
1982 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1983 } else {
1984 /* Egress, clear destination port matrix */
1985 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1986 }
1987
1988 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1989 priv->mirror_group_ports[group] = -1;
1990 sw_w32(0, ctrl_reg);
1991 }
1992
1993 mutex_unlock(&priv->reg_mutex);
1994 }
1995
1996 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1997 {
1998 struct rtl838x_switch_priv *priv = ds->priv;
1999 unsigned long features = 0;
2000 pr_debug("%s: %d %lX\n", __func__, port, flags);
2001 if (priv->r->enable_learning)
2002 features |= BR_LEARNING;
2003 if (priv->r->enable_flood)
2004 features |= BR_FLOOD;
2005 if (priv->r->enable_mcast_flood)
2006 features |= BR_MCAST_FLOOD;
2007 if (priv->r->enable_bcast_flood)
2008 features |= BR_BCAST_FLOOD;
2009 if (flags & ~(features))
2010 return -EINVAL;
2011
2012 return 0;
2013 }
2014
2015 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
2016 {
2017 struct rtl838x_switch_priv *priv = ds->priv;
2018
2019 pr_debug("%s: %d %lX\n", __func__, port, flags);
2020 if (priv->r->enable_learning)
2021 priv->r->enable_learning(port, !!(flags & BR_LEARNING));
2022
2023 if (priv->r->enable_flood)
2024 priv->r->enable_flood(port, !!(flags & BR_FLOOD));
2025
2026 if (priv->r->enable_mcast_flood)
2027 priv->r->enable_mcast_flood(port, !!(flags & BR_MCAST_FLOOD));
2028
2029 if (priv->r->enable_bcast_flood)
2030 priv->r->enable_bcast_flood(port, !!(flags & BR_BCAST_FLOOD));
2031
2032 return 0;
2033 }
2034
2035 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
2036 struct net_device *lag,
2037 struct netdev_lag_upper_info *info)
2038 {
2039 int id;
2040
2041 id = dsa_lag_id(ds->dst, lag);
2042 if (id < 0 || id >= ds->num_lag_ids)
2043 return false;
2044
2045 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2046 return false;
2047 }
2048 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2049 return false;
2050
2051 return true;
2052 }
2053
2054 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2055 {
2056 struct rtl838x_switch_priv *priv = ds->priv;
2057
2058 pr_debug("%s: %d\n", __func__, port);
2059 // Nothing to be done...
2060
2061 return 0;
2062 }
2063
2064 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2065 struct net_device *lag,
2066 struct netdev_lag_upper_info *info)
2067 {
2068 struct rtl838x_switch_priv *priv = ds->priv;
2069 int i, err = 0;
2070
2071 if (!rtl83xx_lag_can_offload(ds, lag, info))
2072 return -EOPNOTSUPP;
2073
2074 mutex_lock(&priv->reg_mutex);
2075
2076 for (i = 0; i < priv->n_lags; i++) {
2077 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2078 break;
2079 }
2080 if (port >= priv->cpu_port) {
2081 err = -EINVAL;
2082 goto out;
2083 }
2084 pr_info("port_lag_join: group %d, port %d\n",i, port);
2085 if (!priv->lag_devs[i])
2086 priv->lag_devs[i] = lag;
2087
2088 if (priv->lag_primary[i]==-1) {
2089 priv->lag_primary[i]=port;
2090 } else
2091 priv->is_lagmember[port] = 1;
2092
2093 priv->lagmembers |= (1ULL << port);
2094
2095 pr_debug("lag_members = %llX\n", priv->lagmembers);
2096 err = rtl83xx_lag_add(priv->ds, i, port, info);
2097 if (err) {
2098 err = -EINVAL;
2099 goto out;
2100 }
2101
2102 out:
2103 mutex_unlock(&priv->reg_mutex);
2104 return err;
2105
2106 }
2107
2108 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2109 struct net_device *lag)
2110 {
2111 int i, group = -1, err;
2112 struct rtl838x_switch_priv *priv = ds->priv;
2113
2114 mutex_lock(&priv->reg_mutex);
2115 for (i=0;i<priv->n_lags;i++) {
2116 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2117 group = i;
2118 break;
2119 }
2120 }
2121
2122 if (group == -1) {
2123 pr_info("port_lag_leave: port %d is not a member\n", port);
2124 err = -EINVAL;
2125 goto out;
2126 }
2127
2128 if (port >= priv->cpu_port) {
2129 err = -EINVAL;
2130 goto out;
2131 }
2132 pr_info("port_lag_del: group %d, port %d\n",group, port);
2133 priv->lagmembers &=~ (1ULL << port);
2134 priv->lag_primary[i] = -1;
2135 priv->is_lagmember[port] = 0;
2136 pr_debug("lag_members = %llX\n", priv->lagmembers);
2137 err = rtl83xx_lag_del(priv->ds, group, port);
2138 if (err) {
2139 err = -EINVAL;
2140 goto out;
2141 }
2142 if (!priv->lags_port_members[i])
2143 priv->lag_devs[i] = NULL;
2144
2145 out:
2146 mutex_unlock(&priv->reg_mutex);
2147 return 0;
2148 }
2149
2150 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2151 {
2152 u32 val;
2153 u32 offset = 0;
2154 struct rtl838x_switch_priv *priv = ds->priv;
2155
2156 if (phy_addr >= 24 && phy_addr <= 27
2157 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2158 if (phy_addr == 26)
2159 offset = 0x100;
2160 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2161 return val;
2162 }
2163
2164 read_phy(phy_addr, 0, phy_reg, &val);
2165 return val;
2166 }
2167
2168 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2169 {
2170 u32 offset = 0;
2171 struct rtl838x_switch_priv *priv = ds->priv;
2172
2173 if (phy_addr >= 24 && phy_addr <= 27
2174 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2175 if (phy_addr == 26)
2176 offset = 0x100;
2177 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2178 return 0;
2179 }
2180 return write_phy(phy_addr, 0, phy_reg, val);
2181 }
2182
2183 const struct dsa_switch_ops rtl83xx_switch_ops = {
2184 .get_tag_protocol = rtl83xx_get_tag_protocol,
2185 .setup = rtl83xx_setup,
2186
2187 .phy_read = dsa_phy_read,
2188 .phy_write = dsa_phy_write,
2189
2190 .phylink_validate = rtl83xx_phylink_validate,
2191 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2192 .phylink_mac_config = rtl83xx_phylink_mac_config,
2193 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2194 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2195
2196 .get_strings = rtl83xx_get_strings,
2197 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2198 .get_sset_count = rtl83xx_get_sset_count,
2199
2200 .port_enable = rtl83xx_port_enable,
2201 .port_disable = rtl83xx_port_disable,
2202
2203 .get_mac_eee = rtl83xx_get_mac_eee,
2204 .set_mac_eee = rtl83xx_set_mac_eee,
2205
2206 .set_ageing_time = rtl83xx_set_ageing_time,
2207 .port_bridge_join = rtl83xx_port_bridge_join,
2208 .port_bridge_leave = rtl83xx_port_bridge_leave,
2209 .port_stp_state_set = rtl83xx_port_stp_state_set,
2210 .port_fast_age = rtl83xx_fast_age,
2211
2212 .port_vlan_filtering = rtl83xx_vlan_filtering,
2213 .port_vlan_prepare = rtl83xx_vlan_prepare,
2214 .port_vlan_add = rtl83xx_vlan_add,
2215 .port_vlan_del = rtl83xx_vlan_del,
2216
2217 .port_fdb_add = rtl83xx_port_fdb_add,
2218 .port_fdb_del = rtl83xx_port_fdb_del,
2219 .port_fdb_dump = rtl83xx_port_fdb_dump,
2220
2221 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2222 .port_mdb_add = rtl83xx_port_mdb_add,
2223 .port_mdb_del = rtl83xx_port_mdb_del,
2224
2225 .port_mirror_add = rtl83xx_port_mirror_add,
2226 .port_mirror_del = rtl83xx_port_mirror_del,
2227
2228 .port_lag_change = rtl83xx_port_lag_change,
2229 .port_lag_join = rtl83xx_port_lag_join,
2230 .port_lag_leave = rtl83xx_port_lag_leave,
2231
2232 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2233 .port_bridge_flags = rtl83xx_port_bridge_flags,
2234 };
2235
2236 const struct dsa_switch_ops rtl930x_switch_ops = {
2237 .get_tag_protocol = rtl83xx_get_tag_protocol,
2238 .setup = rtl93xx_setup,
2239
2240 .phy_read = dsa_phy_read,
2241 .phy_write = dsa_phy_write,
2242
2243 .phylink_validate = rtl93xx_phylink_validate,
2244 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2245 .phylink_mac_config = rtl93xx_phylink_mac_config,
2246 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2247 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2248
2249 .get_strings = rtl83xx_get_strings,
2250 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2251 .get_sset_count = rtl83xx_get_sset_count,
2252
2253 .port_enable = rtl83xx_port_enable,
2254 .port_disable = rtl83xx_port_disable,
2255
2256 .get_mac_eee = rtl93xx_get_mac_eee,
2257 .set_mac_eee = rtl83xx_set_mac_eee,
2258
2259 .set_ageing_time = rtl83xx_set_ageing_time,
2260 .port_bridge_join = rtl83xx_port_bridge_join,
2261 .port_bridge_leave = rtl83xx_port_bridge_leave,
2262 .port_stp_state_set = rtl83xx_port_stp_state_set,
2263 .port_fast_age = rtl930x_fast_age,
2264
2265 .port_vlan_filtering = rtl83xx_vlan_filtering,
2266 .port_vlan_prepare = rtl83xx_vlan_prepare,
2267 .port_vlan_add = rtl83xx_vlan_add,
2268 .port_vlan_del = rtl83xx_vlan_del,
2269
2270 .port_fdb_add = rtl83xx_port_fdb_add,
2271 .port_fdb_del = rtl83xx_port_fdb_del,
2272 .port_fdb_dump = rtl83xx_port_fdb_dump,
2273
2274 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2275 .port_mdb_add = rtl83xx_port_mdb_add,
2276 .port_mdb_del = rtl83xx_port_mdb_del,
2277
2278 .port_lag_change = rtl83xx_port_lag_change,
2279 .port_lag_join = rtl83xx_port_lag_join,
2280 .port_lag_leave = rtl83xx_port_lag_leave,
2281
2282 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2283 .port_bridge_flags = rtl83xx_port_bridge_flags,
2284 };
Staging tree of Christian Lamparter