starfive: enable pcie0/1 on MarsV riscv-mars-202403
authorZoltan HERPAI <wigyori@uid0.hu>
Sun, 17 Mar 2024 22:37:38 +0000 (23:37 +0100)
committerZoltan HERPAI <wigyori@uid0.hu>
Mon, 18 Mar 2024 08:24:58 +0000 (09:24 +0100)
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
target/linux/starfive/patches-6.1/1102-enable-pcie-on-marsv.patch [new file with mode: 0644]

diff --git a/target/linux/starfive/patches-6.1/1102-enable-pcie-on-marsv.patch b/target/linux/starfive/patches-6.1/1102-enable-pcie-on-marsv.patch
new file mode 100644 (file)
index 0000000..d8720e8
--- /dev/null
@@ -0,0 +1,77 @@
+--- linux-6.1.81/arch/riscv/boot/dts/starfive/jh7110-visionfive2-mars-common.dtsi      2024-03-17 23:09:19.579452786 +0100
++++ linux-6.1.81/arch/riscv/boot/dts/starfive.new/jh7110-visionfive2-mars-common.dtsi  2024-03-16 19:00:10.382139562 +0100
+@@ -210,6 +210,21 @@
+       status = "okay";
+ };
++&pcie0 {
++      pinctrl-names = "default";
++      reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
++      phys = <&pciephy0>;
++      status = "okay";
++};
++
++&pcie1 {
++      pinctrl-names = "default";
++      reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
++      phys = <&pciephy1>;
++      status = "okay";
++};
++
++
+ &qspi {
+       #address-cells = <1>;
+       #size-cells = <0>;
+@@ -401,6 +416,52 @@
+                       slew-rate = <0>;
+               };
+       };
++
++      pcie0_wake_default: pcie0_wake_default {
++              wake-pins {
++                      pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
++                      bias-disable;
++                      drive-strength = <2>;
++                      input-enable;
++                      input-schmitt-disable;
++                      slew-rate = <0>;
++              };
++      };
++
++      pcie0_clkreq_default: pcie0_clkreq_default {
++              clkreq-pins {
++                      bias-disable;
++                      pinmux = <GPIOMUX(27, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
++                      drive-strength = <2>;
++                      input-enable;
++                      input-schmitt-disable;
++                      slew-rate = <0>;
++              };
++      };
++
++      pcie1_wake_default: pcie1_wake_default {
++              wake-pins {
++                      bias-disable;
++                      pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
++                      drive-strength = <2>;
++                      input-enable;
++                      input-schmitt-disable;
++                      slew-rate = <0>;
++              };
++      };
++
++      pcie1_clkreq_default: pcie1_clkreq_default {
++              clkreq-pins {
++                      bias-disable;
++                      pinmux = <GPIOMUX(29, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
++                      drive-strength = <2>;
++                      input-enable;
++                      input-schmitt-disable;
++                      slew-rate = <0>;
++              };
++      };
++
++
+ };
+ &uart0 {