1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
6 #include "mt7986a.dtsi"
11 label-mac-device = &gmac0;
12 led-boot = &led_status_green;
13 led-failsafe = &led_status_red;
14 led-running = &led_status_green;
15 led-upgrade = &led_status_red;
19 stdout-path = "serial0:115200n8";
23 reg = <0 0x40000000 0 0x20000000>;
26 reg_3p3v: regulator-3p3v {
27 compatible = "regulator-fixed";
28 regulator-name = "fixed-3.3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
35 reg_5v: regulator-5v {
36 compatible = "regulator-fixed";
37 regulator-name = "fixed-5V";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
45 compatible = "gpio-keys";
49 linux,code = <KEY_RESTART>;
50 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
55 linux,code = <KEY_WPS_BUTTON>;
56 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
62 gpios = <&pio 11 GPIO_ACTIVE_LOW>;
67 compatible = "gpio-leds";
69 led_status_red: status_red {
71 gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
74 led_status_green: status_green {
75 label = "green:status";
76 gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
80 label = "green:turbo";
81 gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
94 compatible = "mediatek,eth-mac";
96 phy-mode = "2500base-x";
98 nvmem-cells = <&macaddr_config_1c>;
99 nvmem-cell-names = "mac-address";
109 compatible = "mediatek,eth-mac";
111 phy-handle = <&phy7>;
112 phy-mode = "2500base-x";
114 nvmem-cells = <&macaddr_config_1c>;
115 nvmem-cell-names = "mac-address";
116 mac-address-increment = <1>;
120 #address-cells = <1>;
126 phy5: ethernet-phy@5 {
127 compatible = "ethernet-phy-ieee802.3-c45";
129 reset-assert-us = <100000>;
130 reset-deassert-us = <100000>;
131 reset-gpios = <&pio 13 GPIO_ACTIVE_LOW>;
132 realtek,aldps-enable;
135 phy7: ethernet-phy@7 {
136 compatible = "ethernet-phy-ieee802.3-c45";
138 reset-assert-us = <100000>;
139 reset-deassert-us = <100000>;
140 reset-gpios = <&pio 17 GPIO_ACTIVE_LOW>;
141 realtek,aldps-enable;
145 compatible = "mediatek,mt7531";
147 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
148 interrupt-controller;
149 #interrupt-cells = <1>;
150 interrupt-parent = <&pio>;
151 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&spi_flash_pins>;
161 compatible = "spi-nand";
162 #address-cells = <1>;
166 spi-max-frequency = <20000000>;
167 spi-tx-bus-width = <4>;
168 spi-rx-bus-width = <4>;
171 compatible = "fixed-partitions";
172 #address-cells = <1>;
177 reg = <0x000000 0x0100000>;
181 config: partition@100000 {
183 reg = <0x100000 0x0060000>;
187 compatible = "fixed-layout";
188 #address-cells = <1>;
191 macaddr_config_1c: macaddr@1c {
197 factory: partition@160000 {
199 reg = <0x160000 0x0060000>;
205 reg = <0x1c0000 0x01c0000>;
211 reg = <0x380000 0x0200000>;
217 reg = <0x580000 0x7800000>;
224 spi_flash_pins: spi-flash-pins-33-to-38 {
227 groups = "spi0", "spi0_wp_hold";
230 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
231 drive-strength = <8>;
232 mediatek,pull-up-adv = <0>; /* bias-disable */
235 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
236 drive-strength = <8>;
237 mediatek,pull-down-adv = <0>; /* bias-disable */
243 vusb33-supply = <®_3p3v>;
244 vbus-supply = <®_5v>;
265 mediatek,mtd-eeprom = <&factory 0x0>;
266 nvmem-cells = <&macaddr_config_1c>;
267 nvmem-cell-names = "mac-address";
268 mac-address-increment = <2>;