ath79: qca: convert to nvmem-layout

[openwrt/staging/hauke.git] / target / linux / ath79 / dts / qca9563_glinet_gl-x1200.dtsi

diff --git a/target/linux/ath79/dts/qca9563_glinet_gl-x1200.dtsi b/target/linux/ath79/dts/qca9563_glinet_gl-x1200.dtsi
index 8980f772e7459c8efdc317f7f5994fa0343f5ed6..ab1f8902b10a0f4ddc14faf1393edc2dd63674bc 100644 (file)
--- a/target/linux/ath79/dts/qca9563_glinet_gl-x1200.dtsi
+++ b/target/linux/ath79/dts/qca9563_glinet_gl-x1200.dtsi
@@ -95,28 +95,30 @@
                                reg = <0x050000 0x010000>;
                                read-only;
 
-                               compatible = "nvmem-cells";
-                               #address-cells = <1>;
-                               #size-cells = <1>;
-
-                               calibration_ath9k: calibration@1000 {
-                                       reg = <0x1000 0x440>;
-                               };
-
-                               calibration_ath10k: calibration@5000 {
-                                       reg = <0x5000 0x2f20>;
-                               };
-
-                               macaddr_art_0: macaddr@0 {
-                                       reg = <0x0 0x6>;
-                               };
-
-                               macaddr_art_1002: macaddr@1002 {
-                                       reg = <0x1002 0x6>;
-                               };
-
-                               macaddr_art_5006: macaddr@5006 {
-                                       reg = <0x5006 0x6>;
+                               nvmem-layout {
+                                       compatible = "fixed-layout";
+                                       #address-cells = <1>;
+                                       #size-cells = <1>;
+
+                                       calibration_ath9k: calibration@1000 {
+                                               reg = <0x1000 0x440>;
+                                       };
+
+                                       calibration_ath10k: calibration@5000 {
+                                               reg = <0x5000 0x2f20>;
+                                       };
+
+                                       macaddr_art_0: macaddr@0 {
+                                               reg = <0x0 0x6>;
+                                       };
+
+                                       macaddr_art_1002: macaddr@1002 {
+                                               reg = <0x1002 0x6>;
+                                       };
+
+                                       macaddr_art_5006: macaddr@5006 {
+                                               reg = <0x5006 0x6>;
+                                       };
                                };
                        };