1 From 944b96d734199642e2ede978c48d754109ca334c Mon Sep 17 00:00:00 2001
2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
3 Date: Mon, 20 Mar 2023 21:54:31 +0800
4 Subject: [PATCH 059/122] dt-bindings: timer: Add timer for StarFive JH7110 SoC
6 Add bindings for the timer on the JH7110 RISC-V SoC
7 by StarFive Technology Ltd.
9 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
10 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12 .../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++++++++++++++++
13 1 file changed, 95 insertions(+)
14 create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
17 +++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
19 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
22 +$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml#
23 +$schema: http://devicetree.org/meta-schemas/core.yaml#
25 +title: StarFive JH7110 Timer
27 + - Xingyu Wu <xingyu.wu@starfivetech.com>
28 + - Samin Guo <samin.guo@starfivetech.com>
31 + This timer has four free-running 32 bit counters in StarFive JH7110 SoC.
32 + And each channel(counter) triggers an interrupt when timeout. They support
33 + one-shot mode and continuous-run mode.
37 + const: starfive,jh7110-timer
44 + - description: channel 0
45 + - description: channel 1
46 + - description: channel 2
47 + - description: channel 3
51 + - description: timer APB
52 + - description: channel 0
53 + - description: channel 1
54 + - description: channel 2
55 + - description: channel 3
67 + - description: timer APB
68 + - description: channel 0
69 + - description: channel 1
70 + - description: channel 2
71 + - description: channel 3
90 +additionalProperties: false
95 + compatible = "starfive,jh7110-timer";
96 + reg = <0x13050000 0x10000>;
97 + interrupts = <69>, <70>, <71> ,<72>;
98 + clocks = <&clk 124>,
103 + clock-names = "apb", "ch0", "ch1",
105 + resets = <&rst 117>,
110 + reset-names = "apb", "ch0", "ch1",