target/linux/starfive/patches-6.1/0056-clk-starfive-Add-StarFive-JH7110-Video-Output-clock-.patch

   1 From 2e632d5c5f8b4577ac823f6a9dcf3eacdb14a0ba Mon Sep 17 00:00:00 2001
   2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
   3 Date: Thu, 18 May 2023 18:12:29 +0800
   4 Subject: [PATCH 056/122] clk: starfive: Add StarFive JH7110 Video-Output clock
   5  driver
   6
   7 Add driver for the StarFive JH7110 Video-Output clock controller.
   8 And these clock controllers should power on and enable the clocks from
   9 SYSCRG first before registering.
  10
  11 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
  12 ---
  13  drivers/clk/starfive/Kconfig                  |  11 +
  14  drivers/clk/starfive/Makefile                 |   1 +
  15  .../clk/starfive/clk-starfive-jh7110-vout.c   | 239 ++++++++++++++++++
  16  3 files changed, 251 insertions(+)
  17  create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-vout.c
  18
  19 --- a/drivers/clk/starfive/Kconfig
  20 +++ b/drivers/clk/starfive/Kconfig
  21 @@ -73,3 +73,14 @@ config CLK_STARFIVE_JH7110_ISP
  22         help
  23           Say yes here to support the Image-Signal-Process clock controller
  24           on the StarFive JH7110 SoC.
  25 +
  26 +config CLK_STARFIVE_JH7110_VOUT
  27 +       tristate "StarFive JH7110 Video-Output clock support"
  28 +       depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU
  29 +       select AUXILIARY_BUS
  30 +       select CLK_STARFIVE_JH71X0
  31 +       select RESET_STARFIVE_JH7110
  32 +       default m if ARCH_STARFIVE
  33 +       help
  34 +         Say yes here to support the Video-Output clock controller
  35 +         on the StarFive JH7110 SoC.
  36 --- a/drivers/clk/starfive/Makefile
  37 +++ b/drivers/clk/starfive/Makefile
  38 @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS)   +=
  39  obj-$(CONFIG_CLK_STARFIVE_JH7110_AON)  += clk-starfive-jh7110-aon.o
  40  obj-$(CONFIG_CLK_STARFIVE_JH7110_STG)  += clk-starfive-jh7110-stg.o
  41  obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP)  += clk-starfive-jh7110-isp.o
  42 +obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
  43 --- /dev/null
  44 +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
  45 @@ -0,0 +1,239 @@
  46 +// SPDX-License-Identifier: GPL-2.0
  47 +/*
  48 + * StarFive JH7110 Video-Output Clock Driver
  49 + *
  50 + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  51 + */
  52 +
  53 +#include <linux/clk.h>
  54 +#include <linux/clk-provider.h>
  55 +#include <linux/io.h>
  56 +#include <linux/platform_device.h>
  57 +#include <linux/pm_runtime.h>
  58 +#include <linux/reset.h>
  59 +
  60 +#include <dt-bindings/clock/starfive,jh7110-crg.h>
  61 +
  62 +#include "clk-starfive-jh7110.h"
  63 +
  64 +/* external clocks */
  65 +#define JH7110_VOUTCLK_VOUT_SRC                        (JH7110_VOUTCLK_END + 0)
  66 +#define JH7110_VOUTCLK_VOUT_TOP_AHB            (JH7110_VOUTCLK_END + 1)
  67 +#define JH7110_VOUTCLK_VOUT_TOP_AXI            (JH7110_VOUTCLK_END + 2)
  68 +#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK   (JH7110_VOUTCLK_END + 3)
  69 +#define JH7110_VOUTCLK_I2STX0_BCLK             (JH7110_VOUTCLK_END + 4)
  70 +#define JH7110_VOUTCLK_HDMITX0_PIXELCLK                (JH7110_VOUTCLK_END + 5)
  71 +#define JH7110_VOUTCLK_EXT_END                 (JH7110_VOUTCLK_END + 6)
  72 +
  73 +static struct clk_bulk_data jh7110_vout_top_clks[] = {
  74 +       { .id = "vout_src" },
  75 +       { .id = "vout_top_ahb" }
  76 +};
  77 +
  78 +static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
  79 +       /* divider */
  80 +       JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
  81 +       JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
  82 +       JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
  83 +       JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
  84 +       /* dc8200 */
  85 +       JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
  86 +       JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
  87 +       JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
  88 +       JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
  89 +                   JH7110_VOUTCLK_DC8200_PIX,
  90 +                   JH7110_VOUTCLK_HDMITX0_PIXELCLK),
  91 +       JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
  92 +                   JH7110_VOUTCLK_DC8200_PIX,
  93 +                   JH7110_VOUTCLK_HDMITX0_PIXELCLK),
  94 +       /* LCD */
  95 +       JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
  96 +                   JH7110_VOUTCLK_DC8200_PIX0,
  97 +                   JH7110_VOUTCLK_DC8200_PIX1),
  98 +       /* dsiTx */
  99 +       JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
 100 +       JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
 101 +       JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
 102 +                   JH7110_VOUTCLK_DC8200_PIX,
 103 +                   JH7110_VOUTCLK_HDMITX0_PIXELCLK),
 104 +       JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
 105 +       /* mipitx DPHY */
 106 +       JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
 107 +                   JH7110_VOUTCLK_TX_ESC),
 108 +       /* hdmi */
 109 +       JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
 110 +                   JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
 111 +       JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
 112 +                   JH7110_VOUTCLK_I2STX0_BCLK),
 113 +       JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
 114 +};
 115 +
 116 +static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv)
 117 +{
 118 +       struct reset_control *top_rst;
 119 +
 120 +       /* The reset should be shared and other Vout modules will use its. */
 121 +       top_rst = devm_reset_control_get_shared(priv->dev, NULL);
 122 +       if (IS_ERR(top_rst))
 123 +               return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n");
 124 +
 125 +       return reset_control_deassert(top_rst);
 126 +}
 127 +
 128 +static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data)
 129 +{
 130 +       struct jh71x0_clk_priv *priv = data;
 131 +       unsigned int idx = clkspec->args[0];
 132 +
 133 +       if (idx < JH7110_VOUTCLK_END)
 134 +               return &priv->reg[idx].hw;
 135 +
 136 +       return ERR_PTR(-EINVAL);
 137 +}
 138 +
 139 +#ifdef CONFIG_PM
 140 +static int jh7110_voutcrg_suspend(struct device *dev)
 141 +{
 142 +       struct top_sysclk *top = dev_get_drvdata(dev);
 143 +
 144 +       clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
 145 +
 146 +       return 0;
 147 +}
 148 +
 149 +static int jh7110_voutcrg_resume(struct device *dev)
 150 +{
 151 +       struct top_sysclk *top = dev_get_drvdata(dev);
 152 +
 153 +       return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
 154 +}
 155 +#endif
 156 +
 157 +static const struct dev_pm_ops jh7110_voutcrg_pm_ops = {
 158 +       SET_RUNTIME_PM_OPS(jh7110_voutcrg_suspend, jh7110_voutcrg_resume, NULL)
 159 +};
 160 +
 161 +static int jh7110_voutcrg_probe(struct platform_device *pdev)
 162 +{
 163 +       struct jh71x0_clk_priv *priv;
 164 +       struct top_sysclk *top;
 165 +       unsigned int idx;
 166 +       int ret;
 167 +
 168 +       priv = devm_kzalloc(&pdev->dev,
 169 +                           struct_size(priv, reg, JH7110_VOUTCLK_END),
 170 +                           GFP_KERNEL);
 171 +       if (!priv)
 172 +               return -ENOMEM;
 173 +
 174 +       top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
 175 +       if (!top)
 176 +               return -ENOMEM;
 177 +
 178 +       spin_lock_init(&priv->rmw_lock);
 179 +       priv->dev = &pdev->dev;
 180 +       priv->base = devm_platform_ioremap_resource(pdev, 0);
 181 +       if (IS_ERR(priv->base))
 182 +               return PTR_ERR(priv->base);
 183 +
 184 +       top->top_clks = jh7110_vout_top_clks;
 185 +       top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks);
 186 +       ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
 187 +       if (ret)
 188 +               return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");
 189 +       dev_set_drvdata(priv->dev, top);
 190 +
 191 +       /* enable power domain and clocks */
 192 +       pm_runtime_enable(priv->dev);
 193 +       ret = pm_runtime_get_sync(priv->dev);
 194 +       if (ret < 0)
 195 +               return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
 196 +
 197 +       ret = jh7110_vout_top_rst_init(priv);
 198 +       if (ret)
 199 +               goto err_exit;
 200 +
 201 +       for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) {
 202 +               u32 max = jh7110_voutclk_data[idx].max;
 203 +               struct clk_parent_data parents[4] = {};
 204 +               struct clk_init_data init = {
 205 +                       .name = jh7110_voutclk_data[idx].name,
 206 +                       .ops = starfive_jh71x0_clk_ops(max),
 207 +                       .parent_data = parents,
 208 +                       .num_parents =
 209 +                               ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
 210 +                       .flags = jh7110_voutclk_data[idx].flags,
 211 +               };
 212 +               struct jh71x0_clk *clk = &priv->reg[idx];
 213 +               unsigned int i;
 214 +               const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {
 215 +                       "vout_src",
 216 +                       "vout_top_ahb",
 217 +                       "vout_top_axi",
 218 +                       "vout_top_hdmitx0_mclk",
 219 +                       "i2stx0_bclk",
 220 +                       "hdmitx0_pixelclk"
 221 +               };
 222 +
 223 +               for (i = 0; i < init.num_parents; i++) {
 224 +                       unsigned int pidx = jh7110_voutclk_data[idx].parents[i];
 225 +
 226 +                       if (pidx < JH7110_VOUTCLK_END)
 227 +                               parents[i].hw = &priv->reg[pidx].hw;
 228 +                       else if (pidx < JH7110_VOUTCLK_EXT_END)
 229 +                               parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END];
 230 +               }
 231 +
 232 +               clk->hw.init = &init;
 233 +               clk->idx = idx;
 234 +               clk->max_div = max & JH71X0_CLK_DIV_MASK;
 235 +
 236 +               ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
 237 +               if (ret)
 238 +                       goto err_exit;
 239 +       }
 240 +
 241 +       ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv);
 242 +       if (ret)
 243 +               goto err_exit;
 244 +
 245 +       ret = jh7110_reset_controller_register(priv, "rst-vo", 4);
 246 +       if (ret)
 247 +               goto err_exit;
 248 +
 249 +       return 0;
 250 +
 251 +err_exit:
 252 +       pm_runtime_put_sync(priv->dev);
 253 +       pm_runtime_disable(priv->dev);
 254 +       return ret;
 255 +}
 256 +
 257 +static int jh7110_voutcrg_remove(struct platform_device *pdev)
 258 +{
 259 +       pm_runtime_put_sync(&pdev->dev);
 260 +       pm_runtime_disable(&pdev->dev);
 261 +
 262 +       return 0;
 263 +}
 264 +
 265 +static const struct of_device_id jh7110_voutcrg_match[] = {
 266 +       { .compatible = "starfive,jh7110-voutcrg" },
 267 +       { /* sentinel */ }
 268 +};
 269 +MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match);
 270 +
 271 +static struct platform_driver jh7110_voutcrg_driver = {
 272 +       .probe = jh7110_voutcrg_probe,
 273 +       .remove = jh7110_voutcrg_remove,
 274 +       .driver = {
 275 +               .name = "clk-starfive-jh7110-vout",
 276 +               .of_match_table = jh7110_voutcrg_match,
 277 +               .pm = &jh7110_voutcrg_pm_ops,
 278 +       },
 279 +};
 280 +module_platform_driver(jh7110_voutcrg_driver);
 281 +
 282 +MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
 283 +MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver");
 284 +MODULE_LICENSE("GPL");