target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-eth.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2021 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
   6  * Author: Jianhui Zhao <zhaojh329@gmail.com>
   7  * Author: Daniel Golle <daniel@makrotopia.org>
   8  */
   9
  10 #include <linux/clk-provider.h>
  11 #include <linux/of.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15
  16 #include "clk-mtk.h"
  17 #include "clk-gate.h"
  18
  19 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
  20
  21 static const struct mtk_gate_regs sgmii0_cg_regs = {
  22         .set_ofs = 0xE4,
  23         .clr_ofs = 0xE4,
  24         .sta_ofs = 0xE4,
  25 };
  26
  27 #define GATE_SGMII0(_id, _name, _parent, _shift) {      \
  28                 .id = _id,                              \
  29                 .name = _name,                          \
  30                 .parent_name = _parent,                 \
  31                 .regs = &sgmii0_cg_regs,                        \
  32                 .shift = _shift,                        \
  33                 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  34         }
  35
  36 static const struct mtk_gate sgmii0_clks[] __initconst = {
  37         GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
  38         GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
  39         GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
  40         GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
  41 };
  42
  43 static const struct mtk_gate_regs sgmii1_cg_regs = {
  44         .set_ofs = 0xE4,
  45         .clr_ofs = 0xE4,
  46         .sta_ofs = 0xE4,
  47 };
  48
  49 #define GATE_SGMII1(_id, _name, _parent, _shift) {      \
  50                 .id = _id,                              \
  51                 .name = _name,                          \
  52                 .parent_name = _parent,                 \
  53                 .regs = &sgmii1_cg_regs,                        \
  54                 .shift = _shift,                        \
  55                 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  56         }
  57
  58 static const struct mtk_gate sgmii1_clks[] __initconst = {
  59         GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
  60         GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
  61         GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
  62         GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
  63 };
  64
  65 static const struct mtk_gate_regs eth_cg_regs = {
  66         .set_ofs = 0x30,
  67         .clr_ofs = 0x30,
  68         .sta_ofs = 0x30,
  69 };
  70
  71 #define GATE_ETH(_id, _name, _parent, _shift) { \
  72                 .id = _id,                              \
  73                 .name = _name,                          \
  74                 .parent_name = _parent,                 \
  75                 .regs = &eth_cg_regs,                   \
  76                 .shift = _shift,                        \
  77                 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  78         }
  79
  80 static const struct mtk_gate eth_clks[] __initconst = {
  81         GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
  82         GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
  83         GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
  84         GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
  85 };
  86
  87 static void __init mtk_sgmiisys_0_init(struct device_node *node)
  88 {
  89         struct clk_onecell_data *clk_data;
  90         int r;
  91
  92         clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
  93
  94         mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
  95                                clk_data);
  96
  97         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  98         if (r)
  99                 pr_err("%s(): could not register clock provider: %d\n",
 100                        __func__, r);
 101 }
 102 CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7981-sgmiisys_0",
 103                mtk_sgmiisys_0_init);
 104
 105 static void __init mtk_sgmiisys_1_init(struct device_node *node)
 106 {
 107         struct clk_onecell_data *clk_data;
 108         int r;
 109
 110         clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
 111
 112         mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
 113                                clk_data);
 114
 115         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 116
 117         if (r)
 118                 pr_err("%s(): could not register clock provider: %d\n",
 119                        __func__, r);
 120 }
 121 CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7981-sgmiisys_1",
 122                mtk_sgmiisys_1_init);
 123
 124 static void __init mtk_ethsys_init(struct device_node *node)
 125 {
 126         struct clk_onecell_data *clk_data;
 127         int r;
 128
 129         clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
 130
 131         mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
 132
 133         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 134
 135         if (r)
 136                 pr_err("%s(): could not register clock provider: %d\n",
 137                        __func__, r);
 138 }
 139 CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7981-ethsys", mtk_ethsys_init);