--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152.c
-@@ -43,10 +43,14 @@
+@@ -44,10 +44,14 @@
#define PLA_IDR 0xc000
#define PLA_RCR 0xc010
#define PLA_DMY_REG0 0xc0b0
#define PLA_FMC 0xc0b4
#define PLA_CFG_WOL 0xc0b6
-@@ -63,6 +67,8 @@
+@@ -64,6 +68,8 @@
#define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
#define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
#define PLA_EXTRA_STATUS 0xd398
#define PLA_EFUSE_DATA 0xdd00
#define PLA_EFUSE_CMD 0xdd02
#define PLA_LEDSEL 0xdd90
-@@ -72,6 +78,8 @@
+@@ -73,6 +79,8 @@
#define PLA_LWAKE_CTRL_REG 0xe007
#define PLA_GPHY_INTR_IMR 0xe022
#define PLA_EEE_CR 0xe040
#define PLA_EEEP_CR 0xe080
#define PLA_MAC_PWR_CTRL 0xe0c0
#define PLA_MAC_PWR_CTRL2 0xe0ca
-@@ -82,6 +90,7 @@
+@@ -83,6 +91,7 @@
#define PLA_TCR1 0xe612
#define PLA_MTPS 0xe615
#define PLA_TXFIFO_CTRL 0xe618
#define PLA_RSTTALLY 0xe800
#define PLA_CR 0xe813
#define PLA_CRWECR 0xe81c
-@@ -98,6 +107,7 @@
+@@ -99,6 +108,7 @@
#define PLA_SFF_STS_7 0xe8de
#define PLA_PHYSTATUS 0xe908
#define PLA_CONFIG6 0xe90a /* CONFIG6 */
#define PLA_BP_BA 0xfc26
#define PLA_BP_0 0xfc28
#define PLA_BP_1 0xfc2a
-@@ -112,6 +122,7 @@
+@@ -113,6 +123,7 @@
#define USB_USB2PHY 0xb41e
#define USB_SSPHYLINK1 0xb426
#define USB_SSPHYLINK2 0xb428
#define USB_U2P3_CTRL 0xb460
#define USB_CSR_DUMMY1 0xb464
#define USB_CSR_DUMMY2 0xb466
-@@ -122,7 +133,12 @@
+@@ -123,7 +134,12 @@
#define USB_FW_FIX_EN0 0xcfca
#define USB_FW_FIX_EN1 0xcfcc
#define USB_LPM_CONFIG 0xcfd8
#define USB_FW_CTRL 0xd334 /* RTL8153B */
#define USB_FC_TIMER 0xd340
#define USB_USB_CTRL 0xd406
-@@ -136,16 +152,20 @@
+@@ -137,16 +153,20 @@
#define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
#define USB_TX_DMA 0xd434
#define USB_UPT_RXDMA_OWN 0xd437
#define USB_UPS_CFG 0xd842
#define USB_UPS_FLAGS 0xd848
#define USB_WDT1_CTRL 0xe404
-@@ -188,6 +208,9 @@
+@@ -189,6 +209,9 @@
#define OCP_EEE_ABLE 0xa5c4
#define OCP_EEE_ADV 0xa5d0
#define OCP_EEE_LPABLE 0xa5d2
#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
#define OCP_PHY_PATCH_STAT 0xb800
#define OCP_PHY_PATCH_CMD 0xb820
-@@ -199,6 +222,7 @@
+@@ -200,6 +223,7 @@
/* SRAM Register */
#define SRAM_GREEN_CFG 0x8011
#define SRAM_LPF_CFG 0x8012
#define SRAM_10M_AMP1 0x8080
#define SRAM_10M_AMP2 0x8082
#define SRAM_IMPEDANCE 0x8084
-@@ -210,11 +234,19 @@
+@@ -211,11 +235,19 @@
#define RCR_AM 0x00000004
#define RCR_AB 0x00000008
#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
/* PLA_RXFIFO_CTRL1 */
#define RXFIFO_THR2_FULL 0x00000060
#define RXFIFO_THR2_HIGH 0x00000038
-@@ -285,6 +317,7 @@
+@@ -286,6 +318,7 @@
#define MCU_BORW_EN 0x4000
/* PLA_CPCR */
#define CPCR_RX_VLAN 0x0040
/* PLA_CFG_WOL */
-@@ -310,6 +343,10 @@
+@@ -311,6 +344,10 @@
/* PLA_CONFIG6 */
#define LANWAKE_CLR_EN BIT(0)
/* PLA_CONFIG5 */
#define BWF_EN 0x0040
#define MWF_EN 0x0020
-@@ -333,6 +370,7 @@
+@@ -334,6 +371,7 @@
/* PLA_MAC_PWR_CTRL2 */
#define EEE_SPDWN_RATIO 0x8007
#define MAC_CLK_SPDWN_EN BIT(15)
/* PLA_MAC_PWR_CTRL3 */
#define PLA_MCU_SPDWN_EN BIT(14)
-@@ -345,6 +383,7 @@
+@@ -346,6 +384,7 @@
#define PWRSAVE_SPDWN_EN 0x1000
#define RXDV_SPDWN_EN 0x0800
#define TX10MIDLE_EN 0x0100
#define TP100_SPDWN_EN 0x0020
#define TP500_SPDWN_EN 0x0010
#define TP1000_SPDWN_EN 0x0008
-@@ -385,6 +424,13 @@
+@@ -386,6 +425,13 @@
#define LINK_CHANGE_FLAG BIT(8)
#define POLL_LINK_CHG BIT(0)
/* USB_USB2PHY */
#define USB2PHY_SUSPEND 0x0001
#define USB2PHY_L1 0x0002
-@@ -433,6 +479,9 @@
+@@ -434,6 +480,9 @@
#define BMU_RESET_EP_IN 0x01
#define BMU_RESET_EP_OUT 0x02
/* USB_UPT_RXDMA_OWN */
#define OWN_UPDATE BIT(0)
#define OWN_CLEAR BIT(1)
-@@ -440,27 +489,52 @@
+@@ -441,27 +490,52 @@
/* USB_FW_TASK */
#define FC_PATCH_TASK BIT(1)
/* USB_POWER_CUT */
#define PWR_EN 0x0001
-@@ -496,8 +570,12 @@
+@@ -497,8 +571,12 @@
#define SEN_VAL_NORMAL 0xa000
#define SEL_RXIDLE 0x0100
/* USB_UPS_FLAGS */
#define UPS_FLAGS_R_TUNE BIT(0)
-@@ -505,6 +583,7 @@
+@@ -506,6 +584,7 @@
#define UPS_FLAGS_250M_CKDIV BIT(2)
#define UPS_FLAGS_EN_ALDPS BIT(3)
#define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
#define ups_flags_speed(x) ((x) << 16)
#define UPS_FLAGS_EN_EEE BIT(20)
#define UPS_FLAGS_EN_500M_EEE BIT(21)
-@@ -525,6 +604,8 @@ enum spd_duplex {
+@@ -526,6 +605,8 @@ enum spd_duplex {
FORCE_10M_FULL,
FORCE_100M_HALF,
FORCE_100M_FULL,
};
/* OCP_ALDPS_CONFIG */
-@@ -589,6 +670,9 @@ enum spd_duplex {
+@@ -590,6 +671,9 @@ enum spd_duplex {
#define EN_10M_CLKDIV BIT(11)
#define EN_10M_BGOFF 0x0080
/* OCP_PHY_STATE */
#define TXDIS_STATE 0x01
#define ABD_STATE 0x02
-@@ -608,7 +692,8 @@ enum spd_duplex {
+@@ -609,7 +693,8 @@ enum spd_duplex {
#define EN_EMI_L 0x0040
/* OCP_SYSCLK_CFG */
/* SRAM_GREEN_CFG */
#define GREEN_ETH_EN BIT(15)
-@@ -639,6 +724,11 @@ enum spd_duplex {
+@@ -640,6 +725,11 @@ enum spd_duplex {
#define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
enum rtl_register_content {
_1000bps = 0x10,
_100bps = 0x08,
_10bps = 0x04,
-@@ -646,6 +736,9 @@ enum rtl_register_content {
+@@ -647,6 +737,9 @@ enum rtl_register_content {
FULL_DUP = 0x01,
};
#define RTL8152_MAX_TX 4
#define RTL8152_MAX_RX 10
#define INTBUFSIZE 2
-@@ -660,7 +753,6 @@ enum rtl_register_content {
+@@ -661,7 +754,6 @@ enum rtl_register_content {
#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
#define RTL8153_RMS RTL8153_MAX_PACKET
#define RTL8152_TX_TIMEOUT (5 * HZ)
#define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
#define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
#define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
-@@ -797,6 +889,7 @@ struct r8152 {
+@@ -798,6 +890,7 @@ struct r8152 {
} rtl_ops;
struct ups_info {
u32 _10m_ckdiv:1;
u32 _250m_ckdiv:1;
u32 aldps:1;
-@@ -838,7 +931,9 @@ struct r8152 {
+@@ -839,7 +932,9 @@ struct r8152 {
u32 rx_buf_sz;
u32 rx_copybreak;
u32 rx_pending;
u16 ocp_base;
u16 speed;
u16 eee_adv;
-@@ -998,6 +1093,15 @@ enum rtl_version {
+@@ -999,6 +1094,15 @@ enum rtl_version {
RTL_VER_07,
RTL_VER_08,
RTL_VER_09,
RTL_VER_MAX
};
-@@ -1013,6 +1117,7 @@ enum tx_csum_stat {
+@@ -1014,6 +1118,7 @@ enum tx_csum_stat {
#define RTL_ADVERTISED_100_FULL BIT(3)
#define RTL_ADVERTISED_1000_HALF BIT(4)
#define RTL_ADVERTISED_1000_FULL BIT(5)
/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
* The RTL chips use a 64 element hash table based on the Ethernet CRC.
-@@ -2606,7 +2711,7 @@ static netdev_tx_t rtl8152_start_xmit(st
+@@ -2607,7 +2712,7 @@ static netdev_tx_t rtl8152_start_xmit(st
static void r8152b_reset_packet_filter(struct r8152 *tp)
{
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
ocp_data &= ~FMC_FCR_MCU_EN;
-@@ -2617,14 +2722,47 @@ static void r8152b_reset_packet_filter(s
+@@ -2618,14 +2723,47 @@ static void r8152b_reset_packet_filter(s
static void rtl8152_nic_reset(struct r8152 *tp)
{
}
}
-@@ -2633,9 +2771,9 @@ static void set_tx_qlen(struct r8152 *tp
+@@ -2634,9 +2772,9 @@ static void set_tx_qlen(struct r8152 *tp
tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
}
}
static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
-@@ -2795,6 +2933,7 @@ static int rtl_enable(struct r8152 *tp)
+@@ -2796,6 +2934,7 @@ static int rtl_enable(struct r8152 *tp)
switch (tp->version) {
case RTL_VER_08:
case RTL_VER_09:
r8153b_rx_agg_chg_indicate(tp);
break;
default:
-@@ -2832,6 +2971,7 @@ static void r8153_set_rx_early_timeout(s
+@@ -2833,6 +2972,7 @@ static void r8153_set_rx_early_timeout(s
case RTL_VER_08:
case RTL_VER_09:
/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
* primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
*/
-@@ -2841,6 +2981,18 @@ static void r8153_set_rx_early_timeout(s
+@@ -2842,6 +2982,18 @@ static void r8153_set_rx_early_timeout(s
ocp_data);
break;
default:
break;
}
-@@ -2860,8 +3012,19 @@ static void r8153_set_rx_early_size(stru
+@@ -2861,8 +3013,19 @@ static void r8153_set_rx_early_size(stru
break;
case RTL_VER_08:
case RTL_VER_09:
break;
default:
WARN_ON_ONCE(1);
-@@ -2871,6 +3034,8 @@ static void r8153_set_rx_early_size(stru
+@@ -2872,6 +3035,8 @@ static void r8153_set_rx_early_size(stru
static int rtl8153_enable(struct r8152 *tp)
{
if (test_bit(RTL8152_UNPLUG, &tp->flags))
return -ENODEV;
-@@ -2881,15 +3046,18 @@ static int rtl8153_enable(struct r8152 *
+@@ -2882,15 +3047,18 @@ static int rtl8153_enable(struct r8152 *
rtl_set_ifg(tp, rtl8152_get_speed(tp));
}
return rtl_enable(tp);
-@@ -2954,12 +3122,40 @@ static void rtl_rx_vlan_en(struct r8152
+@@ -2955,12 +3123,40 @@ static void rtl_rx_vlan_en(struct r8152
{
u32 ocp_data;
}
static int rtl8152_set_features(struct net_device *dev,
-@@ -3052,6 +3248,40 @@ static void __rtl_set_wol(struct r8152 *
+@@ -3053,6 +3249,40 @@ static void __rtl_set_wol(struct r8152 *
device_set_wakeup_enable(&tp->udev->dev, false);
}
static void r8153_u1u2en(struct r8152 *tp, bool enable)
{
u8 u1u2[8];
-@@ -3111,6 +3341,9 @@ static void r8153b_ups_flags(struct r815
+@@ -3112,6 +3342,9 @@ static void r8153b_ups_flags(struct r815
if (tp->ups_info.eee_cmod_lv)
ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
if (tp->ups_info._10m_ckdiv)
ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
-@@ -3161,6 +3394,88 @@ static void r8153b_ups_flags(struct r815
+@@ -3162,6 +3395,88 @@ static void r8153b_ups_flags(struct r815
ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
}
static void rtl_green_en(struct r8152 *tp, bool enable)
{
u16 data;
-@@ -3224,16 +3539,16 @@ static void r8153b_ups_en(struct r8152 *
+@@ -3225,16 +3540,16 @@ static void r8153b_ups_en(struct r8152 *
ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
int i;
-@@ -3253,6 +3568,95 @@ static void r8153b_ups_en(struct r8152 *
+@@ -3254,6 +3569,95 @@ static void r8153b_ups_en(struct r8152 *
}
}
static void r8153_power_cut_en(struct r8152 *tp, bool enable)
{
u32 ocp_data;
-@@ -3382,6 +3786,38 @@ static void rtl8153b_runtime_enable(stru
+@@ -3383,6 +3787,38 @@ static void rtl8153b_runtime_enable(stru
}
}
static void r8153_teredo_off(struct r8152 *tp)
{
u32 ocp_data;
-@@ -3402,14 +3838,19 @@ static void r8153_teredo_off(struct r815
+@@ -3403,14 +3839,19 @@ static void r8153_teredo_off(struct r815
case RTL_VER_08:
case RTL_VER_09:
}
ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
-@@ -3444,6 +3885,12 @@ static void rtl_clear_bp(struct r8152 *t
+@@ -3445,6 +3886,12 @@ static void rtl_clear_bp(struct r8152 *t
break;
case RTL_VER_08:
case RTL_VER_09:
default:
if (type == MCU_TYPE_USB) {
ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
-@@ -3653,6 +4100,11 @@ static bool rtl8152_is_fw_mac_ok(struct
+@@ -3654,6 +4101,11 @@ static bool rtl8152_is_fw_mac_ok(struct
case RTL_VER_06:
case RTL_VER_08:
case RTL_VER_09:
fw_reg = 0xf800;
bp_ba_addr = PLA_BP_BA;
bp_en_addr = PLA_BP_EN;
-@@ -3676,6 +4128,11 @@ static bool rtl8152_is_fw_mac_ok(struct
+@@ -3677,6 +4129,11 @@ static bool rtl8152_is_fw_mac_ok(struct
break;
case RTL_VER_08:
case RTL_VER_09:
fw_reg = 0xe600;
bp_ba_addr = USB_BP_BA;
bp_en_addr = USB_BP2_EN;
-@@ -4215,6 +4672,22 @@ static void r8153_eee_en(struct r8152 *t
+@@ -4216,6 +4673,22 @@ static void r8153_eee_en(struct r8152 *t
tp->ups_info.eee = enable;
}
static void rtl_eee_enable(struct r8152 *tp, bool enable)
{
switch (tp->version) {
-@@ -4236,6 +4709,7 @@ static void rtl_eee_enable(struct r8152
+@@ -4237,6 +4710,7 @@ static void rtl_eee_enable(struct r8152
case RTL_VER_06:
case RTL_VER_08:
case RTL_VER_09:
if (enable) {
r8153_eee_en(tp, true);
ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
-@@ -4244,6 +4718,19 @@ static void rtl_eee_enable(struct r8152
+@@ -4245,6 +4719,19 @@ static void rtl_eee_enable(struct r8152
ocp_reg_write(tp, OCP_EEE_ADV, 0);
}
break;
default:
break;
}
-@@ -4290,6 +4777,20 @@ static void wait_oob_link_list_ready(str
+@@ -4291,6 +4778,20 @@ static void wait_oob_link_list_ready(str
}
}
static void r8152b_exit_oob(struct r8152 *tp)
{
u32 ocp_data;
-@@ -4340,7 +4841,7 @@ static void r8152b_exit_oob(struct r8152
+@@ -4341,7 +4842,7 @@ static void r8152b_exit_oob(struct r8152
}
/* TX share fifo free credit full threshold */
ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
-@@ -4517,6 +5018,21 @@ static int r8153b_post_firmware_1(struct
+@@ -4518,6 +5019,21 @@ static int r8153b_post_firmware_1(struct
return 0;
}
static void r8153_aldps_en(struct r8152 *tp, bool enable)
{
u16 data;
-@@ -4719,6 +5235,13 @@ static void r8153b_hw_phy_cfg(struct r81
+@@ -4720,6 +5236,13 @@ static void r8153b_hw_phy_cfg(struct r81
set_bit(PHY_RESET, &tp->flags);
}
static void rtl8153_change_mtu(struct r8152 *tp)
{
ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
-@@ -4806,6 +5329,7 @@ static void r8153_enter_oob(struct r8152
+@@ -4807,6 +5330,7 @@ static void r8153_enter_oob(struct r8152
case RTL_VER_08:
case RTL_VER_09:
/* Clear teredo wake event. bit[15:8] is the teredo wakeup
* type. Set it to zero. bits[7:0] are the W1C bits about
* the events. Set them to all 1 to clear them.
-@@ -4842,6 +5366,96 @@ static void rtl8153_disable(struct r8152
+@@ -4843,6 +5367,96 @@ static void rtl8153_disable(struct r8152
r8153_aldps_en(tp, true);
}
static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
u32 advertising)
{
-@@ -4890,58 +5504,73 @@ static int rtl8152_set_speed(struct r815
+@@ -4891,58 +5505,73 @@ static int rtl8152_set_speed(struct r815
tp->mii.force_media = 1;
} else {
}
bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
-@@ -5097,6 +5726,253 @@ static void rtl8153b_down(struct r8152 *
+@@ -5098,6 +5727,253 @@ static void rtl8153b_down(struct r8152 *
r8153_aldps_en(tp, true);
}
static bool rtl8152_in_nway(struct r8152 *tp)
{
u16 nway_state;
-@@ -5127,7 +6003,7 @@ static void set_carrier(struct r8152 *tp
+@@ -5128,7 +6004,7 @@ static void set_carrier(struct r8152 *tp
{
struct net_device *netdev = tp->netdev;
struct napi_struct *napi = &tp->napi;
speed = rtl8152_get_speed(tp);
-@@ -5140,7 +6016,7 @@ static void set_carrier(struct r8152 *tp
+@@ -5141,7 +6017,7 @@ static void set_carrier(struct r8152 *tp
rtl_start_rx(tp);
clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
_rtl8152_set_rx_mode(netdev);
netif_wake_queue(netdev);
netif_info(tp, link, netdev, "carrier on\n");
} else if (netif_queue_stopped(netdev) &&
-@@ -5502,14 +6378,9 @@ static void r8153_init(struct r8152 *tp)
+@@ -5521,14 +6397,9 @@ static void r8153_init(struct r8152 *tp)
ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
r8153_u1u2en(tp, true);
usb_enable_lpm(tp->udev);
-@@ -5600,9 +6471,7 @@ static void r8153b_init(struct r8152 *tp
+@@ -5621,9 +6492,7 @@ static void r8153b_init(struct r8152 *tp
usb_enable_lpm(tp->udev);
/* MAC clock speed down */
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
ocp_data &= ~PLA_MCU_SPDWN_EN;
-@@ -5629,6 +6498,1069 @@ static void r8153b_init(struct r8152 *tp
- tp->coalesce = 15000; /* 15 us */
+@@ -5652,6 +6521,1069 @@ static void r8153b_init(struct r8152 *tp
+ r8152_led_configuration(tp);
}
+static void r8153c_init(struct r8152 *tp)
static int rtl8152_pre_reset(struct usb_interface *intf)
{
struct r8152 *tp = usb_get_intfdata(intf);
-@@ -5992,6 +7924,22 @@ int rtl8152_get_link_ksettings(struct ne
+@@ -6015,6 +7947,22 @@ int rtl8152_get_link_ksettings(struct ne
mii_ethtool_get_link_ksettings(&tp->mii, cmd);
mutex_unlock(&tp->control);
usb_autopm_put_interface(tp->intf);
-@@ -6035,6 +7983,10 @@ static int rtl8152_set_link_ksettings(st
+@@ -6058,6 +8006,10 @@ static int rtl8152_set_link_ksettings(st
cmd->link_modes.advertising))
advertising |= RTL_ADVERTISED_1000_FULL;
mutex_lock(&tp->control);
ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
-@@ -6624,6 +8576,67 @@ static int rtl_ops_init(struct r8152 *tp
+@@ -6647,6 +8599,67 @@ static int rtl_ops_init(struct r8152 *tp
tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
break;
default:
ret = -ENODEV;
dev_err(&tp->intf->dev, "Unknown Device\n");
-@@ -6637,11 +8650,13 @@ static int rtl_ops_init(struct r8152 *tp
+@@ -6660,11 +8673,13 @@ static int rtl_ops_init(struct r8152 *tp
#define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
#define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
#define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
static int rtl_fw_init(struct r8152 *tp)
{
-@@ -6667,6 +8682,11 @@ static int rtl_fw_init(struct r8152 *tp)
+@@ -6690,6 +8705,11 @@ static int rtl_fw_init(struct r8152 *tp)
rtl_fw->pre_fw = r8153b_pre_firmware_1;
rtl_fw->post_fw = r8153b_post_firmware_1;
break;
default:
break;
}
-@@ -6722,6 +8742,27 @@ u8 rtl8152_get_version(struct usb_interf
+@@ -6745,6 +8765,27 @@ u8 rtl8152_get_version(struct usb_interf
case 0x6010:
version = RTL_VER_09;
break;
default:
version = RTL_VER_UNKNOWN;
dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
-@@ -6834,12 +8875,29 @@ static int rtl8152_probe(struct usb_inte
+@@ -6857,12 +8898,29 @@ static int rtl8152_probe(struct usb_inte
/* MTU range: 68 - 1500 or 9194 */
netdev->min_mtu = ETH_MIN_MTU;
switch (tp->version) {
break;
}
-@@ -6855,7 +8913,13 @@ static int rtl8152_probe(struct usb_inte
+@@ -6878,7 +8936,13 @@ static int rtl8152_probe(struct usb_inte
tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
if (tp->mii.supports_gmii) {
tp->advertising |= RTL_ADVERTISED_1000_FULL;
}
tp->duplex = DUPLEX_FULL;
-@@ -6879,7 +8943,11 @@ static int rtl8152_probe(struct usb_inte
+@@ -6902,7 +8966,11 @@ static int rtl8152_probe(struct usb_inte
set_ethernet_addr(tp);
usb_set_intfdata(intf, tp);
ret = register_netdev(netdev);
if (ret != 0) {
-@@ -6915,7 +8983,8 @@ static void rtl8152_disconnect(struct us
+@@ -6938,7 +9006,8 @@ static void rtl8152_disconnect(struct us
unregister_netdev(tp->netdev);
tasklet_kill(&tp->tx_tl);
cancel_delayed_work_sync(&tp->hw_phy_work);
rtl8152_release_firmware(tp);
free_netdev(tp->netdev);
}
-@@ -6935,13 +9004,28 @@ static void rtl8152_disconnect(struct us
+@@ -6958,13 +9027,28 @@ static void rtl8152_disconnect(struct us
.idProduct = (prod), \
.bInterfaceClass = USB_CLASS_COMM, \
.bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
projects / openwrt / staging / thess.git / blobdiff