kernel: move mv88e6xxx fix to generic backports

[openwrt/staging/stintel.git] / target / linux / generic / backport-6.1 / 807-v6.5-01-net-dsa-mv88e6xxx-pass-directly-chip-structure-to-mv.patch

diff --git a/target/linux/generic/backport-6.1/807-v6.5-01-net-dsa-mv88e6xxx-pass-directly-chip-structure-to-mv.patch b/target/linux/generic/backport-6.1/807-v6.5-01-net-dsa-mv88e6xxx-pass-directly-chip-structure-to-mv.patch
index 58777cd280be9f4433a8d08f11b893d217ef183e..8c062dc3b4c6eb02ff9b07d5ee413be4566594f7 100644 (file)
--- a/target/linux/generic/backport-6.1/807-v6.5-01-net-dsa-mv88e6xxx-pass-directly-chip-structure-to-mv.patch
+++ b/target/linux/generic/backport-6.1/807-v6.5-01-net-dsa-mv88e6xxx-pass-directly-chip-structure-to-mv.patch
@@ -44,7 +44,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
                __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
        } else {
                if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
-@@ -839,7 +837,7 @@ static void mv88e6xxx_get_caps(struct ds
+@@ -851,7 +849,7 @@ static void mv88e6xxx_get_caps(struct ds
        chip->info->ops->phylink_get_caps(chip, port, config);
        mv88e6xxx_reg_unlock(chip);
  
@@ -53,7 +53,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
                __set_bit(PHY_INTERFACE_MODE_INTERNAL,
                          config->supported_interfaces);
                /* Internal ports with no phy-mode need GMII for PHYLIB */
-@@ -860,7 +858,7 @@ static void mv88e6xxx_mac_config(struct
+@@ -872,7 +870,7 @@ static void mv88e6xxx_mac_config(struct
  
        mv88e6xxx_reg_lock(chip);