mediatek: rewrite flow offload code

[openwrt/staging/rmilecki.git] / target / linux / mediatek / patches-5.4 / 1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch

diff --git a/target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch b/target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch
index ed9aecdf74b32e967bb82f64b7abe96b3bd33c96..18ddd0863ef355e1b3824c1d096a405b233b3df9 100644 (file)
--- a/target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch
+++ b/target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch
@@ -37,12 +37,13 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #include <linux/mfd/syscon.h>
  #include <linux/regmap.h>
  #include <linux/clk.h>
-@@ -2486,6 +2487,12 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2482,6 +2483,13 @@ static int mtk_hw_init(struct mtk_eth *e
        if (ret)
                goto err_disable_pm;
  
 +      if (of_dma_is_coherent(eth->dev->of_node)) {
-+              u32 mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA;
++              u32 mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
++                         ETHSYS_DMA_AG_MAP_PPE;
 +
 +              regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, mask, mask);
 +      }
@@ -50,7 +51,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
        if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
                ret = device_reset(eth->dev);
                if (ret) {
-@@ -3088,6 +3095,16 @@ static int mtk_probe(struct platform_dev
+@@ -3080,6 +3088,16 @@ static int mtk_probe(struct platform_dev
                }
        }
  
@@ -69,7 +70,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
                                          GFP_KERNEL);
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -426,6 +426,11 @@
+@@ -435,6 +435,12 @@
  #define RSTCTRL_FE            BIT(6)
  #define RSTCTRL_PPE           BIT(31)
  
@@ -77,6 +78,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +#define ETHSYS_DMA_AG_MAP     0x408
 +#define ETHSYS_DMA_AG_MAP_PDMA        BIT(0)
 +#define ETHSYS_DMA_AG_MAP_QDMA        BIT(1)
++#define ETHSYS_DMA_AG_MAP_PPE BIT(2)
 +
  /* SGMII subsystem config registers */
  /* Register to auto-negotiation restart */