--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -680,7 +680,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
+@@ -674,7 +674,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
};
static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
{ .fw_name = "xo", .name = "xo" },
};
-@@ -733,7 +733,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
+@@ -727,7 +727,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
};
static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
{ .fw_name = "xo", .name = "xo" },
};
-@@ -1137,7 +1137,7 @@ static const struct freq_tbl ftbl_nss_no
+@@ -1131,7 +1131,7 @@ static const struct freq_tbl ftbl_nss_no
static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
-@@ -1362,7 +1362,7 @@ static const struct freq_tbl ftbl_nss_pp
+@@ -1356,7 +1356,7 @@ static const struct freq_tbl ftbl_nss_pp
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &nss_crypto_pll.clkr.hw },
-@@ -1413,10 +1413,10 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1407,10 +1407,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
};
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
-@@ -1465,10 +1465,10 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1459,10 +1459,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
};
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
-@@ -1696,12 +1696,12 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1690,12 +1690,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
};
static const struct parent_map
-@@ -1758,12 +1758,12 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1752,12 +1752,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
};
static const struct parent_map
-@@ -1820,10 +1820,10 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1814,10 +1814,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
};
static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
-@@ -1877,10 +1877,10 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1871,10 +1871,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },