delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
delete mode 100644 include/soc/fsl/qe/qe_ic.h
-diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c
-similarity index 54%
-rename from drivers/soc/fsl/qe/qe_ic.c
-rename to drivers/irqchip/irq-qeic.c
-index ec2ca864..21e3b43c 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
-+++ b/drivers/irqchip/irq-qeic.c
-@@ -1,7 +1,7 @@
- /*
++++ /dev/null
+@@ -1,512 +0,0 @@
+-/*
- * arch/powerpc/sysdev/qe_lib/qe_ic.c
-+ * drivers/irqchip/irq-qeic.c
- *
+- *
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
+- *
+- * Author: Li Yang <leoli@freescale.com>
+- * Based on code from Shlomi Gridish <gridish@freescale.com>
+- *
+- * QUICC ENGINE Interrupt Controller
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- */
+-
+-#include <linux/of_irq.h>
+-#include <linux/of_address.h>
+-#include <linux/kernel.h>
+-#include <linux/init.h>
+-#include <linux/errno.h>
+-#include <linux/reboot.h>
+-#include <linux/slab.h>
+-#include <linux/stddef.h>
+-#include <linux/sched.h>
+-#include <linux/signal.h>
+-#include <linux/device.h>
+-#include <linux/spinlock.h>
+-#include <asm/irq.h>
+-#include <asm/io.h>
+-#include <soc/fsl/qe/qe_ic.h>
+-
+-#include "qe_ic.h"
+-
+-static DEFINE_RAW_SPINLOCK(qe_ic_lock);
+-
+-static struct qe_ic_info qe_ic_info[] = {
+- [1] = {
+- .mask = 0x00008000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 0,
+- .pri_reg = QEIC_CIPWCC,
+- },
+- [2] = {
+- .mask = 0x00004000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 1,
+- .pri_reg = QEIC_CIPWCC,
+- },
+- [3] = {
+- .mask = 0x00002000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 2,
+- .pri_reg = QEIC_CIPWCC,
+- },
+- [10] = {
+- .mask = 0x00000040,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 1,
+- .pri_reg = QEIC_CIPZCC,
+- },
+- [11] = {
+- .mask = 0x00000020,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 2,
+- .pri_reg = QEIC_CIPZCC,
+- },
+- [12] = {
+- .mask = 0x00000010,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 3,
+- .pri_reg = QEIC_CIPZCC,
+- },
+- [13] = {
+- .mask = 0x00000008,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 4,
+- .pri_reg = QEIC_CIPZCC,
+- },
+- [14] = {
+- .mask = 0x00000004,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 5,
+- .pri_reg = QEIC_CIPZCC,
+- },
+- [15] = {
+- .mask = 0x00000002,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 6,
+- .pri_reg = QEIC_CIPZCC,
+- },
+- [20] = {
+- .mask = 0x10000000,
+- .mask_reg = QEIC_CRIMR,
+- .pri_code = 3,
+- .pri_reg = QEIC_CIPRTA,
+- },
+- [25] = {
+- .mask = 0x00800000,
+- .mask_reg = QEIC_CRIMR,
+- .pri_code = 0,
+- .pri_reg = QEIC_CIPRTB,
+- },
+- [26] = {
+- .mask = 0x00400000,
+- .mask_reg = QEIC_CRIMR,
+- .pri_code = 1,
+- .pri_reg = QEIC_CIPRTB,
+- },
+- [27] = {
+- .mask = 0x00200000,
+- .mask_reg = QEIC_CRIMR,
+- .pri_code = 2,
+- .pri_reg = QEIC_CIPRTB,
+- },
+- [28] = {
+- .mask = 0x00100000,
+- .mask_reg = QEIC_CRIMR,
+- .pri_code = 3,
+- .pri_reg = QEIC_CIPRTB,
+- },
+- [32] = {
+- .mask = 0x80000000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 0,
+- .pri_reg = QEIC_CIPXCC,
+- },
+- [33] = {
+- .mask = 0x40000000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 1,
+- .pri_reg = QEIC_CIPXCC,
+- },
+- [34] = {
+- .mask = 0x20000000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 2,
+- .pri_reg = QEIC_CIPXCC,
+- },
+- [35] = {
+- .mask = 0x10000000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 3,
+- .pri_reg = QEIC_CIPXCC,
+- },
+- [36] = {
+- .mask = 0x08000000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 4,
+- .pri_reg = QEIC_CIPXCC,
+- },
+- [40] = {
+- .mask = 0x00800000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 0,
+- .pri_reg = QEIC_CIPYCC,
+- },
+- [41] = {
+- .mask = 0x00400000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 1,
+- .pri_reg = QEIC_CIPYCC,
+- },
+- [42] = {
+- .mask = 0x00200000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 2,
+- .pri_reg = QEIC_CIPYCC,
+- },
+- [43] = {
+- .mask = 0x00100000,
+- .mask_reg = QEIC_CIMR,
+- .pri_code = 3,
+- .pri_reg = QEIC_CIPYCC,
+- },
+-};
+-
+-static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
+-{
+- return in_be32(base + (reg >> 2));
+-}
+-
+-static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
+- u32 value)
+-{
+- out_be32(base + (reg >> 2), value);
+-}
+-
+-static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
+-{
+- return irq_get_chip_data(virq);
+-}
+-
+-static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
+-{
+- return irq_data_get_irq_chip_data(d);
+-}
+-
+-static void qe_ic_unmask_irq(struct irq_data *d)
+-{
+- struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
+- unsigned int src = irqd_to_hwirq(d);
+- unsigned long flags;
+- u32 temp;
+-
+- raw_spin_lock_irqsave(&qe_ic_lock, flags);
+-
+- temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
+- qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
+- temp | qe_ic_info[src].mask);
+-
+- raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
+-}
+-
+-static void qe_ic_mask_irq(struct irq_data *d)
+-{
+- struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
+- unsigned int src = irqd_to_hwirq(d);
+- unsigned long flags;
+- u32 temp;
+-
+- raw_spin_lock_irqsave(&qe_ic_lock, flags);
+-
+- temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
+- qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
+- temp & ~qe_ic_info[src].mask);
+-
+- /* Flush the above write before enabling interrupts; otherwise,
+- * spurious interrupts will sometimes happen. To be 100% sure
+- * that the write has reached the device before interrupts are
+- * enabled, the mask register would have to be read back; however,
+- * this is not required for correctness, only to avoid wasting
+- * time on a large number of spurious interrupts. In testing,
+- * a sync reduced the observed spurious interrupts to zero.
+- */
+- mb();
+-
+- raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
+-}
+-
+-static struct irq_chip qe_ic_irq_chip = {
+- .name = "QEIC",
+- .irq_unmask = qe_ic_unmask_irq,
+- .irq_mask = qe_ic_mask_irq,
+- .irq_mask_ack = qe_ic_mask_irq,
+-};
+-
+-static int qe_ic_host_match(struct irq_domain *h, struct device_node *node,
+- enum irq_domain_bus_token bus_token)
+-{
+- /* Exact match, unless qe_ic node is NULL */
+- struct device_node *of_node = irq_domain_get_of_node(h);
+- return of_node == NULL || of_node == node;
+-}
+-
+-static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,
+- irq_hw_number_t hw)
+-{
+- struct qe_ic *qe_ic = h->host_data;
+- struct irq_chip *chip;
+-
+- if (hw >= ARRAY_SIZE(qe_ic_info)) {
+- pr_err("%s: Invalid hw irq number for QEIC\n", __func__);
+- return -EINVAL;
+- }
+-
+- if (qe_ic_info[hw].mask == 0) {
+- printk(KERN_ERR "Can't map reserved IRQ\n");
+- return -EINVAL;
+- }
+- /* Default chip */
+- chip = &qe_ic->hc_irq;
+-
+- irq_set_chip_data(virq, qe_ic);
+- irq_set_status_flags(virq, IRQ_LEVEL);
+-
+- irq_set_chip_and_handler(virq, chip, handle_level_irq);
+-
+- return 0;
+-}
+-
+-static const struct irq_domain_ops qe_ic_host_ops = {
+- .match = qe_ic_host_match,
+- .map = qe_ic_host_map,
+- .xlate = irq_domain_xlate_onetwocell,
+-};
+-
+-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+-unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
+-{
+- int irq;
+-
+- BUG_ON(qe_ic == NULL);
+-
+- /* get the interrupt source vector. */
+- irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
+-
+- if (irq == 0)
+- return NO_IRQ;
+-
+- return irq_linear_revmap(qe_ic->irqhost, irq);
+-}
+-
+-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+-unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
+-{
+- int irq;
+-
+- BUG_ON(qe_ic == NULL);
+-
+- /* get the interrupt source vector. */
+- irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
+-
+- if (irq == 0)
+- return NO_IRQ;
+-
+- return irq_linear_revmap(qe_ic->irqhost, irq);
+-}
+-
+-void __init qe_ic_init(struct device_node *node, unsigned int flags,
+- void (*low_handler)(struct irq_desc *desc),
+- void (*high_handler)(struct irq_desc *desc))
+-{
+- struct qe_ic *qe_ic;
+- struct resource res;
+- u32 temp = 0, ret, high_active = 0;
+-
+- ret = of_address_to_resource(node, 0, &res);
+- if (ret)
+- return;
+-
+- qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
+- if (qe_ic == NULL)
+- return;
+-
+- qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
+- &qe_ic_host_ops, qe_ic);
+- if (qe_ic->irqhost == NULL) {
+- kfree(qe_ic);
+- return;
+- }
+-
+- qe_ic->regs = ioremap(res.start, resource_size(&res));
+-
+- qe_ic->hc_irq = qe_ic_irq_chip;
+-
+- qe_ic->virq_high = irq_of_parse_and_map(node, 0);
+- qe_ic->virq_low = irq_of_parse_and_map(node, 1);
+-
+- if (qe_ic->virq_low == NO_IRQ) {
+- printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
+- kfree(qe_ic);
+- return;
+- }
+-
+- /* default priority scheme is grouped. If spread mode is */
+- /* required, configure cicr accordingly. */
+- if (flags & QE_IC_SPREADMODE_GRP_W)
+- temp |= CICR_GWCC;
+- if (flags & QE_IC_SPREADMODE_GRP_X)
+- temp |= CICR_GXCC;
+- if (flags & QE_IC_SPREADMODE_GRP_Y)
+- temp |= CICR_GYCC;
+- if (flags & QE_IC_SPREADMODE_GRP_Z)
+- temp |= CICR_GZCC;
+- if (flags & QE_IC_SPREADMODE_GRP_RISCA)
+- temp |= CICR_GRTA;
+- if (flags & QE_IC_SPREADMODE_GRP_RISCB)
+- temp |= CICR_GRTB;
+-
+- /* choose destination signal for highest priority interrupt */
+- if (flags & QE_IC_HIGH_SIGNAL) {
+- temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
+- high_active = 1;
+- }
+-
+- qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
+-
+- irq_set_handler_data(qe_ic->virq_low, qe_ic);
+- irq_set_chained_handler(qe_ic->virq_low, low_handler);
+-
+- if (qe_ic->virq_high != NO_IRQ &&
+- qe_ic->virq_high != qe_ic->virq_low) {
+- irq_set_handler_data(qe_ic->virq_high, qe_ic);
+- irq_set_chained_handler(qe_ic->virq_high, high_handler);
+- }
+-}
+-
+-void qe_ic_set_highest_priority(unsigned int virq, int high)
+-{
+- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
+- unsigned int src = virq_to_hw(virq);
+- u32 temp = 0;
+-
+- temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
+-
+- temp &= ~CICR_HP_MASK;
+- temp |= src << CICR_HP_SHIFT;
+-
+- temp &= ~CICR_HPIT_MASK;
+- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
+-
+- qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
+-}
+-
+-/* Set Priority level within its group, from 1 to 8 */
+-int qe_ic_set_priority(unsigned int virq, unsigned int priority)
+-{
+- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
+- unsigned int src = virq_to_hw(virq);
+- u32 temp;
+-
+- if (priority > 8 || priority == 0)
+- return -EINVAL;
+- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
+- "%s: Invalid hw irq number for QEIC\n", __func__))
+- return -EINVAL;
+- if (qe_ic_info[src].pri_reg == 0)
+- return -EINVAL;
+-
+- temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
+-
+- if (priority < 4) {
+- temp &= ~(0x7 << (32 - priority * 3));
+- temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
+- } else {
+- temp &= ~(0x7 << (24 - priority * 3));
+- temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
+- }
+-
+- qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
+-
+- return 0;
+-}
+-
+-/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
+-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
+-{
+- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
+- unsigned int src = virq_to_hw(virq);
+- u32 temp, control_reg = QEIC_CICNR, shift = 0;
+-
+- if (priority > 2 || priority == 0)
+- return -EINVAL;
+- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
+- "%s: Invalid hw irq number for QEIC\n", __func__))
+- return -EINVAL;
+-
+- switch (qe_ic_info[src].pri_reg) {
+- case QEIC_CIPZCC:
+- shift = CICNR_ZCC1T_SHIFT;
+- break;
+- case QEIC_CIPWCC:
+- shift = CICNR_WCC1T_SHIFT;
+- break;
+- case QEIC_CIPYCC:
+- shift = CICNR_YCC1T_SHIFT;
+- break;
+- case QEIC_CIPXCC:
+- shift = CICNR_XCC1T_SHIFT;
+- break;
+- case QEIC_CIPRTA:
+- shift = CRICR_RTA1T_SHIFT;
+- control_reg = QEIC_CRICR;
+- break;
+- case QEIC_CIPRTB:
+- shift = CRICR_RTB1T_SHIFT;
+- control_reg = QEIC_CRICR;
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- shift += (2 - priority) * 2;
+- temp = qe_ic_read(qe_ic->regs, control_reg);
+- temp &= ~(SIGNAL_MASK << shift);
+- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
+- qe_ic_write(qe_ic->regs, control_reg, temp);
+-
+- return 0;
+-}
+-
+-static struct bus_type qe_ic_subsys = {
+- .name = "qe_ic",
+- .dev_name = "qe_ic",
+-};
+-
+-static struct device device_qe_ic = {
+- .id = 0,
+- .bus = &qe_ic_subsys,
+-};
+-
+-static int __init init_qe_ic_sysfs(void)
+-{
+- int rc;
+-
+- printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
+-
+- rc = subsys_system_register(&qe_ic_subsys, NULL);
+- if (rc) {
+- printk(KERN_ERR "Failed registering qe_ic sys class\n");
+- return -ENODEV;
+- }
+- rc = device_register(&device_qe_ic);
+- if (rc) {
+- printk(KERN_ERR "Failed registering qe_ic sys device\n");
+- return -ENODEV;
+- }
+- return 0;
+-}
+-
+-subsys_initcall(init_qe_ic_sysfs);
+--- /dev/null
++++ b/drivers/irqchip/irq-qeic.c
+@@ -0,0 +1,605 @@
++/*
++ * drivers/irqchip/irq-qeic.c
++ *
+ * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Author: Li Yang <leoli@freescale.com>
- * Based on code from Shlomi Gridish <gridish@freescale.com>
-@@ -18,7 +18,11 @@
- #include <linux/of_address.h>
- #include <linux/kernel.h>
- #include <linux/init.h>
++ *
++ * Author: Li Yang <leoli@freescale.com>
++ * Based on code from Shlomi Gridish <gridish@freescale.com>
++ *
++ * QUICC ENGINE Interrupt Controller
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
- #include <linux/errno.h>
++#include <linux/errno.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
- #include <linux/reboot.h>
- #include <linux/slab.h>
- #include <linux/stddef.h>
-@@ -26,11 +30,136 @@
- #include <linux/signal.h>
- #include <linux/device.h>
- #include <linux/spinlock.h>
--#include <asm/irq.h>
++#include <linux/reboot.h>
++#include <linux/slab.h>
++#include <linux/stddef.h>
++#include <linux/sched.h>
++#include <linux/signal.h>
++#include <linux/device.h>
++#include <linux/spinlock.h>
+#include <linux/irq.h>
- #include <asm/io.h>
--#include <soc/fsl/qe/qe_ic.h>
-
--#include "qe_ic.h"
++#include <asm/io.h>
++
+#define NR_QE_IC_INTS 64
+
+/* QE IC registers offset */
+ /* The remapper for this QEIC */
+ struct irq_domain *irqhost;
+
-+ /* The "linux" controller struct */
-+ struct irq_chip hc_irq;
++ /* The "linux" controller struct */
++ struct irq_chip hc_irq;
++
++ /* VIRQ numbers of QE high/low irqs */
++ unsigned int virq_high;
++ unsigned int virq_low;
++};
++
++/*
++ * QE interrupt controller internal structure
++ */
++struct qe_ic_info {
++ /* location of this source at the QIMR register. */
++ u32 mask;
++
++ /* Mask register offset */
++ u32 mask_reg;
++
++ /*
++ * for grouped interrupts sources - the interrupt
++ * code as appears at the group priority register
++ */
++ u8 pri_code;
++
++ /* Group priority register offset */
++ u32 pri_reg;
++};
++
++static DEFINE_RAW_SPINLOCK(qe_ic_lock);
++
++static struct qe_ic_info qe_ic_info[] = {
++ [1] = {
++ .mask = 0x00008000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 0,
++ .pri_reg = QEIC_CIPWCC,
++ },
++ [2] = {
++ .mask = 0x00004000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 1,
++ .pri_reg = QEIC_CIPWCC,
++ },
++ [3] = {
++ .mask = 0x00002000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 2,
++ .pri_reg = QEIC_CIPWCC,
++ },
++ [10] = {
++ .mask = 0x00000040,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 1,
++ .pri_reg = QEIC_CIPZCC,
++ },
++ [11] = {
++ .mask = 0x00000020,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 2,
++ .pri_reg = QEIC_CIPZCC,
++ },
++ [12] = {
++ .mask = 0x00000010,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 3,
++ .pri_reg = QEIC_CIPZCC,
++ },
++ [13] = {
++ .mask = 0x00000008,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 4,
++ .pri_reg = QEIC_CIPZCC,
++ },
++ [14] = {
++ .mask = 0x00000004,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 5,
++ .pri_reg = QEIC_CIPZCC,
++ },
++ [15] = {
++ .mask = 0x00000002,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 6,
++ .pri_reg = QEIC_CIPZCC,
++ },
++ [20] = {
++ .mask = 0x10000000,
++ .mask_reg = QEIC_CRIMR,
++ .pri_code = 3,
++ .pri_reg = QEIC_CIPRTA,
++ },
++ [25] = {
++ .mask = 0x00800000,
++ .mask_reg = QEIC_CRIMR,
++ .pri_code = 0,
++ .pri_reg = QEIC_CIPRTB,
++ },
++ [26] = {
++ .mask = 0x00400000,
++ .mask_reg = QEIC_CRIMR,
++ .pri_code = 1,
++ .pri_reg = QEIC_CIPRTB,
++ },
++ [27] = {
++ .mask = 0x00200000,
++ .mask_reg = QEIC_CRIMR,
++ .pri_code = 2,
++ .pri_reg = QEIC_CIPRTB,
++ },
++ [28] = {
++ .mask = 0x00100000,
++ .mask_reg = QEIC_CRIMR,
++ .pri_code = 3,
++ .pri_reg = QEIC_CIPRTB,
++ },
++ [32] = {
++ .mask = 0x80000000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 0,
++ .pri_reg = QEIC_CIPXCC,
++ },
++ [33] = {
++ .mask = 0x40000000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 1,
++ .pri_reg = QEIC_CIPXCC,
++ },
++ [34] = {
++ .mask = 0x20000000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 2,
++ .pri_reg = QEIC_CIPXCC,
++ },
++ [35] = {
++ .mask = 0x10000000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 3,
++ .pri_reg = QEIC_CIPXCC,
++ },
++ [36] = {
++ .mask = 0x08000000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 4,
++ .pri_reg = QEIC_CIPXCC,
++ },
++ [40] = {
++ .mask = 0x00800000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 0,
++ .pri_reg = QEIC_CIPYCC,
++ },
++ [41] = {
++ .mask = 0x00400000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 1,
++ .pri_reg = QEIC_CIPYCC,
++ },
++ [42] = {
++ .mask = 0x00200000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 2,
++ .pri_reg = QEIC_CIPYCC,
++ },
++ [43] = {
++ .mask = 0x00100000,
++ .mask_reg = QEIC_CIMR,
++ .pri_code = 3,
++ .pri_reg = QEIC_CIPYCC,
++ },
++};
++
++static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
++{
++ return ioread32be(base + (reg >> 2));
++}
++
++static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
++ u32 value)
++{
++ iowrite32be(value, base + (reg >> 2));
++}
++
++static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
++{
++ return irq_get_chip_data(virq);
++}
++
++static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
++{
++ return irq_data_get_irq_chip_data(d);
++}
++
++static void qe_ic_unmask_irq(struct irq_data *d)
++{
++ struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
++ unsigned int src = irqd_to_hwirq(d);
++ unsigned long flags;
++ u32 temp;
++
++ raw_spin_lock_irqsave(&qe_ic_lock, flags);
++
++ temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
++ qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
++ temp | qe_ic_info[src].mask);
++
++ raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
++}
++
++static void qe_ic_mask_irq(struct irq_data *d)
++{
++ struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
++ unsigned int src = irqd_to_hwirq(d);
++ unsigned long flags;
++ u32 temp;
++
++ raw_spin_lock_irqsave(&qe_ic_lock, flags);
++
++ temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
++ qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
++ temp & ~qe_ic_info[src].mask);
++
++ /* Flush the above write before enabling interrupts; otherwise,
++ * spurious interrupts will sometimes happen. To be 100% sure
++ * that the write has reached the device before interrupts are
++ * enabled, the mask register would have to be read back; however,
++ * this is not required for correctness, only to avoid wasting
++ * time on a large number of spurious interrupts. In testing,
++ * a sync reduced the observed spurious interrupts to zero.
++ */
++ mb();
++
++ raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
++}
++
++static struct irq_chip qe_ic_irq_chip = {
++ .name = "QEIC",
++ .irq_unmask = qe_ic_unmask_irq,
++ .irq_mask = qe_ic_mask_irq,
++ .irq_mask_ack = qe_ic_mask_irq,
++};
++
++static int qe_ic_host_match(struct irq_domain *h, struct device_node *node,
++ enum irq_domain_bus_token bus_token)
++{
++ /* Exact match, unless qe_ic node is NULL */
++ struct device_node *of_node = irq_domain_get_of_node(h);
++ return of_node == NULL || of_node == node;
++}
++
++static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,
++ irq_hw_number_t hw)
++{
++ struct qe_ic *qe_ic = h->host_data;
++ struct irq_chip *chip;
++
++ if (hw >= ARRAY_SIZE(qe_ic_info)) {
++ pr_err("%s: Invalid hw irq number for QEIC\n", __func__);
++ return -EINVAL;
++ }
+
-+ /* VIRQ numbers of QE high/low irqs */
-+ unsigned int virq_high;
-+ unsigned int virq_low;
-+};
++ if (qe_ic_info[hw].mask == 0) {
++ printk(KERN_ERR "Can't map reserved IRQ\n");
++ return -EINVAL;
++ }
++ /* Default chip */
++ chip = &qe_ic->hc_irq;
+
-+/*
-+ * QE interrupt controller internal structure
-+ */
-+struct qe_ic_info {
-+ /* location of this source at the QIMR register. */
-+ u32 mask;
++ irq_set_chip_data(virq, qe_ic);
++ irq_set_status_flags(virq, IRQ_LEVEL);
+
-+ /* Mask register offset */
-+ u32 mask_reg;
++ irq_set_chip_and_handler(virq, chip, handle_level_irq);
+
-+ /*
-+ * for grouped interrupts sources - the interrupt
-+ * code as appears at the group priority register
-+ */
-+ u8 pri_code;
++ return 0;
++}
+
-+ /* Group priority register offset */
-+ u32 pri_reg;
++static const struct irq_domain_ops qe_ic_host_ops = {
++ .match = qe_ic_host_match,
++ .map = qe_ic_host_map,
++ .xlate = irq_domain_xlate_onetwocell,
+};
-
- static DEFINE_RAW_SPINLOCK(qe_ic_lock);
-
-@@ -175,15 +304,15 @@ static struct qe_ic_info qe_ic_info[] = {
- },
- };
-
--static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
-+static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
- {
-- return in_be32(base + (reg >> 2));
-+ return ioread32be(base + (reg >> 2));
- }
-
--static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
-+static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
- u32 value)
- {
-- out_be32(base + (reg >> 2), value);
-+ iowrite32be(value, base + (reg >> 2));
- }
-
- static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
-@@ -285,8 +414,8 @@ static const struct irq_domain_ops qe_ic_host_ops = {
- .xlate = irq_domain_xlate_onetwocell,
- };
-
--/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
--unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
++
+/* Return an interrupt vector or 0 if no interrupt is pending. */
+static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
- {
- int irq;
-
-@@ -296,13 +425,13 @@ unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
- irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
-
- if (irq == 0)
-- return NO_IRQ;
++{
++ int irq;
++
++ BUG_ON(qe_ic == NULL);
++
++ /* get the interrupt source vector. */
++ irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
++
++ if (irq == 0)
+ return 0;
-
- return irq_linear_revmap(qe_ic->irqhost, irq);
- }
-
--/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
--unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
++
++ return irq_linear_revmap(qe_ic->irqhost, irq);
++}
++
+/* Return an interrupt vector or 0 if no interrupt is pending. */
+static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
- {
- int irq;
-
-@@ -312,32 +441,96 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
- irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
-
- if (irq == 0)
-- return NO_IRQ;
++{
++ int irq;
++
++ BUG_ON(qe_ic == NULL);
++
++ /* get the interrupt source vector. */
++ irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
++
++ if (irq == 0)
+ return 0;
-
- return irq_linear_revmap(qe_ic->irqhost, irq);
- }
-
--void __init qe_ic_init(struct device_node *node, unsigned int flags,
-- void (*low_handler)(struct irq_desc *desc),
-- void (*high_handler)(struct irq_desc *desc))
++
++ return irq_linear_revmap(qe_ic->irqhost, irq);
++}
++
+static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+}
+
+static int __init qe_ic_init(struct device_node *node, unsigned int flags)
- {
- struct qe_ic *qe_ic;
- struct resource res;
-- u32 temp = 0, ret, high_active = 0;
++{
++ struct qe_ic *qe_ic;
++ struct resource res;
+ u32 temp = 0, high_active = 0;
+ int ret = 0;
+
+ if (!node)
+ return -ENODEV;
-
- ret = of_address_to_resource(node, 0, &res);
-- if (ret)
-- return;
++
++ ret = of_address_to_resource(node, 0, &res);
+ if (ret) {
+ ret = -ENODEV;
+ goto err_put_node;
+ }
-
- qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
-- if (qe_ic == NULL)
-- return;
++
++ qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
+ if (qe_ic == NULL) {
+ ret = -ENOMEM;
+ goto err_put_node;
+ }
-
- qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
- &qe_ic_host_ops, qe_ic);
- if (qe_ic->irqhost == NULL) {
-- kfree(qe_ic);
-- return;
++
++ qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
++ &qe_ic_host_ops, qe_ic);
++ if (qe_ic->irqhost == NULL) {
+ ret = -ENOMEM;
+ goto err_free_qe_ic;
- }
-
- qe_ic->regs = ioremap(res.start, resource_size(&res));
-@@ -347,10 +540,10 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
- qe_ic->virq_high = irq_of_parse_and_map(node, 0);
- qe_ic->virq_low = irq_of_parse_and_map(node, 1);
-
-- if (qe_ic->virq_low == NO_IRQ) {
-- printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
-- kfree(qe_ic);
-- return;
++ }
++
++ qe_ic->regs = ioremap(res.start, resource_size(&res));
++
++ qe_ic->hc_irq = qe_ic_irq_chip;
++
++ qe_ic->virq_high = irq_of_parse_and_map(node, 0);
++ qe_ic->virq_low = irq_of_parse_and_map(node, 1);
++
+ if (qe_ic->virq_low == 0) {
+ pr_err("Failed to map QE_IC low IRQ\n");
+ ret = -ENOMEM;
+ goto err_domain_remove;
- }
-
- /* default priority scheme is grouped. If spread mode is */
-@@ -377,136 +570,36 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
- qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
-
- irq_set_handler_data(qe_ic->virq_low, qe_ic);
-- irq_set_chained_handler(qe_ic->virq_low, low_handler);
++ }
++
++ /* default priority scheme is grouped. If spread mode is */
++ /* required, configure cicr accordingly. */
++ if (flags & QE_IC_SPREADMODE_GRP_W)
++ temp |= CICR_GWCC;
++ if (flags & QE_IC_SPREADMODE_GRP_X)
++ temp |= CICR_GXCC;
++ if (flags & QE_IC_SPREADMODE_GRP_Y)
++ temp |= CICR_GYCC;
++ if (flags & QE_IC_SPREADMODE_GRP_Z)
++ temp |= CICR_GZCC;
++ if (flags & QE_IC_SPREADMODE_GRP_RISCA)
++ temp |= CICR_GRTA;
++ if (flags & QE_IC_SPREADMODE_GRP_RISCB)
++ temp |= CICR_GRTB;
++
++ /* choose destination signal for highest priority interrupt */
++ if (flags & QE_IC_HIGH_SIGNAL) {
++ temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
++ high_active = 1;
++ }
++
++ qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
++
++ irq_set_handler_data(qe_ic->virq_low, qe_ic);
+ irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
-
-- if (qe_ic->virq_high != NO_IRQ &&
++
+ if (qe_ic->virq_high != 0 &&
- qe_ic->virq_high != qe_ic->virq_low) {
- irq_set_handler_data(qe_ic->virq_high, qe_ic);
-- irq_set_chained_handler(qe_ic->virq_high, high_handler);
-- }
--}
--
--void qe_ic_set_highest_priority(unsigned int virq, int high)
--{
-- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
-- unsigned int src = virq_to_hw(virq);
-- u32 temp = 0;
--
-- temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
--
-- temp &= ~CICR_HP_MASK;
-- temp |= src << CICR_HP_SHIFT;
--
-- temp &= ~CICR_HPIT_MASK;
-- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
--
-- qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
--}
--
--/* Set Priority level within its group, from 1 to 8 */
--int qe_ic_set_priority(unsigned int virq, unsigned int priority)
--{
-- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
-- unsigned int src = virq_to_hw(virq);
-- u32 temp;
--
-- if (priority > 8 || priority == 0)
-- return -EINVAL;
-- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
-- "%s: Invalid hw irq number for QEIC\n", __func__))
-- return -EINVAL;
-- if (qe_ic_info[src].pri_reg == 0)
-- return -EINVAL;
--
-- temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
--
-- if (priority < 4) {
-- temp &= ~(0x7 << (32 - priority * 3));
-- temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
-- } else {
-- temp &= ~(0x7 << (24 - priority * 3));
-- temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
++ qe_ic->virq_high != qe_ic->virq_low) {
++ irq_set_handler_data(qe_ic->virq_high, qe_ic);
+ irq_set_chained_handler(qe_ic->virq_high,
+ qe_ic_cascade_high_mpic);
- }
--
-- qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
--
++ }
+ of_node_put(node);
- return 0;
--}
--
--/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
--int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
--{
-- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
-- unsigned int src = virq_to_hw(virq);
-- u32 temp, control_reg = QEIC_CICNR, shift = 0;
--
-- if (priority > 2 || priority == 0)
-- return -EINVAL;
-- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
-- "%s: Invalid hw irq number for QEIC\n", __func__))
-- return -EINVAL;
--
-- switch (qe_ic_info[src].pri_reg) {
-- case QEIC_CIPZCC:
-- shift = CICNR_ZCC1T_SHIFT;
-- break;
-- case QEIC_CIPWCC:
-- shift = CICNR_WCC1T_SHIFT;
-- break;
-- case QEIC_CIPYCC:
-- shift = CICNR_YCC1T_SHIFT;
-- break;
-- case QEIC_CIPXCC:
-- shift = CICNR_XCC1T_SHIFT;
-- break;
-- case QEIC_CIPRTA:
-- shift = CRICR_RTA1T_SHIFT;
-- control_reg = QEIC_CRICR;
-- break;
-- case QEIC_CIPRTB:
-- shift = CRICR_RTB1T_SHIFT;
-- control_reg = QEIC_CRICR;
-- break;
-- default:
-- return -EINVAL;
-- }
--
-- shift += (2 - priority) * 2;
-- temp = qe_ic_read(qe_ic->regs, control_reg);
-- temp &= ~(SIGNAL_MASK << shift);
-- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
-- qe_ic_write(qe_ic->regs, control_reg, temp);
-
-- return 0;
++ return 0;
++
+err_domain_remove:
+ irq_domain_remove(qe_ic->irqhost);
+err_free_qe_ic:
+err_put_node:
+ of_node_put(node);
+ return ret;
- }
-
--static struct bus_type qe_ic_subsys = {
-- .name = "qe_ic",
-- .dev_name = "qe_ic",
--};
--
--static struct device device_qe_ic = {
-- .id = 0,
-- .bus = &qe_ic_subsys,
--};
--
--static int __init init_qe_ic_sysfs(void)
++}
++
+static int __init init_qe_ic(struct device_node *node,
+ struct device_node *parent)
- {
-- int rc;
++{
+ int ret;
-
-- printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
++
+ ret = qe_ic_init(node, 0);
+ if (ret)
+ return ret;
-
-- rc = subsys_system_register(&qe_ic_subsys, NULL);
-- if (rc) {
-- printk(KERN_ERR "Failed registering qe_ic sys class\n");
-- return -ENODEV;
-- }
-- rc = device_register(&device_qe_ic);
-- if (rc) {
-- printk(KERN_ERR "Failed registering qe_ic sys device\n");
-- return -ENODEV;
-- }
- return 0;
- }
-
--subsys_initcall(init_qe_ic_sysfs);
++
++ return 0;
++}
++
+IRQCHIP_DECLARE(qeic, "fsl,qe-ic", init_qe_ic);
-diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
-index 65647533..27e11404 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.c
+++ b/drivers/net/wan/fsl_ucc_hdlc.c
-@@ -381,8 +381,8 @@ static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
+@@ -381,8 +381,8 @@ static netdev_tx_t ucc_hdlc_tx(struct sk
/* set bd status and length */
bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
/* Move to next BD in the ring */
if (!(bd_status & T_W_S))
-@@ -457,7 +457,7 @@ static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
+@@ -457,7 +457,7 @@ static int hdlc_rx_done(struct ucc_hdlc_
struct sk_buff *skb;
hdlc_device *hdlc = dev_to_hdlc(dev);
struct qe_bd *bd;
u16 length, howmany = 0;
u8 *bdbuffer;
int i;
-diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
-index 73a2e08b..b26b6431 100644
--- a/drivers/soc/fsl/qe/Kconfig
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -4,7 +4,7 @@
select GENERIC_ALLOCATOR
select CRC32
help
-diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
-index 2031d385..51e47264 100644
--- a/drivers/soc/fsl/qe/Makefile
+++ b/drivers/soc/fsl/qe/Makefile
@@ -1,7 +1,7 @@
obj-$(CONFIG_CPM) += qe_common.o
obj-$(CONFIG_UCC) += ucc.o
obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
-diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
-index 2707a827..2b53e852 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -33,8 +33,6 @@
} else {
if (cmd == QE_ASSIGN_PAGE) {
/* Here device is the SNUM, not sub-block */
-@@ -134,20 +144,26 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
+@@ -134,20 +144,26 @@ int qe_issue_cmd(u32 cmd, u32 device, u8
mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
}
of_node_put(qe);
-@@ -221,7 +237,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
+@@ -221,7 +237,7 @@ int qe_setbrg(enum qe_clock brg, unsigne
tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
QE_BRGC_ENABLE | div16;
return 0;
}
-@@ -395,14 +411,14 @@ static void qe_upload_microcode(const void *base,
+@@ -395,14 +411,14 @@ static void qe_upload_microcode(const vo
"uploading microcode '%s'\n", ucode->id);
/* Use auto-increment */
}
/*
-@@ -487,7 +503,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
+@@ -487,7 +503,7 @@ int qe_upload_firmware(const struct qe_f
* If the microcode calls for it, split the I-RAM.
*/
if (!firmware->split)
if (firmware->soc.model)
printk(KERN_INFO
-@@ -521,11 +537,11 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
+@@ -521,11 +537,11 @@ int qe_upload_firmware(const struct qe_f
u32 trap = be32_to_cpu(ucode->traps[j]);
if (trap)
if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
/* No QE ever has fewer than 28 SNUMs */
pr_err("QE: number of snum is invalid\n");
-diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
-deleted file mode 100644
-index 926a2ed4..00000000
--- a/drivers/soc/fsl/qe/qe_ic.h
+++ /dev/null
@@ -1,103 +0,0 @@
-};
-
-#endif /* _POWERPC_SYSDEV_QE_IC_H */
-diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
-index 7ae59abc..8966e8b6 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b/drivers/soc/fsl/qe/qe_io.c
@@ -22,8 +22,6 @@
#undef DEBUG
-@@ -61,16 +59,16 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
+@@ -61,16 +59,16 @@ void __par_io_config_pin(struct qe_pio_r
pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
/* Set open drain, if required */
/* get all bits mask for 2 bit per port */
pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
-@@ -82,34 +80,30 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
+@@ -82,34 +80,30 @@ void __par_io_config_pin(struct qe_pio_r
/* clear and set 2 bits mask */
if (pin > (QE_PIO_PINS / 2) - 1) {
}
}
EXPORT_SYMBOL(__par_io_config_pin);
-@@ -137,12 +131,12 @@ int par_io_data_set(u8 port, u8 pin, u8 val)
+@@ -137,12 +131,12 @@ int par_io_data_set(u8 port, u8 pin, u8
/* calculate pin location */
pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
return 0;
}
-diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
-index a1048b44..818e6798 100644
--- a/drivers/soc/fsl/qe/qe_tdm.c
+++ b/drivers/soc/fsl/qe/qe_tdm.c
-@@ -227,10 +227,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
+@@ -227,10 +227,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm,
&siram[siram_entry_id * 32 + 0x200 + i]);
}
/* Set SIxMR register */
sixmr = SIMR_SAD(siram_entry_id);
-diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c
-index c646d871..bc64b834 100644
--- a/drivers/soc/fsl/qe/ucc.c
+++ b/drivers/soc/fsl/qe/ucc.c
-@@ -39,7 +39,7 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
+@@ -39,7 +39,7 @@ int ucc_set_qe_mux_mii_mng(unsigned int
return -EINVAL;
spin_lock_irqsave(&cmxgcr_lock, flags);
ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
spin_unlock_irqrestore(&cmxgcr_lock, flags);
-@@ -84,7 +84,7 @@ int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
+@@ -84,7 +84,7 @@ int ucc_set_type(unsigned int ucc_num, e
return -EINVAL;
}
UCC_GUEMR_SET_RESERVED3 | speed);
return 0;
-@@ -113,9 +113,9 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
+@@ -113,9 +113,9 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned
get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
if (set)
return 0;
}
-@@ -211,7 +211,7 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
+@@ -211,7 +211,7 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc
if (mode == COMM_DIR_RX)
shift += 4;
clock_bits << shift);
return 0;
-diff --git a/drivers/soc/fsl/qe/ucc_fast.c b/drivers/soc/fsl/qe/ucc_fast.c
-index 83d8d16e..5115e935 100644
--- a/drivers/soc/fsl/qe/ucc_fast.c
+++ b/drivers/soc/fsl/qe/ucc_fast.c
-@@ -33,41 +33,41 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
+@@ -33,41 +33,41 @@ void ucc_fast_dump_regs(struct ucc_fast_
printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
}
EXPORT_SYMBOL(ucc_fast_dump_regs);
-@@ -89,7 +89,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);
+@@ -89,7 +89,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subbloc
void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
{
}
EXPORT_SYMBOL(ucc_fast_transmit_on_demand);
-@@ -101,7 +101,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
+@@ -101,7 +101,7 @@ void ucc_fast_enable(struct ucc_fast_pri
uf_regs = uccf->uf_regs;
/* Enable reception and/or transmission on this UCC. */
if (mode & COMM_DIR_TX) {
gumr |= UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 1;
-@@ -110,7 +110,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
+@@ -110,7 +110,7 @@ void ucc_fast_enable(struct ucc_fast_pri
gumr |= UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 1;
}
}
EXPORT_SYMBOL(ucc_fast_enable);
-@@ -122,7 +122,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
+@@ -122,7 +122,7 @@ void ucc_fast_disable(struct ucc_fast_pr
uf_regs = uccf->uf_regs;
/* Disable reception and/or transmission on this UCC. */
if (mode & COMM_DIR_TX) {
gumr &= ~UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 0;
-@@ -131,7 +131,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
+@@ -131,7 +131,7 @@ void ucc_fast_disable(struct ucc_fast_pr
gumr &= ~UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 0;
}
}
EXPORT_SYMBOL(ucc_fast_disable);
-@@ -263,12 +263,13 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
+@@ -263,12 +263,13 @@ int ucc_fast_init(struct ucc_fast_info *
gumr |= uf_info->tenc;
gumr |= uf_info->tcrc;
gumr |= uf_info->mode;
printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
__func__);
uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
-@@ -281,7 +282,8 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
+@@ -281,7 +282,8 @@ int ucc_fast_init(struct ucc_fast_info *
qe_muram_alloc(uf_info->urfs +
UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
__func__);
uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
-@@ -290,15 +292,15 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
+@@ -290,15 +292,15 @@ int ucc_fast_init(struct ucc_fast_info *
}
/* Set Virtual Fifo registers */
/* Mux clocking */
/* Grant Support */
-@@ -366,14 +368,14 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
+@@ -366,14 +368,14 @@ int ucc_fast_init(struct ucc_fast_info *
}
/* Set interrupt mask register at UCC level. */
*uccf_ret = uccf;
return 0;
-diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
-index 481eb298..ee409fdf 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -34,6 +34,7 @@
#include <asm/reg.h>
/*
-diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
-index 70339d79..f7a14f2d 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -21,7 +21,6 @@
#include <soc/fsl/qe/immap_qe.h>
#include <linux/of.h>
#include <linux/of_address.h>
-diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
-deleted file mode 100644
-index 1e155ca6..00000000
--- a/include/soc/fsl/qe/qe_ic.h
+++ /dev/null
@@ -1,139 +0,0 @@
-}
-
-#endif /* _ASM_POWERPC_QE_IC_H */
---
-2.14.1
-
projects / openwrt / staging / hauke.git / blobdiff