/*
- * Platform driver for the Realtek RTL8366S ethernet switch
+ * Platform driver for the Realtek RTL8366RB ethernet switch
*
* Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
+ * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
+ * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
-#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
#include <linux/delay.h>
#include <linux/skbuff.h>
-#include <linux/rtl8366rb.h>
+#include <linux/rtl8366.h>
#include "rtl8366_smi.h"
#define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
-#define RTL8366RB_DRIVER_VER "0.2.2"
+#define RTL8366RB_DRIVER_VER "0.2.4"
#define RTL8366RB_PHY_NO_MAX 4
#define RTL8366RB_PHY_PAGE_MAX 7
/* Port Enable Control register */
#define RTL8366RB_PECR 0x0001
+/* Port Mirror Control Register */
+#define RTL8366RB_PMCR 0x0007
+#define RTL8366RB_PMCR_SOURCE_PORT(_x) (_x)
+#define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f
+#define RTL8366RB_PMCR_MONITOR_PORT(_x) ((_x) << 4)
+#define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0
+#define RTL8366RB_PMCR_MIRROR_RX BIT(8)
+#define RTL8366RB_PMCR_MIRROR_TX BIT(9)
+#define RTL8366RB_PMCR_MIRROR_SPC BIT(10)
+#define RTL8366RB_PMCR_MIRROR_ISO BIT(11)
+
/* Switch Security Control registers */
#define RTL8366RB_SSCR0 0x0002
#define RTL8366RB_SSCR1 0x0003
#define RTL8366RB_VLAN_MEMBER_MASK 0xff
#define RTL8366RB_VLAN_FID_MASK 0x7
+
+/* Port ingress bandwidth control */
+#define RTL8366RB_IB_BASE 0x0200
+#define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum)
+#define RTL8366RB_IB_BDTH_MASK 0x3fff
+#define RTL8366RB_IB_PREIFG_OFFSET 14
+#define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET)
+
+/* Port egress bandwidth control */
+#define RTL8366RB_EB_BASE 0x02d1
+#define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum)
+#define RTL8366RB_EB_BDTH_MASK 0x3fff
+#define RTL8366RB_EB_PREIFG_REG 0x02f8
+#define RTL8366RB_EB_PREIFG_OFFSET 9
+#define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET)
+
+#define RTL8366RB_BDTH_SW_MAX 1048512
+#define RTL8366RB_BDTH_UNIT 64
+#define RTL8366RB_BDTH_REG_DEFAULT 16383
+
+/* QOS */
+#define RTL8366RB_QOS_BIT 15
+#define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT)
+/* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
+#define RTL8366RB_QOS_DEFAULT_PREIFG 1
+
+
static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
{ 0, 0, 4, "IfInOctets" },
{ 0, 4, 4, "EtherStatsOctets" },
int timeout = 10;
u32 data;
- rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
- RTL8366RB_CHIP_CTRL_RESET_HW);
+ rtl8366_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,
+ RTL8366RB_CHIP_CTRL_RESET_HW);
do {
msleep(1);
if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
return 0;
}
-static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
+static int rtl8366rb_setup(struct rtl8366_smi *smi)
{
int err;
+#ifdef CONFIG_OF
+ unsigned i;
+ struct device_node *np;
+ unsigned num_initvals;
+ const __be32 *paddr;
+
+ np = smi->parent->of_node;
+
+ paddr = of_get_property(np, "realtek,initvals", &num_initvals);
+ if (paddr) {
+ dev_info(smi->parent, "applying initvals from DTS\n");
+
+ if (num_initvals < (2 * sizeof(*paddr)))
+ return -EINVAL;
+
+ num_initvals /= sizeof(*paddr);
+
+ for (i = 0; i < num_initvals - 1; i += 2) {
+ u32 reg = be32_to_cpup(paddr + i);
+ u32 val = be32_to_cpup(paddr + i + 1);
+
+ REG_WR(smi, reg, val);
+ }
+ }
+#endif
/* set maximum packet length to 1536 bytes */
REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
RTL8366RB_SGCR_MAX_LENGTH_1536);
- /* enable all ports */
- REG_WR(smi, RTL8366RB_PECR, 0);
-
/* enable learning for all ports */
REG_WR(smi, RTL8366RB_SSCR0, 0);
int i;
if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
- vlan4k->member > RTL8366RB_PORT_ALL ||
- vlan4k->untag > RTL8366RB_PORT_ALL ||
+ vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
+ vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
vlan4k->fid > RTL8366RB_FIDMAX)
return -EINVAL;
if (index >= RTL8366RB_NUM_VLANS ||
vlanmc->vid >= RTL8366RB_NUM_VIDS ||
vlanmc->priority > RTL8366RB_PRIORITYMAX ||
- vlanmc->member > RTL8366RB_PORT_ALL ||
- vlanmc->untag > RTL8366RB_PORT_ALL ||
+ vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
+ vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
vlanmc->fid > RTL8366RB_FIDMAX)
return -EINVAL;
static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
{
- if (vlan == 0 || vlan >= RTL8366RB_NUM_VLANS)
+ unsigned max = RTL8366RB_NUM_VLANS;
+
+ if (smi->vlan4k_enabled)
+ max = RTL8366RB_NUM_VIDS - 1;
+
+ if (vlan == 0 || vlan >= max)
return 0;
return 1;
}
-static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
+static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
{
return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
(enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
}
-static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
+static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
{
return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
RTL8366RB_SGCR_EN_VLAN_4KTB,
(enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
}
+static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)
+{
+ return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),
+ (enable) ? 0 : (1 << port));
+}
+
static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
RTL8366RB_MIB_CTRL_GLOBAL_RESET);
}
-static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
- const struct switch_attr *attr,
- struct switch_val *val)
-{
- struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
- u32 data;
-
- if (attr->ofs == 1) {
- rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
-
- if (data & RTL8366RB_SGCR_EN_VLAN)
- val->value.i = 1;
- else
- val->value.i = 0;
- } else if (attr->ofs == 2) {
- rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
-
- if (data & RTL8366RB_SGCR_EN_VLAN_4KTB)
- val->value.i = 1;
- else
- val->value.i = 0;
- }
-
- return 0;
-}
-
static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
val->value.i);
}
-static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
- const struct switch_attr *attr,
- struct switch_val *val)
-{
- struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
-
- if (attr->ofs == 1)
- return rtl8366rb_vlan_set_vlan(smi, val->value.i);
- else
- return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
-}
-
static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
return 0;
}
-
-static const char *rtl8366rb_speed_str(unsigned speed)
-{
- switch (speed) {
- case 0:
- return "10baseT";
- case 1:
- return "100baseT";
- case 2:
- return "1000baseT";
- }
-
- return "unknown";
-}
-
static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
- const struct switch_attr *attr,
- struct switch_val *val)
+ int port,
+ struct switch_port_link *link)
{
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
- u32 len = 0, data = 0;
+ u32 data = 0;
+ u32 speed;
- if (val->port_vlan >= RTL8366RB_NUM_PORTS)
+ if (port >= RTL8366RB_NUM_PORTS)
return -EINVAL;
- memset(smi->buf, '\0', sizeof(smi->buf));
- rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
- (val->port_vlan / 2), &data);
+ rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + (port / 2),
+ &data);
- if (val->port_vlan % 2)
+ if (port % 2)
data = data >> 8;
- if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
- len = snprintf(smi->buf, sizeof(smi->buf),
- "port:%d link:up speed:%s %s-duplex %s%s%s",
- val->port_vlan,
- rtl8366rb_speed_str(data &
- RTL8366RB_PORT_STATUS_SPEED_MASK),
- (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
- "full" : "half",
- (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
- "tx-pause ": "",
- (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
- "rx-pause " : "",
- (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
- "nway ": "");
- } else {
- len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
- val->port_vlan);
- }
+ link->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK);
+ if (!link->link)
+ return 0;
- val->value.s = smi->buf;
- val->len = len;
+ link->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK);
+ link->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK);
+ link->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK);
+ link->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK);
+
+ speed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK);
+ switch (speed) {
+ case 0:
+ link->speed = SWITCH_PORT_SPEED_10;
+ break;
+ case 1:
+ link->speed = SWITCH_PORT_SPEED_100;
+ break;
+ case 2:
+ link->speed = SWITCH_PORT_SPEED_1000;
+ break;
+ default:
+ link->speed = SWITCH_PORT_SPEED_UNKNOWN;
+ break;
+ }
return 0;
}
data = val->value.i << (val->port_vlan * 4);
}
- return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
+ return rtl8366_smi_rmwr(smi, reg, mask, data);
}
static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
return 0;
}
-static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
- const struct switch_attr *attr,
- struct switch_val *val)
+static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
{
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 mask, data;
if (val->port_vlan >= RTL8366RB_NUM_PORTS)
return -EINVAL;
- return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
- RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
+ mask = 1 << val->port_vlan ;
+ if (val->value.i)
+ data = mask;
+ else
+ data = 0;
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
}
-static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
+static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
{
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
- int err;
+ u32 data;
- err = rtl8366rb_reset_chip(smi);
- if (err)
- return err;
+ if (val->port_vlan >= RTL8366RB_NUM_PORTS)
+ return -EINVAL;
- err = rtl8366rb_hw_init(smi);
- if (err)
- return err;
+ rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
+ if (data & (1 << val->port_vlan))
+ val->value.i = 1;
+ else
+ val->value.i = 0;
- return rtl8366_reset_vlan(smi);
+ return 0;
+}
+
+static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+
+ if (val->port_vlan >= RTL8366RB_NUM_PORTS)
+ return -EINVAL;
+
+ if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
+ val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
+ else
+ val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
+ RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
+ val->value.i |
+ (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
+
+}
+
+static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ if (val->port_vlan >= RTL8366RB_NUM_PORTS)
+ return -EINVAL;
+
+ rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
+ data &= RTL8366RB_IB_BDTH_MASK;
+ if (data < RTL8366RB_IB_BDTH_MASK)
+ data += 1;
+
+ val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
+
+ return 0;
+}
+
+static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+
+ if (val->port_vlan >= RTL8366RB_NUM_PORTS)
+ return -EINVAL;
+
+ rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
+ RTL8366RB_EB_PREIFG_MASK,
+ (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
+
+ if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
+ val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
+ else
+ val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
+ RTL8366RB_EB_BDTH_MASK, val->value.i );
+
+}
+
+static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ if (val->port_vlan >= RTL8366RB_NUM_PORTS)
+ return -EINVAL;
+
+ rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
+ data &= RTL8366RB_EB_BDTH_MASK;
+ if (data < RTL8366RB_EB_BDTH_MASK)
+ data += 1;
+
+ val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
+
+ return 0;
+}
+
+static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ if (val->value.i)
+ data = RTL8366RB_QOS_MASK;
+ else
+ data = 0;
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
+}
+
+static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
+ if (data & RTL8366RB_QOS_MASK)
+ val->value.i = 1;
+ else
+ val->value.i = 0;
+
+ return 0;
+}
+
+static int rtl8366rb_sw_set_mirror_rx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ if (val->value.i)
+ data = RTL8366RB_PMCR_MIRROR_RX;
+ else
+ data = 0;
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_RX, data);
+}
+
+static int rtl8366rb_sw_get_mirror_rx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
+ if (data & RTL8366RB_PMCR_MIRROR_RX)
+ val->value.i = 1;
+ else
+ val->value.i = 0;
+
+ return 0;
+}
+
+static int rtl8366rb_sw_set_mirror_tx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ if (val->value.i)
+ data = RTL8366RB_PMCR_MIRROR_TX;
+ else
+ data = 0;
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_TX, data);
+}
+
+static int rtl8366rb_sw_get_mirror_tx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
+ if (data & RTL8366RB_PMCR_MIRROR_TX)
+ val->value.i = 1;
+ else
+ val->value.i = 0;
+
+ return 0;
+}
+
+static int rtl8366rb_sw_set_monitor_isolation_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ if (val->value.i)
+ data = RTL8366RB_PMCR_MIRROR_ISO;
+ else
+ data = 0;
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_ISO, data);
+}
+
+static int rtl8366rb_sw_get_monitor_isolation_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
+ if (data & RTL8366RB_PMCR_MIRROR_ISO)
+ val->value.i = 1;
+ else
+ val->value.i = 0;
+
+ return 0;
+}
+
+static int rtl8366rb_sw_set_mirror_pause_frames_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ if (val->value.i)
+ data = RTL8366RB_PMCR_MIRROR_SPC;
+ else
+ data = 0;
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_SPC, data);
+}
+
+static int rtl8366rb_sw_get_mirror_pause_frames_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
+ if (data & RTL8366RB_PMCR_MIRROR_SPC)
+ val->value.i = 1;
+ else
+ val->value.i = 0;
+
+ return 0;
+}
+
+static int rtl8366rb_sw_set_mirror_monitor_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ data = RTL8366RB_PMCR_MONITOR_PORT(val->value.i);
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MONITOR_PORT_MASK, data);
+}
+
+static int rtl8366rb_sw_get_mirror_monitor_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
+ val->value.i = (data & RTL8366RB_PMCR_MONITOR_PORT_MASK) >> 4;
+
+ return 0;
+}
+
+static int rtl8366rb_sw_set_mirror_source_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ data = RTL8366RB_PMCR_SOURCE_PORT(val->value.i);
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_SOURCE_PORT_MASK, data);
+}
+
+static int rtl8366rb_sw_get_mirror_source_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+ u32 data;
+
+ rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
+ val->value.i = data & RTL8366RB_PMCR_SOURCE_PORT_MASK;
+
+ return 0;
+}
+
+static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
+
+ if (val->port_vlan >= RTL8366RB_NUM_PORTS)
+ return -EINVAL;
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
+ RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
}
static struct switch_attr rtl8366rb_globals[] = {
.type = SWITCH_TYPE_INT,
.name = "enable_vlan",
.description = "Enable VLAN mode",
- .set = rtl8366rb_sw_set_vlan_enable,
- .get = rtl8366rb_sw_get_vlan_enable,
+ .set = rtl8366_sw_set_vlan_enable,
+ .get = rtl8366_sw_get_vlan_enable,
.max = 1,
.ofs = 1
}, {
.type = SWITCH_TYPE_INT,
.name = "enable_vlan4k",
.description = "Enable VLAN 4K mode",
- .set = rtl8366rb_sw_set_vlan_enable,
- .get = rtl8366rb_sw_get_vlan_enable,
+ .set = rtl8366_sw_set_vlan_enable,
+ .get = rtl8366_sw_get_vlan_enable,
.max = 1,
.ofs = 2
}, {
.set = rtl8366rb_sw_set_blinkrate,
.get = rtl8366rb_sw_get_blinkrate,
.max = 5
+ }, {
+ .type = SWITCH_TYPE_INT,
+ .name = "enable_qos",
+ .description = "Enable QOS",
+ .set = rtl8366rb_sw_set_qos_enable,
+ .get = rtl8366rb_sw_get_qos_enable,
+ .max = 1
+ }, {
+ .type = SWITCH_TYPE_INT,
+ .name = "enable_mirror_rx",
+ .description = "Enable mirroring of RX packets",
+ .set = rtl8366rb_sw_set_mirror_rx_enable,
+ .get = rtl8366rb_sw_get_mirror_rx_enable,
+ .max = 1
+ }, {
+ .type = SWITCH_TYPE_INT,
+ .name = "enable_mirror_tx",
+ .description = "Enable mirroring of TX packets",
+ .set = rtl8366rb_sw_set_mirror_tx_enable,
+ .get = rtl8366rb_sw_get_mirror_tx_enable,
+ .max = 1
+ }, {
+ .type = SWITCH_TYPE_INT,
+ .name = "enable_monitor_isolation",
+ .description = "Enable isolation of monitor port (TX packets will be dropped)",
+ .set = rtl8366rb_sw_set_monitor_isolation_enable,
+ .get = rtl8366rb_sw_get_monitor_isolation_enable,
+ .max = 1
+ }, {
+ .type = SWITCH_TYPE_INT,
+ .name = "enable_mirror_pause_frames",
+ .description = "Enable mirroring of RX pause frames",
+ .set = rtl8366rb_sw_set_mirror_pause_frames_enable,
+ .get = rtl8366rb_sw_get_mirror_pause_frames_enable,
+ .max = 1
+ }, {
+ .type = SWITCH_TYPE_INT,
+ .name = "mirror_monitor_port",
+ .description = "Mirror monitor port",
+ .set = rtl8366rb_sw_set_mirror_monitor_port,
+ .get = rtl8366rb_sw_get_mirror_monitor_port,
+ .max = 5
+ }, {
+ .type = SWITCH_TYPE_INT,
+ .name = "mirror_source_port",
+ .description = "Mirror source port",
+ .set = rtl8366rb_sw_set_mirror_source_port,
+ .get = rtl8366rb_sw_get_mirror_source_port,
+ .max = 5
},
};
static struct switch_attr rtl8366rb_port[] = {
{
- .type = SWITCH_TYPE_STRING,
- .name = "link",
- .description = "Get port link information",
- .max = 1,
- .set = NULL,
- .get = rtl8366rb_sw_get_port_link,
- }, {
.type = SWITCH_TYPE_NOVAL,
.name = "reset_mib",
.description = "Reset single port MIB counters",
.max = 15,
.set = rtl8366rb_sw_set_port_led,
.get = rtl8366rb_sw_get_port_led,
+ }, {
+ .type = SWITCH_TYPE_INT,
+ .name = "disable",
+ .description = "Get/Set port state (enabled or disabled)",
+ .max = 1,
+ .set = rtl8366rb_sw_set_port_disable,
+ .get = rtl8366rb_sw_get_port_disable,
+ }, {
+ .type = SWITCH_TYPE_INT,
+ .name = "rate_in",
+ .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
+ .max = RTL8366RB_BDTH_SW_MAX,
+ .set = rtl8366rb_sw_set_port_rate_in,
+ .get = rtl8366rb_sw_get_port_rate_in,
+ }, {
+ .type = SWITCH_TYPE_INT,
+ .name = "rate_out",
+ .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
+ .max = RTL8366RB_BDTH_SW_MAX,
+ .set = rtl8366rb_sw_set_port_rate_out,
+ .get = rtl8366rb_sw_get_port_rate_out,
},
};
.max = 1,
.set = NULL,
.get = rtl8366_sw_get_vlan_info,
+ }, {
+ .type = SWITCH_TYPE_INT,
+ .name = "fid",
+ .description = "Get/Set vlan FID",
+ .max = RTL8366RB_FIDMAX,
+ .set = rtl8366_sw_set_vlan_fid,
+ .get = rtl8366_sw_get_vlan_fid,
},
};
.set_vlan_ports = rtl8366_sw_set_vlan_ports,
.get_port_pvid = rtl8366_sw_get_port_pvid,
.set_port_pvid = rtl8366_sw_set_port_pvid,
- .reset_switch = rtl8366rb_sw_reset_switch,
+ .reset_switch = rtl8366_sw_reset_switch,
+ .get_port_link = rtl8366rb_sw_get_port_link,
};
static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
dev->name = "RTL8366RB";
dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
dev->ports = RTL8366RB_NUM_PORTS;
- dev->vlans = RTL8366RB_NUM_VLANS;
+ dev->vlans = RTL8366RB_NUM_VIDS;
dev->ops = &rtl8366_ops;
- dev->devname = dev_name(smi->parent);
+ dev->alias = dev_name(smi->parent);
err = register_switch(dev, NULL);
if (err)
return err;
}
-static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
-{
- return (bus->read == rtl8366rb_mii_read &&
- bus->write == rtl8366rb_mii_write);
-}
-
-static int rtl8366rb_setup(struct rtl8366_smi *smi)
-{
- int ret;
-
- ret = rtl8366rb_reset_chip(smi);
- if (ret)
- return ret;
-
- ret = rtl8366rb_hw_init(smi);
- return ret;
-}
-
static int rtl8366rb_detect(struct rtl8366_smi *smi)
{
u32 chip_id = 0;
static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
.detect = rtl8366rb_detect,
+ .reset_chip = rtl8366rb_reset_chip,
.setup = rtl8366rb_setup,
.mii_read = rtl8366rb_mii_read,
.set_mc_index = rtl8366rb_set_mc_index,
.get_mib_counter = rtl8366rb_get_mib_counter,
.is_vlan_valid = rtl8366rb_is_vlan_valid,
+ .enable_vlan = rtl8366rb_enable_vlan,
+ .enable_vlan4k = rtl8366rb_enable_vlan4k,
+ .enable_port = rtl8366rb_enable_port,
};
-static int __init rtl8366rb_probe(struct platform_device *pdev)
+static int rtl8366rb_probe(struct platform_device *pdev)
{
static int rtl8366_smi_version_printed;
- struct rtl8366rb_platform_data *pdata;
struct rtl8366_smi *smi;
int err;
printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
" version " RTL8366RB_DRIVER_VER"\n");
- pdata = pdev->dev.platform_data;
- if (!pdata) {
- dev_err(&pdev->dev, "no platform data specified\n");
- err = -EINVAL;
- goto err_out;
- }
-
- smi = rtl8366_smi_alloc(&pdev->dev);
- if (!smi) {
- err = -ENOMEM;
- goto err_out;
- }
+ smi = rtl8366_smi_probe(pdev);
+ if (!smi)
+ return -ENODEV;
- smi->gpio_sda = pdata->gpio_sda;
- smi->gpio_sck = pdata->gpio_sck;
+ smi->clk_delay = 10;
+ smi->cmd_read = 0xa9;
+ smi->cmd_write = 0xa8;
smi->ops = &rtl8366rb_smi_ops;
smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
smi->num_ports = RTL8366RB_NUM_PORTS;
rtl8366_smi_cleanup(smi);
err_free_smi:
kfree(smi);
- err_out:
return err;
}
-static int rtl8366rb_phy_config_init(struct phy_device *phydev)
-{
- if (!rtl8366rb_mii_bus_match(phydev->bus))
- return -EINVAL;
-
- return 0;
-}
-
-static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
-{
- return 0;
-}
-
-static struct phy_driver rtl8366rb_phy_driver = {
- .phy_id = 0x001cc960,
- .name = "Realtek RTL8366RB",
- .phy_id_mask = 0x1ffffff0,
- .features = PHY_GBIT_FEATURES,
- .config_aneg = rtl8366rb_phy_config_aneg,
- .config_init = rtl8366rb_phy_config_init,
- .read_status = genphy_read_status,
- .driver = {
- .owner = THIS_MODULE,
- },
-};
-
-static int __devexit rtl8366rb_remove(struct platform_device *pdev)
+static int rtl8366rb_remove(struct platform_device *pdev)
{
struct rtl8366_smi *smi = platform_get_drvdata(pdev);
return 0;
}
+#ifdef CONFIG_OF
+static const struct of_device_id rtl8366rb_match[] = {
+ { .compatible = "realtek,rtl8366rb" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, rtl8366rb_match);
+#endif
+
static struct platform_driver rtl8366rb_driver = {
.driver = {
.name = RTL8366RB_DRIVER_NAME,
.owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(rtl8366rb_match),
},
.probe = rtl8366rb_probe,
- .remove = __devexit_p(rtl8366rb_remove),
+ .remove = rtl8366rb_remove,
};
static int __init rtl8366rb_module_init(void)
{
- int ret;
- ret = platform_driver_register(&rtl8366rb_driver);
- if (ret)
- return ret;
-
- ret = phy_driver_register(&rtl8366rb_phy_driver);
- if (ret)
- goto err_platform_unregister;
-
- return 0;
-
- err_platform_unregister:
- platform_driver_unregister(&rtl8366rb_driver);
- return ret;
+ return platform_driver_register(&rtl8366rb_driver);
}
module_init(rtl8366rb_module_init);
static void __exit rtl8366rb_module_exit(void)
{
- phy_driver_unregister(&rtl8366rb_phy_driver);
platform_driver_unregister(&rtl8366rb_driver);
}
module_exit(rtl8366rb_module_exit);
MODULE_VERSION(RTL8366RB_DRIVER_VER);
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
+MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
+MODULE_AUTHOR("Colin Leitner <colin.leitner@googlemail.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
projects / openwrt / staging / florian.git / blobdiff