ipq806x: 6.1: manually refresh kernel patches

[openwrt/openwrt.git] / target / linux / ipq806x / patches-6.1 / 107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch

diff --git a/target/linux/ipq806x/patches-6.1/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch b/target/linux/ipq806x/patches-6.1/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch
index 418d6b26ce7a96b2d9bd0b05d3685a680e0cb004..0417572be0205e93ddb45f90671e7fc4e9ba9c4f 100644 (file)
--- a/target/linux/ipq806x/patches-6.1/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch
+++ b/target/linux/ipq806x/patches-6.1/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch
@@ -29,7 +29,25 @@ Tested-by: Jonathan McDowell <noodles@earth.li>
                cxo_board: cxo_board {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
-@@ -503,11 +509,19 @@
+@@ -490,6 +490,17 @@
+                       clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+                       clock-names = "pll8_vote", "pxo";
+                       clock-output-names = "acpu_l2_aux";
++                      #clock-cells = <0>;
++              };
++
++              kraitcc: clock-controller {
++                      compatible = "qcom,krait-cc-v1";
++                      clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
++                               <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
++                      clock-names = "hfpll0", "hfpll1", "hfpll_l2",
++                                    "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
++                                    "qsb", "pxo";
++                      #clock-cells = <1>;
+               };
+ 
+               acc0: clock-controller@2088000 {
+@@ -503,17 +509,25 @@
                acc0: clock-controller@2088000 {
                        compatible = "qcom,kpss-acc-v1";
                        reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
@@ -39,6 +57,13 @@ Tested-by: Jonathan McDowell <noodles@earth.li>
 +                      #clock-cells = <0>;
                };
  
+               saw0: regulator@2089000 {
+-                      compatible = "qcom,saw2";
++                      compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
+                       reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+                       regulator;
+               };
+ 
                acc1: clock-controller@2098000 {
                        compatible = "qcom,kpss-acc-v1";
                        reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
@@ -48,15 +73,8 @@ Tested-by: Jonathan McDowell <noodles@earth.li>
 +                      #clock-cells = <0>;
                };
  
-               adm_dma: dma-controller@18300000 {
-@@ -531,17 +545,23 @@
-               };
- 
-               saw0: regulator@2089000 {
--                      compatible = "qcom,saw2";
-+                      compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
-                       reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
-                       regulator;
+               saw1: regulator@2099000 {
+@@ -531,11 +545,17 @@
                };
  
                saw1: regulator@2099000 {
@@ -72,24 +90,6 @@ Tested-by: Jonathan McDowell <noodles@earth.li>
 +                      regulator;
 +              };
 +
-               gsbi1: gsbi@12440000 {
-                       compatible = "qcom,gsbi-v1.0.0";
-                       reg = <0x12440000 0x100>;
-@@ -920,6 +940,17 @@
-                       clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
-                       clock-names = "pll8_vote", "pxo";
-                       clock-output-names = "acpu_l2_aux";
-+                      #clock-cells = <0>;
-+              };
-+
-+              kraitcc: clock-controller {
-+                      compatible = "qcom,krait-cc-v1";
-+                      clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
-+                               <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
-+                      clock-names = "hfpll0", "hfpll1", "hfpll_l2",
-+                                    "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
-+                                    "qsb", "pxo";
-+                      #clock-cells = <1>;
-               };
- 
-               lcc: clock-controller@28000000 {
+               nss_common: syscon@03000000 {
+                       compatible = "syscon";
+                       reg = <0x03000000 0x0000FFFF>;