ipq806x: convert each device to DSA implementation
[openwrt/openwrt.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8064-wxr-2533dhp.dts
index 39fd81fe5537f38cb5fe93400c6c80c023bb3606..97d76e11f0d1471a4747b4e500768afe20496eee 100644 (file)
        pinctrl-0 = <&mdio0_pins>;
        pinctrl-names = "default";
 
-       ethernet-phy@0 {
-               reg = <0>;
-               qca,ar8327-initvals = <
-                       0x00004 0x07600000  /* PAD0_MODE */
-                       0x00008 0x01000000  /* PAD5_MODE */
-                       0x0000c 0x00000080  /* PAD6_MODE */
-                       0x00050 0xcc35cc35  /* LED_CTRL0 */
-                       0x00054 0xca35ca35  /* LED_CTRL1 */
-                       0x00058 0xc935c935  /* LED_CTRL2 */
-                       0x0005c 0x03ffff00  /* LED_CTRL3 */
-                       0x000e4 0x0006a545  /* MAC_POWER_SEL */
-                       0x000e0 0xc74164de  /* SGMII_CTRL */
-                       0x0007c 0x0000007e  /* PORT0_STATUS */
-                       0x00094 0x0000007e  /* PORT6_STATUS */
-                       >;
-       };
+       switch@10 {
+               compatible = "qca,qca8337";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0x10>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               label = "cpu";
+                               ethernet = <&gmac1>;
+                               phy-mode = "rgmii";
+                               tx-internal-delay-ps = <1000>;
+                               rx-internal-delay-ps = <1000>;
+
+                               fixed-link {
+                                       speed = <1000>;
+                                       full-duplex;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                               label = "lan1";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port1>;
+                       };
+
+                       port@2 {
+                               reg = <2>;
+                               label = "lan2";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port2>;
+                       };
+
+                       port@3 {
+                               reg = <3>;
+                               label = "lan3";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port3>;
+                       };
+
+                       port@4 {
+                               reg = <4>;
+                               label = "lan4";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port4>;
+                       };
+
+                       port@5 {
+                               reg = <5>;
+                               label = "wan";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port5>;
+                       };
 
-       ethernet-phy@4 {
-               reg = <4>;
+                       /*
+                       port@6 {
+                               reg = <0>;
+                               label = "cpu";
+                               ethernet = <&gmac2>;
+                               phy-mode = "rgmii";
+
+                               fixed-link {
+                                       speed = <1000>;
+                                       full-duplex;
+                                       pause;
+                                       asym-pause;
+                               };
+                       };
+                       */
+               };
+
+               mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       phy_port1: phy@0 {
+                               reg = <0>;
+                       };
+
+                       phy_port2: phy@1 {
+                               reg = <1>;
+                       };
+
+                       phy_port3: phy@2 {
+                               reg = <2>;
+                       };
+
+                       phy_port4: phy@3 {
+                               reg = <3>;
+                       };
+
+                       phy_port5: phy@4 {
+                               reg = <4>;
+                       };
+               };
        };
 };